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Searched refs:SLCR_REG (Results 1 – 5 of 5) sorted by relevance

/lk-master/platform/zynq/
A Dplatform.c70 SLCR_REG(ARM_PLL_CTRL) &= ~PLL_RESET; in zynq_pll_init()
83 SLCR_REG(DDR_PLL_CTRL) &= ~PLL_RESET; in zynq_pll_init()
93 SLCR_REG(DDR_CLK_CTRL) = 0; in zynq_pll_init()
94 SLCR_REG(DDR_PLL_CTRL) |= PLL_PWRDOWN; in zynq_pll_init()
99 SLCR_REG(IO_PLL_CTRL) &= ~PLL_RESET; in zynq_pll_init()
115 SLCR_REG(GPIOB_CTRL) = GPIOB_CTRL_VREF_EN; in zynq_mio_init()
169 SLCR_REG(DDRIOB_DDR_CTRL) = 0x00000E60U; in zynq_ddr_init()
170 SLCR_REG(DDRIOB_DCI_CTRL) = 0x00000001U; in zynq_ddr_init()
171 SLCR_REG(DDRIOB_DCI_CTRL) |= 0x00000020U; in zynq_ddr_init()
334 SLCR_REG(LVL_SHFTR_EN) = 0xF; in platform_early_init()
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A Dclocks.c23 LTRACEF("ARM_PLL_CTRL 0x%x\n", SLCR_REG(ARM_PLL_CTRL)); in get_arm_pll_freq()
27 uint32_t fdiv = BITS_SHIFT(SLCR_REG(ARM_PLL_CTRL), 18, 12); in get_arm_pll_freq()
33 LTRACEF("DDR_PLL_CTRL 0x%x\n", SLCR_REG(DDR_PLL_CTRL)); in get_ddr_pll_freq()
37 uint32_t fdiv = BITS_SHIFT(SLCR_REG(DDR_PLL_CTRL), 18, 12); in get_ddr_pll_freq()
43 LTRACEF("IO_PLL_CTRL 0x%x\n", SLCR_REG(IO_PLL_CTRL)); in get_io_pll_freq()
47 uint32_t fdiv = BITS_SHIFT(SLCR_REG(IO_PLL_CTRL), 18, 12); in get_io_pll_freq()
53 LTRACEF("ARM_CLK_CTRL 0x%x\n", SLCR_REG(ARM_CLK_CTRL)); in get_cpu_input_freq()
55 uint32_t divisor = BITS_SHIFT(SLCR_REG(ARM_CLK_CTRL), 13, 8); in get_cpu_input_freq()
56 uint32_t srcsel = BITS_SHIFT(SLCR_REG(ARM_CLK_CTRL), 5, 4); in get_cpu_input_freq()
89 return get_cpu_input_freq() / ((SLCR_REG(CLK_621_TRUE) & 1) ? 3 : 2); in get_cpu_2x_freq()
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A Dgpio.c156 uint32_t mio_cfg = SLCR_REG(MIO_PIN_00 + (gpio * 4)); in gpio_config()
169 SLCR_REG(MIO_PIN_00 + (gpio * 4)) = mio_cfg; in gpio_config()
A Dgem.c485 SLCR_REG(GPIOB_CTRL) = 0x1; in gem_init()
/lk-master/platform/zynq/include/platform/
A Dzynq.h362 #define SLCR_REG(reg) (*REG32((uintptr_t)&SLCR->reg)) macro

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