1 /*
2 * Copyright (c) 2014 Travis Geiselbrecht
3 *
4 * Use of this source code is governed by a MIT-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/MIT
7 */
8 #pragma once
9
10 #define ZYNQ_MIO_CNT 54
11
12 /* memory addresses */
13 /* assumes sram is mapped at 0 the first MB of sdram is covered by it */
14 #define SDRAM_BASE (0x00100000)
15 #define SDRAM_APERTURE_SIZE (0x3ff00000)
16 #define SRAM_BASE (0x0)
17 #define SRAM_BASE_HIGH (0xfffc0000)
18 #define SRAM_APERTURE_SIZE (0x00040000)
19 #define SRAM_SIZE (0x00040000)
20
21 /* hardware base addresses */
22 #define UART0_BASE (0xe0000000)
23 #define UART1_BASE (0xe0001000)
24 #define USB0_BASE (0xe0002000)
25 #define USB1_BASE (0xe0003000)
26 #define I2C0_BASE (0xe0004000)
27 #define I2C1_BASE (0xe0005000)
28 #define SPI0_BASE (0xe0006000)
29 #define SPI1_BASE (0xe0007000)
30 #define CAN0_BASE (0xe0008000)
31 #define CAN1_BASE (0xe0009000)
32 #define GPIO_BASE (0xe000a000)
33 #define GEM0_BASE (0xe000b000) // gigabit eth controller
34 #define GEM1_BASE (0xe000c000) // ""
35 #define QSPI_BASE (0xe000d000)
36 #define SMCC_BASE (0xe000e000) // PL353 shared memory controller
37
38 #define SD0_BASE (0xe0100000)
39 #define SD1_BASE (0xe0101000)
40
41 #define SLCR_BASE (0xf8000000)
42 #define TTC0_BASE (0xf8001000)
43 #define TTC1_BASE (0xf8002000)
44 #define DMAC0_NS_BASE (0xf8004000)
45 #define DMAC0_S_BASE (0xf8003000)
46 #define SWDT_BASE (0xf8005000)
47
48 #define CPUPRIV_BASE (0xf8f00000)
49 #define SCU_CONTROL_BASE (CPUPRIV_BASE + 0x0000)
50 #define GIC_PROC_BASE (CPUPRIV_BASE + 0x0100)
51 #define GLOBAL_TIMER_BASE (CPUPRIV_BASE + 0x0200)
52 #define PRIV_TIMER_BASE (CPUPRIV_BASE + 0x0600)
53 #define GIC_DISTRIB_BASE (CPUPRIV_BASE + 0x1000)
54 #define L2CACHE_BASE (CPUPRIV_BASE + 0x2000)
55
56 #define QSPI_LINEAR_BASE (0xfc000000)
57
58 /* interrupts */
59 #define TTC0_A_INT 42
60 #define TTC0_B_INT 43
61 #define TTC0_C_INT 44
62 #define GPIO_INT 52
63 #define USB0_INT 53
64 #define ETH0_INT 54
65 #define ETH0_WAKE_INT 55
66 #define SDIO0_INT 56
67 #define I2C0_INT 57
68 #define SPI0_INT 58
69 #define UART0_INT 59
70 #define UART1_INT 82
71 #define TTC1_A_INT 69
72 #define TTC2_B_INT 70
73 #define TTC3_C_INT 71
74 #define ETH1_INT 77
75 #define ETH1_WAKE_INT 78
76
77 /* Perhipheral IRQs from fabric */
78 #define F2P0_IRQ 61
79 #define F2P1_IRQ 62
80 #define F2P2_IRQ 63
81 #define F2P3_IRQ 64
82 #define F2P4_IRQ 65
83 #define F2P5_IRQ 66
84 #define F2P6_IRQ 67
85 #define F2P7_IRQ 68
86
87 #define F2P8_IRQ 84
88 #define F2P9_IRQ 85
89 #define F2P10_IRQ 86
90 #define F2P11_IRQ 87
91 #define F2P12_IRQ 88
92 #define F2P13_IRQ 89
93 #define F2P14_IRQ 90
94 #define F2P15_IRQ 91
95
96 #define MAX_INT 96
97
98 #ifndef ASSEMBLY
99
100 #include <lk/reg.h>
101 #include <lk/compiler.h>
102 #include <lk/bits.h>
103 #include <stdbool.h>
104 #include <sys/types.h>
105
106 /* Configuration values for each of the system PLLs. Refer to the TRM 25.10.4 */
107 typedef struct {
108 uint32_t lock_cnt;
109 uint32_t cp;
110 uint32_t res;
111 uint32_t fdiv;
112 } zynq_pll_cfg_t;
113
114 typedef struct {
115 uint32_t arm_clk;
116 uint32_t ddr_clk;
117 uint32_t dci_clk;
118 uint32_t gem0_clk;
119 uint32_t gem0_rclk;
120 uint32_t gem1_clk;
121 uint32_t gem1_rclk;
122 uint32_t smc_clk;
123 uint32_t lqspi_clk;
124 uint32_t sdio_clk;
125 uint32_t uart_clk;
126 uint32_t spi_clk;
127 uint32_t can_clk;
128 uint32_t can_mioclk;
129 uint32_t usb0_clk;
130 uint32_t usb1_clk;
131 uint32_t pcap_clk;
132 uint32_t fpga0_clk;
133 uint32_t fpga1_clk;
134 uint32_t fpga2_clk;
135 uint32_t fpga3_clk;
136 uint32_t aper_clk;
137 uint32_t clk_621_true;
138 } zynq_clk_cfg_t;
139
140 typedef struct {
141 zynq_pll_cfg_t arm;
142 zynq_pll_cfg_t ddr;
143 zynq_pll_cfg_t io;
144 } zynq_pll_cfg_tree_t;
145
146 /* Configuration for the DDR controller and buffers. TRM Ch 10 */
147 typedef struct {
148 uint32_t addr0;
149 uint32_t addr1;
150 uint32_t data0;
151 uint32_t data1;
152 uint32_t diff0;
153 uint32_t diff1;
154 bool ibuf_disable;
155 bool term_disable;
156 } zynq_ddriob_cfg_t;;
157
158 /* SLCR registers */
159 struct slcr_regs {
160 uint32_t SCL; // Secure Configuration Lock
161 uint32_t SLCR_LOCK; // SLCR Write Protection Lock
162 uint32_t SLCR_UNLOCK; // SLCR Write Protection Unlock
163 uint32_t SLCR_LOCKSTA; // SLCR Write Protection Status
164 uint32_t ___reserved0[60];
165 uint32_t ARM_PLL_CTRL; // ARM PLL Control
166 uint32_t DDR_PLL_CTRL; // DDR PLL Control
167 uint32_t IO_PLL_CTRL; // IO PLL Control
168 uint32_t PLL_STATUS; // PLL Status
169 uint32_t ARM_PLL_CFG; // ARM PLL Configuration
170 uint32_t DDR_PLL_CFG; // DDR PLL Configuration
171 uint32_t IO_PLL_CFG; // IO PLL Configuration
172 uint32_t ___reserved1[1];
173 uint32_t ARM_CLK_CTRL; // CPU Clock Control
174 uint32_t DDR_CLK_CTRL; // DDR Clock Control
175 uint32_t DCI_CLK_CTRL; // DCI clock control
176 uint32_t APER_CLK_CTRL; // AMBA Peripheral Clock Control
177 uint32_t USB0_CLK_CTRL; // USB 0 ULPI Clock Control
178 uint32_t USB1_CLK_CTRL; // USB 1 ULPI Clock Control
179 uint32_t GEM0_RCLK_CTRL; // GigE 0 Rx Clock and Rx Signals Select
180 uint32_t GEM1_RCLK_CTRL; // GigE 1 Rx Clock and Rx Signals Select
181 uint32_t GEM0_CLK_CTRL; // GigE 0 Ref Clock Control
182 uint32_t GEM1_CLK_CTRL; // GigE 1 Ref Clock Control
183 uint32_t SMC_CLK_CTRL; // SMC Ref Clock Control
184 uint32_t LQSPI_CLK_CTRL; // Quad SPI Ref Clock Control
185 uint32_t SDIO_CLK_CTRL; // SDIO Ref Clock Control
186 uint32_t UART_CLK_CTRL; // UART Ref Clock Control
187 uint32_t SPI_CLK_CTRL; // SPI Ref Clock Control
188 uint32_t CAN_CLK_CTRL; // CAN Ref Clock Control
189 uint32_t CAN_MIOCLK_CTRL; // CAN MIO Clock Control
190 uint32_t DBG_CLK_CTRL; // SoC Debug Clock Control
191 uint32_t PCAP_CLK_CTRL; // PCAP Clock Control
192 uint32_t TOPSW_CLK_CTRL; // Central Interconnect Clock Control
193 uint32_t FPGA0_CLK_CTRL; // PL Clock 0 Output control
194 uint32_t FPGA0_THR_CTRL; // PL Clock 0 Throttle control
195 uint32_t FPGA0_THR_CNT; // PL Clock 0 Throttle Count control
196 uint32_t FPGA0_THR_STA; // PL Clock 0 Throttle Status read
197 uint32_t FPGA1_CLK_CTRL; // PL Clock 1 Output control
198 uint32_t FPGA1_THR_CTRL; // PL Clock 1 Throttle control
199 uint32_t FPGA1_THR_CNT; // PL Clock 1 Throttle Count
200 uint32_t FPGA1_THR_STA; // PL Clock 1 Throttle Status control
201 uint32_t FPGA2_CLK_CTRL; // PL Clock 2 output control
202 uint32_t FPGA2_THR_CTRL; // PL Clock 2 Throttle Control
203 uint32_t FPGA2_THR_CNT; // PL Clock 2 Throttle Count
204 uint32_t FPGA2_THR_STA; // PL Clock 2 Throttle Status
205 uint32_t FPGA3_CLK_CTRL; // PL Clock 3 output control
206 uint32_t FPGA3_THR_CTRL; // PL Clock 3 Throttle Control
207 uint32_t FPGA3_THR_CNT; // PL Clock 3 Throttle Count
208 uint32_t FPGA3_THR_STA; // PL Clock 3 Throttle Status
209 uint32_t ___reserved2[5];
210 uint32_t CLK_621_TRUE; // CPU Clock Ratio Mode select
211 uint32_t ___reserved3[14];
212 uint32_t PSS_RST_CTRL; // PS Software Reset Control
213 uint32_t DDR_RST_CTRL; // DDR Software Reset Control
214 uint32_t TOPSW_RST_CTRL; // Central Interconnect Reset Control
215 uint32_t DMAC_RST_CTRL; // DMAC Software Reset Control
216 uint32_t USB_RST_CTRL; // USB Software Reset Control
217 uint32_t GEM_RST_CTRL; // Gigabit Ethernet SW Reset Control
218 uint32_t SDIO_RST_CTRL; // SDIO Software Reset Control
219 uint32_t SPI_RST_CTRL; // SPI Software Reset Control
220 uint32_t CAN_RST_CTRL; // CAN Software Reset Control
221 uint32_t I2C_RST_CTRL; // I2C Software Reset Control
222 uint32_t UART_RST_CTRL; // UART Software Reset Control
223 uint32_t GPIO_RST_CTRL; // GPIO Software Reset Control
224 uint32_t LQSPI_RST_CTRL; // Quad SPI Software Reset Control
225 uint32_t SMC_RST_CTRL; // SMC Software Reset Control
226 uint32_t OCM_RST_CTRL; // OCM Software Reset Control
227 uint32_t ___reserved4[1];
228 uint32_t FPGA_RST_CTRL; // FPGA Software Reset Control
229 uint32_t A9_CPU_RST_CTRL; // CPU Reset and Clock control
230 uint32_t ___reserved5[1];
231 uint32_t RS_AWDT_CTRL; // Watchdog Timer Reset Control
232 uint32_t ___reserved6[2];
233 uint32_t REBOOT_STATUS; // Reboot Status, persistent
234 uint32_t BOOT_MODE; // Boot Mode Strapping Pins
235 uint32_t ___reserved7[40];
236 uint32_t APU_CTRL; // APU Control
237 uint32_t WDT_CLK_SEL; // SWDT clock source select
238 uint32_t ___reserved8[78];
239 uint32_t TZ_DMA_NS; // DMAC TrustZone Config
240 uint32_t TZ_DMA_IRQ_NS; // DMAC TrustZone Config for Interrupts
241 uint32_t TZ_DMA_PERIPH_NS; // DMAC TrustZone Config for Peripherals
242 uint32_t ___reserved9[57];
243 uint32_t PSS_IDCODE; // PS IDCODE
244 uint32_t ___reserved10[51];
245 uint32_t DDR_URGENT; // DDR Urgent Control
246 uint32_t ___reserved11[2];
247 uint32_t DDR_CAL_START; // DDR Calibration Start Triggers
248 uint32_t ___reserved12[1];
249 uint32_t DDR_REF_START; // DDR Refresh Start Triggers
250 uint32_t DDR_CMD_STA; // DDR Command Store Status
251 uint32_t DDR_URGENT_SEL; // DDR Urgent Select
252 uint32_t DDR_DFI_STATUS; // DDR DFI status
253 uint32_t ___reserved13[55];
254 uint32_t MIO_PIN_00; // MIO Pin 0 Control
255 uint32_t MIO_PIN_01; // MIO Pin 1 Control
256 uint32_t MIO_PIN_02; // MIO Pin 2 Control
257 uint32_t MIO_PIN_03; // MIO Pin 3 Control
258 uint32_t MIO_PIN_04; // MIO Pin 4 Control
259 uint32_t MIO_PIN_05; // MIO Pin 5 Control
260 uint32_t MIO_PIN_06; // MIO Pin 6 Control
261 uint32_t MIO_PIN_07; // MIO Pin 7 Control
262 uint32_t MIO_PIN_08; // MIO Pin 8 Control
263 uint32_t MIO_PIN_09; // MIO Pin 9 Control
264 uint32_t MIO_PIN_10; // MIO Pin 10 Control
265 uint32_t MIO_PIN_11; // MIO Pin 11 Control
266 uint32_t MIO_PIN_12; // MIO Pin 12 Control
267 uint32_t MIO_PIN_13; // MIO Pin 13 Control
268 uint32_t MIO_PIN_14; // MIO Pin 14 Control
269 uint32_t MIO_PIN_15; // MIO Pin 15 Control
270 uint32_t MIO_PIN_16; // MIO Pin 16 Control
271 uint32_t MIO_PIN_17; // MIO Pin 17 Control
272 uint32_t MIO_PIN_18; // MIO Pin 18 Control
273 uint32_t MIO_PIN_19; // MIO Pin 19 Control
274 uint32_t MIO_PIN_20; // MIO Pin 20 Control
275 uint32_t MIO_PIN_21; // MIO Pin 21 Control
276 uint32_t MIO_PIN_22; // MIO Pin 22 Control
277 uint32_t MIO_PIN_23; // MIO Pin 23 Control
278 uint32_t MIO_PIN_24; // MIO Pin 24 Control
279 uint32_t MIO_PIN_25; // MIO Pin 25 Control
280 uint32_t MIO_PIN_26; // MIO Pin 26 Control
281 uint32_t MIO_PIN_27; // MIO Pin 27 Control
282 uint32_t MIO_PIN_28; // MIO Pin 28 Control
283 uint32_t MIO_PIN_29; // MIO Pin 29 Control
284 uint32_t MIO_PIN_30; // MIO Pin 30 Control
285 uint32_t MIO_PIN_31; // MIO Pin 31 Control
286 uint32_t MIO_PIN_32; // MIO Pin 32 Control
287 uint32_t MIO_PIN_33; // MIO Pin 33 Control
288 uint32_t MIO_PIN_34; // MIO Pin 34 Control
289 uint32_t MIO_PIN_35; // MIO Pin 35 Control
290 uint32_t MIO_PIN_36; // MIO Pin 36 Control
291 uint32_t MIO_PIN_37; // MIO Pin 37 Control
292 uint32_t MIO_PIN_38; // MIO Pin 38 Control
293 uint32_t MIO_PIN_39; // MIO Pin 39 Control
294 uint32_t MIO_PIN_40; // MIO Pin 40 Control
295 uint32_t MIO_PIN_41; // MIO Pin 41 Control
296 uint32_t MIO_PIN_42; // MIO Pin 42 Control
297 uint32_t MIO_PIN_43; // MIO Pin 43 Control
298 uint32_t MIO_PIN_44; // MIO Pin 44 Control
299 uint32_t MIO_PIN_45; // MIO Pin 45 Control
300 uint32_t MIO_PIN_46; // MIO Pin 46 Control
301 uint32_t MIO_PIN_47; // MIO Pin 47 Control
302 uint32_t MIO_PIN_48; // MIO Pin 48 Control
303 uint32_t MIO_PIN_49; // MIO Pin 49 Control
304 uint32_t MIO_PIN_50; // MIO Pin 50 Control
305 uint32_t MIO_PIN_51; // MIO Pin 51 Control
306 uint32_t MIO_PIN_52; // MIO Pin 52 Control
307 uint32_t MIO_PIN_53; // MIO Pin 53 Control
308 uint32_t ___reserved14[11];
309 uint32_t MIO_LOOPBACK; // Loopback function within MIO
310 uint32_t ___reserved15[1];
311 uint32_t MIO_MST_TRI0; // MIO pin Tri-state Enables, 31:0
312 uint32_t MIO_MST_TRI1; // MIO pin Tri-state Enables, 53:32
313 uint32_t ___reserved16[7];
314 uint32_t SD0_WP_CD_SEL; // SDIO 0 WP CD select
315 uint32_t SD1_WP_CD_SEL; // SDIO 1 WP CD select
316 uint32_t ___reserved17[50];
317 uint32_t LVL_SHFTR_EN; // Level Shifters Enable
318 uint32_t ___reserved18[3];
319 uint32_t OCM_CFG; // OCM Address Mapping
320 uint32_t ___reserved19[66];
321 uint32_t RESERVED; // Reserved
322 uint32_t ___reserved20[56];
323 uint32_t GPIOB_CTRL; // PS IO Buffer Control
324 uint32_t GPIOB_CFG_CMOS18; // MIO GPIOB CMOS 1.8V config
325 uint32_t GPIOB_CFG_CMOS25; // MIO GPIOB CMOS 2.5V config
326 uint32_t GPIOB_CFG_CMOS33; // MIO GPIOB CMOS 3.3V config
327 uint32_t ___reserved21[1];
328 uint32_t GPIOB_CFG_HSTL; // MIO GPIOB HSTL config
329 uint32_t GPIOB_DRVR_BIAS_CTRL; // MIO GPIOB Driver Bias Control
330 uint32_t ___reserved22[9];
331 uint32_t DDRIOB_ADDR0; // DDR IOB Config for A[14:0], CKE and DRST_B
332 uint32_t DDRIOB_ADDR1; // DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B
333 uint32_t DDRIOB_DATA0; // DDR IOB Config for Data 15:0
334 uint32_t DDRIOB_DATA1; // DDR IOB Config for Data 31:16
335 uint32_t DDRIOB_DIFF0; // DDR IOB Config for DQS 1:0
336 uint32_t DDRIOB_DIFF1; // DDR IOB Config for DQS 3:2
337 uint32_t DDRIOB_CLOCK; // DDR IOB Config for Clock Output
338 uint32_t DDRIOB_DRIVE_SLEW_ADDR; // Drive and Slew controls for Address and Command pins of the DDR Interface
339 uint32_t DDRIOB_DRIVE_SLEW_DATA; // Drive and Slew controls for DQ pins of the DDR Interface
340 uint32_t DDRIOB_DRIVE_SLEW_DIFF; // Drive and Slew controls for DQS pins of the DDR Interface
341 uint32_t DDRIOB_DRIVE_SLEW_CLOCK; // Drive and Slew controls for Clock pins of the DDR Interface
342 uint32_t DDRIOB_DDR_CTRL; // DDR IOB Buffer Control
343 uint32_t DDRIOB_DCI_CTRL; // DDR IOB DCI Config
344 uint32_t DDRIOB_DCI_STATUS; // DDR IO Buffer DCI Status
345 };
346
347 /* Verify the entries match the TRM offset to validate the struct */
348 STATIC_ASSERT(offsetof(struct slcr_regs, SCL) == 0x0);
349 STATIC_ASSERT(offsetof(struct slcr_regs, DDRIOB_DCI_STATUS) == 0xb74);
350
351 #define DDRC_CTRL 0xF8006000
352 #define DDRC_MODE_STATUS 0xF8006054
353
354 #define DDRC_CTRL_OUT_OF_RESET (1)
355 #define DDRC_CTRL_BUS_WIDTH_16BIT (1 << 2)
356 #define DDRC_CTRL_RDRW_IDLE_GAP(x) ((x & BIT_MASK(7) << 7)
357
358 #define DDRC_STS_OPER_MODE(x) (x & BIT_MASK(3))
359 #define DDRC_STS_SELF_REFRESH DDRC_STS_OPER_MODE(0x3)
360
361 #define SLCR ((volatile struct slcr_regs *)SLCR_BASE)
362 #define SLCR_REG(reg) (*REG32((uintptr_t)&SLCR->reg))
363
364 /* ARM_PLL_CFG */
365 #define PLL_CFG_PLL_RES(x) ((x & BIT_MASK(4)) << 4)
366 #define PLL_CFG_PLL_CP(x) ((x & BIT_MASK(4)) << 8)
367 #define PLL_CFG_LOCK_CNT(x) ((x & BIT_MASK(10)) << 12)
368
369 /* DDR_PLL_CFG */
370
371 /* ARM_PLL_CTRL and IO_PLL_CTRL */
372 #define PLL_RESET (1)
373 #define PLL_PWRDOWN (1 << 1)
374 #define PLL_BYPASS_QUAL (1 << 3)
375 #define PLL_BYPASS_FORCE (1 << 4)
376 #define PLL_FDIV(x) ((x & BIT_MASK(7)) << 12)
377
378 /* ARM_CLK_CTRL */
379 #define ARM_CLK_CTRL_SRCSEL(x) ((x & BIT_MASK(2)) << 4)
380 #define ARM_CLK_CTRL_DIVISOR(x) ((x & BIT_MASK(6)) << 8)
381 #define ARM_CLK_CTRL_CPU_6OR4XCLKACT (1 << 24)
382 #define ARM_CLK_CTRL_CPU_3OR2XCLKACT (1 << 25)
383 #define ARM_CLK_CTRL_CPU_2XCLKACT (1 << 26)
384 #define ARM_CLK_CTRL_CPU_1XCLKACT (1 << 27)
385 #define ARM_CLK_CTRL_PERI_CLKACT (1 << 28)
386
387 /* DDR_CLK_CTRL */
388 #define DDR_CLK_CTRL_DDR_3XCLKACT (1)
389 #define DDR_CLK_CTRL_DDR_2XCLKACT (1 << 1)
390 #define DDR_CLK_CTRL_DDR_3XCLK_DIV(x) ((x & BIT_MASK(6)) << 20)
391 #define DDR_CLK_CTRL_DDR_2XCLK_DIV(x) ((x & BIT_MASK(6)) << 26)
392
393 /* PLL_STATUS */
394 #define PLL_STATUS_ARM_PLL_LOCK (1)
395 #define PLL_STATUS_DDR_PLL_LOCK (1 << 1)
396 #define PLL_STATUS_IO_PLL_LOCK (1 << 2)
397 #define PLL_STATUS_ARM_PLL_STABLE (1 << 3)
398 #define PLL_STATUS_DDR_PLL_STABLE (1 << 4)
399 #define PLL_STATUS_IO_PLL_STABLE (1 << 5)
400
401 /* Generic clock control */
402 #define CLK_CTRL_CLKACT (1)
403 #define CLK_CTRL_CLKACT1 (1 << 1)
404 #define CLK_CTRL_SRCSEL(x) ((x & BIT_MASK(2)) << 4)
405 #define CLK_CTRL_DIVISOR0(x) ((x & BIT_MASK(6)) << 8)
406 #define CLK_CTRL_DIVISOR1(x) ((x & BIT_MASK(6)) << 20)
407
408 /* GEM clock control */
409 #define GEM_CLK_CTRL_SRCSEL(x) ((x & BIT_MASK(3)) << 4)
410
411 /* CLK 621 just has a single enable bit */
412 #define CLK_621_ENABLE (1)
413
414 /* AMBA Peripheral Clock Control */
415 #define SMC_CPU_CLK_EN (1 << 24)
416 #define LQSPI_CPU_CLK_EN (1 << 23)
417 #define GPIO_CPU_CLK_EN (1 << 22)
418 #define UART1_CPU_CLK_EN (1 << 21)
419 #define UART0_CPU_CLK_EN (1 << 20)
420 #define I2C1_CPU_CLK_EN (1 << 19)
421 #define I2C0_CPU_CLK_EN (1 << 18)
422 #define CAN1_CPU_CLK_EN (1 << 17)
423 #define CAN0_CPU_CLK_EN (1 << 16)
424 #define SPI1_CPU_CLK_EN (1 << 15)
425 #define SPI0_CPU_CLK_EN (1 << 14)
426 #define SDI1_CPU_CLK_EN (1 << 11)
427 #define SDI0_CPU_CLK_EN (1 << 10)
428 #define GEM1_CPU_CLK_EN (1 << 7)
429 #define GEM0_CPU_CLK_EN (1 << 6)
430 #define USB1_CPU_CLK_EN (1 << 3)
431 #define USB0_CPU_CLK_EN (1 << 2)
432 #define DMA_CPU_CLK_EN (1 << 0)
433
434 /* GPIOB_CTRL */
435 #define GPIOB_CTRL_VREF_09_EN (1 << 4)
436 #define GPIOB_CTRL_VREF_EN (1)
437
438 /* DDRIOB_ADDR */
439 #define DDRIOB_PULLUP_EN (1 << 11)
440 #define DDRIOB_OUTPUT_EN(x) ((x & BIT_MASK(2)) << 9)
441 #define DDRIOB_TERM_DISABLE_MODE (1 << 8)
442 #define DDRIOB_IBUF_DISABLE_MODE (1 << 7)
443 #define DDRIOB_DCI_TYPE(x) ((x & BIT_MASK(2)) << 5)
444 #define DDRIOB_TERM_EN (1 << 4)
445 #define DDRIOB_DCI_UPDATE_B (1 << 3)
446 #define DDRIOB_INP_TYPE(x) ((x & BIT_MASK(2)) << 1)
447
448 /* SD1_WP_CD_SEL */
449 #define SDIO0_WP_SEL(x) (x & BIT_MASK(6))
450 #define SDIO0_CD_SEL(x) ((x & BIT_MASK(6)) << 16)
451
452 /* MIO pin configuration */
453 #define MIO_TRI_ENABLE (1)
454 #define MIO_L0_SEL (1 << 1)
455 #define MIO_L1_SEL (1 << 2)
456 #define MIO_L2_SEL(x) ((x & BIT_MASK(2)) << 3)
457 #define MIO_L2_SEL_MASK MIO_L2_SEL(0x3)
458 #define MIO_L3_SEL(x) ((x & BIT_MASK(3)) << 5)
459 #define MIO_L3_SEL_MASK MIO_L3_SEL(0x7)
460 #define MIO_SPEED_FAST (1 << 8)
461 #define MIO_IO_TYPE_LVCMOS18 (0x1 << 9)
462 #define MIO_IO_TYPE_LVCMOS25 (0x2 << 9)
463 #define MIO_IO_TYPE_LVCMOS33 (0x3 << 9)
464 #define MIO_IO_TYPE_HSTL (0x4 << 9)
465 #define MIO_IO_TYPE_MASK (0x7 << 9)
466 #define MIO_PULLUP (1 << 12)
467 #define MIO_DISABLE_RCVR (1 << 13)
468 #define MIO_DEFAULT (0xFFFF0000)
469
470 /* UART registers */
471 #define UART_CR (0x00)
472 #define UART_MR (0x04)
473 #define UART_IER (0x08)
474 #define UART_IDR (0x0c)
475 #define UART_IMR (0x10)
476 #define UART_ISR (0x14)
477 #define UART_BAUDGEN (0x18)
478 #define UART_RXTOUT (0x1c)
479 #define UART_RXWM (0x20)
480 #define UART_MODEMCR (0x24)
481 #define UART_MODEMSR (0x28)
482 #define UART_SR (0x2c)
483 #define UART_FIFO (0x30)
484 #define UART_BAUD_DIV (0x34)
485 #define UART_FLOW_DELAY (0x38)
486 #define UART_TX_FIFO_TRIGGER (0x44)
487
488 #define NUM_UARTS 2
489
490 #define UART_CR_RXRES (1)
491 #define UART_CR_TXRES (1 << 1)
492 #define UART_CR_RXEN (1 << 2)
493 #define UART_CR_RXDIS (1 << 3)
494 #define UART_CR_TXEN (1 << 4)
495 #define UART_CR_TXDIS (1 << 5)
496 #define UART_CR_RSTTO (1 << 6)
497 #define UART_CR_STTBRK (1 << 7)
498 #define UART_CR_STPBRK (1 << 8)
499
500 #define UART_MR_CLKS_DIV8 (1)
501 #define UART_MR_CHRL(x) ((x & BIT_MASK(2)) << 1)
502 #define UART_MR_PAR(x) ((x & BIT_MASK(3)) << 3)
503 #define UART_MR_NBSTOP(x) ((x & BIT_MASK(2)) << 6)
504 #define UART_MR_CHMODE(x) ((x & BIT_MASK(2)) << 8)
505
506 #define UART_BRG_DIV(x) (x & BIT_MASK(16))
507 #define UART_BRD_DIV(x) (x & BIT_MASK(8))
508
509 /* system watchdog timer */
510 struct swdt_regs {
511 uint32_t MODE;
512 uint32_t CONTROL;
513 uint32_t RESTART;
514 uint32_t STATUS;
515 };
516
517 #define SWDT ((volatile struct swdt_regs *)SWDT_BASE)
518 #define SWDT_REG(reg) (*REG32((uintptr_t)&SWDT->reg))
519
520 /* zynq specific functions */
zynq_slcr_unlock(void)521 static inline void zynq_slcr_unlock(void) { SLCR->SLCR_UNLOCK = 0xdf0d; }
zynq_slcr_lock(void)522 static inline void zynq_slcr_lock(void) { SLCR->SLCR_LOCK = 0x767b; }
523
524 uint32_t zynq_get_arm_freq(void);
525 uint32_t zynq_get_arm_timer_freq(void);
526 uint32_t zynq_get_swdt_freq(void);
527 void zynq_dump_clocks(void);
528
529 enum zynq_clock_source {
530 PLL_IO = 0,
531 PLL_CPU = 2,
532 PLL_DDR = 3,
533 };
534
535 enum zynq_periph {
536 PERIPH_USB0,
537 PERIPH_USB1,
538 PERIPH_GEM0,
539 PERIPH_GEM1,
540 PERIPH_SMC,
541 PERIPH_LQSPI,
542 PERIPH_SDIO0,
543 PERIPH_SDIO1,
544 PERIPH_UART0,
545 PERIPH_UART1,
546 PERIPH_SPI0,
547 PERIPH_SPI1,
548 PERIPH_CAN0,
549 PERIPH_CAN1,
550 PERIPH_DBG,
551 PERIPH_PCAP,
552 PERIPH_FPGA0,
553 PERIPH_FPGA1,
554 PERIPH_FPGA2,
555 PERIPH_FPGA3,
556
557 _PERIPH_MAX,
558 };
559
560 status_t zynq_set_clock(enum zynq_periph, bool enable, enum zynq_clock_source, uint32_t divisor, uint32_t divisor2);
561 uint32_t zynq_get_clock(enum zynq_periph);
562
563 /* boot mode */
564 #define ZYNQ_BOOT_MODE_JTAG (0)
565 #define ZYNQ_BOOT_MODE_QSPI (1)
566 #define ZYNQ_BOOT_MODE_NOR (2)
567 #define ZYNQ_BOOT_MODE_NAND (4)
568 #define ZYNQ_BOOT_MODE_SD (5)
569 #define ZYNQ_BOOT_MODE_MASK (0x7) /* only interested in BOOT_MODE[2:0] */
570
zynq_get_boot_mode(void)571 static inline uint32_t zynq_get_boot_mode(void) { return SLCR->BOOT_MODE & ZYNQ_BOOT_MODE_MASK; }
572
573 #endif // !ASSEMBLY
574
575