1 //***************************************************************************** 2 // 3 // hw_ssi.h - Macros used when accessing the SSI hardware. 4 // 5 // Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 9453 of the Stellaris Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_SSI_H__ 41 #define __HW_SSI_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the SSI register offsets. 46 // 47 //***************************************************************************** 48 #define SSI_O_CR0 0x00000000 // SSI Control 0 49 #define SSI_O_CR1 0x00000004 // SSI Control 1 50 #define SSI_O_DR 0x00000008 // SSI Data 51 #define SSI_O_SR 0x0000000C // SSI Status 52 #define SSI_O_CPSR 0x00000010 // SSI Clock Prescale 53 #define SSI_O_IM 0x00000014 // SSI Interrupt Mask 54 #define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status 55 #define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status 56 #define SSI_O_ICR 0x00000020 // SSI Interrupt Clear 57 #define SSI_O_DMACTL 0x00000024 // SSI DMA Control 58 #define SSI_O_CC 0x00000FC8 // SSI Clock Configuration 59 60 //***************************************************************************** 61 // 62 // The following are defines for the bit fields in the SSI_O_CR0 register. 63 // 64 //***************************************************************************** 65 #define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate 66 #define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase 67 #define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity 68 #define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select 69 #define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format 70 #define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous 71 // Serial Frame Format 72 #define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format 73 #define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select 74 #define SSI_CR0_DSS_4 0x00000003 // 4-bit data 75 #define SSI_CR0_DSS_5 0x00000004 // 5-bit data 76 #define SSI_CR0_DSS_6 0x00000005 // 6-bit data 77 #define SSI_CR0_DSS_7 0x00000006 // 7-bit data 78 #define SSI_CR0_DSS_8 0x00000007 // 8-bit data 79 #define SSI_CR0_DSS_9 0x00000008 // 9-bit data 80 #define SSI_CR0_DSS_10 0x00000009 // 10-bit data 81 #define SSI_CR0_DSS_11 0x0000000A // 11-bit data 82 #define SSI_CR0_DSS_12 0x0000000B // 12-bit data 83 #define SSI_CR0_DSS_13 0x0000000C // 13-bit data 84 #define SSI_CR0_DSS_14 0x0000000D // 14-bit data 85 #define SSI_CR0_DSS_15 0x0000000E // 15-bit data 86 #define SSI_CR0_DSS_16 0x0000000F // 16-bit data 87 #define SSI_CR0_SCR_S 8 88 89 //***************************************************************************** 90 // 91 // The following are defines for the bit fields in the SSI_O_CR1 register. 92 // 93 //***************************************************************************** 94 #define SSI_CR1_EOT 0x00000010 // End of Transmission 95 #define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable 96 #define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select 97 #define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port 98 // Enable 99 #define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode 100 101 //***************************************************************************** 102 // 103 // The following are defines for the bit fields in the SSI_O_DR register. 104 // 105 //***************************************************************************** 106 #define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data 107 #define SSI_DR_DATA_S 0 108 109 //***************************************************************************** 110 // 111 // The following are defines for the bit fields in the SSI_O_SR register. 112 // 113 //***************************************************************************** 114 #define SSI_SR_BSY 0x00000010 // SSI Busy Bit 115 #define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full 116 #define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty 117 #define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full 118 #define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty 119 120 //***************************************************************************** 121 // 122 // The following are defines for the bit fields in the SSI_O_CPSR register. 123 // 124 //***************************************************************************** 125 #define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor 126 #define SSI_CPSR_CPSDVSR_S 0 127 128 //***************************************************************************** 129 // 130 // The following are defines for the bit fields in the SSI_O_IM register. 131 // 132 //***************************************************************************** 133 #define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask 134 #define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask 135 #define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt 136 // Mask 137 #define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt 138 // Mask 139 140 //***************************************************************************** 141 // 142 // The following are defines for the bit fields in the SSI_O_RIS register. 143 // 144 //***************************************************************************** 145 #define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt 146 // Status 147 #define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt 148 // Status 149 #define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw 150 // Interrupt Status 151 #define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw 152 // Interrupt Status 153 154 //***************************************************************************** 155 // 156 // The following are defines for the bit fields in the SSI_O_MIS register. 157 // 158 //***************************************************************************** 159 #define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked 160 // Interrupt Status 161 #define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked 162 // Interrupt Status 163 #define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked 164 // Interrupt Status 165 #define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked 166 // Interrupt Status 167 168 //***************************************************************************** 169 // 170 // The following are defines for the bit fields in the SSI_O_ICR register. 171 // 172 //***************************************************************************** 173 #define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt 174 // Clear 175 #define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt 176 // Clear 177 178 //***************************************************************************** 179 // 180 // The following are defines for the bit fields in the SSI_O_DMACTL register. 181 // 182 //***************************************************************************** 183 #define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable 184 #define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable 185 186 //***************************************************************************** 187 // 188 // The following are defines for the bit fields in the SSI_O_CC register. 189 // 190 //***************************************************************************** 191 #define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source 192 #define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the 193 // PLL bypass is in effect) or the 194 // PLL output (default) 195 #define SSI_CC_CS_PIOSC 0x00000005 // PIOSC 196 197 //***************************************************************************** 198 // 199 // The following definitions are deprecated. 200 // 201 //***************************************************************************** 202 #ifndef DEPRECATED 203 204 //***************************************************************************** 205 // 206 // The following are deprecated defines for the bit fields in the SSI_O_CR0 207 // register. 208 // 209 //***************************************************************************** 210 #define SSI_CR0_SCR 0x0000FF00 // Serial clock rate 211 #define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask 212 #define SSI_CR0_DSS 0x0000000F // Data size select 213 214 //***************************************************************************** 215 // 216 // The following are deprecated defines for the bit fields in the SSI_O_CPSR 217 // register. 218 // 219 //***************************************************************************** 220 #define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale 221 222 //***************************************************************************** 223 // 224 // The following are deprecated defines for the SSI controller's FIFO size. 225 // 226 //***************************************************************************** 227 #define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO 228 #define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO 229 230 //***************************************************************************** 231 // 232 // The following are deprecated defines for the bit fields in the interrupt 233 // mask set and clear, raw interrupt, masked interrupt, and interrupt clear 234 // registers. 235 // 236 //***************************************************************************** 237 #define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt 238 #define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt 239 #define SSI_INT_RXTO 0x00000002 // RX timeout interrupt 240 #define SSI_INT_RXOR 0x00000001 // RX overrun interrupt 241 242 #endif 243 244 #endif // __HW_SSI_H__ 245