Searched refs:SSI_DR0_OFFSET (Results 1 – 5 of 5) sorted by relevance
| /lk-master/external/platform/pico/rp2_common/boot_stage2/ |
| A D | boot2_w25q080.S | 166 str r1, [r3, #SSI_DR0_OFFSET]
170 ldr r1, [r3, #SSI_DR0_OFFSET]
174 str r1, [r3, #SSI_DR0_OFFSET]
176 str r0, [r3, #SSI_DR0_OFFSET]
177 str r2, [r3, #SSI_DR0_OFFSET]
180 ldr r1, [r3, #SSI_DR0_OFFSET]
181 ldr r1, [r3, #SSI_DR0_OFFSET]
182 ldr r1, [r3, #SSI_DR0_OFFSET]
235 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
237 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
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| A D | boot2_is25lp080.S | 128 str r1, [r3, #SSI_DR0_OFFSET]
132 ldr r1, [r3, #SSI_DR0_OFFSET]
136 str r1, [r3, #SSI_DR0_OFFSET]
138 str r2, [r3, #SSI_DR0_OFFSET]
141 ldr r1, [r3, #SSI_DR0_OFFSET]
142 ldr r1, [r3, #SSI_DR0_OFFSET]
204 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
206 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
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| A D | boot2_w25x10cl.S | 138 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
140 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
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| /lk-master/external/platform/pico/rp2_common/boot_stage2/asminclude/boot2_helpers/ |
| A D | read_flash_sreg.S | 19 str r0, [r3, #SSI_DR0_OFFSET]
21 str r0, [r3, #SSI_DR0_OFFSET]
25 ldr r0, [r3, #SSI_DR0_OFFSET]
26 ldr r0, [r3, #SSI_DR0_OFFSET]
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| /lk-master/external/platform/pico/rp2040/hardware_regs/include/hardware/regs/ |
| A D | ssi.h | 681 #define SSI_DR0_OFFSET 0x00000060 macro
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