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Searched refs:SSI_SPI_CTRLR0_ADDR_L_LSB (Results 1 – 5 of 5) sorted by relevance

/lk-master/external/platform/pico/rp2_common/boot_stage2/
A Dboot2_w25x10cl.S123 (7 << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Send 28 bits (24 address + 4 mode) */ \
172 (7 << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Send 28 bits (24 address + 4 mode) */ \
A Dboot2_is25lp080.S189 (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \
232 (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \
A Dboot2_w25q080.S220 (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \
257 (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \
A Dboot2_generic_03h.S48 (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \
/lk-master/external/platform/pico/rp2040/hardware_regs/include/hardware/regs/
A Dssi.h776 #define SSI_SPI_CTRLR0_ADDR_L_LSB 2 macro

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