1 /* 2 * Copyright (c) 2016 Erik Gilling 3 * 4 * Use of this source code is governed by a MIT-style 5 * license that can be found in the LICENSE file or at 6 * https://opensource.org/licenses/MIT 7 */ 8 #pragma once 9 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <sys/types.h> 13 14 #include <stm32f0xx.h> 15 16 enum { 17 STM32_RCC_REG_AHB = 0, 18 STM32_RCC_REG_APB1 = 1, 19 STM32_RCC_REG_APB2 = 2, 20 }; 21 22 #define STM32_RCC_CLK(reg, index) (((reg) << 16) | (index)) 23 #define STM32_RCC_CLK_AHB(index) STM32_RCC_CLK(STM32_RCC_REG_AHB, index) 24 #define STM32_RCC_CLK_APB1(index) STM32_RCC_CLK(STM32_RCC_REG_APB1, index) 25 #define STM32_RCC_CLK_APB2(index) STM32_RCC_CLK(STM32_RCC_REG_APB2, index) 26 27 #define STM32_RCC_CLK_REG(clk) ((clk) >> 16) 28 #define STM32_RCC_CLK_INDEX(clk) ((clk) & 0xffff) 29 30 typedef enum { 31 // AHB clocks. 32 STM32_RCC_CLK_DMA = STM32_RCC_CLK_AHB(0), 33 STM32_RCC_CLK_DMA2 = STM32_RCC_CLK_AHB(1), 34 STM32_RCC_CLK_SRAM = STM32_RCC_CLK_AHB(2), 35 STM32_RCC_CLK_FLITF = STM32_RCC_CLK_AHB(4), 36 STM32_RCC_CLK_CRC = STM32_RCC_CLK_AHB(6), 37 STM32_RCC_CLK_IOPA = STM32_RCC_CLK_AHB(17), 38 STM32_RCC_CLK_IOPB = STM32_RCC_CLK_AHB(18), 39 STM32_RCC_CLK_IOPC = STM32_RCC_CLK_AHB(19), 40 STM32_RCC_CLK_IOPD = STM32_RCC_CLK_AHB(20), 41 STM32_RCC_CLK_IOPE = STM32_RCC_CLK_AHB(21), 42 STM32_RCC_CLK_IOPF = STM32_RCC_CLK_AHB(22), 43 STM32_RCC_CLK_TSC = STM32_RCC_CLK_AHB(24), 44 45 // APB1 clocks. 46 STM32_RCC_CLK_TIM2 = STM32_RCC_CLK_APB1(0), 47 STM32_RCC_CLK_TIM3 = STM32_RCC_CLK_APB1(1), 48 STM32_RCC_CLK_TIM6 = STM32_RCC_CLK_APB1(4), 49 STM32_RCC_CLK_TIM7 = STM32_RCC_CLK_APB1(5), 50 STM32_RCC_CLK_TIM14 = STM32_RCC_CLK_APB1(8), 51 STM32_RCC_CLK_WWDG = STM32_RCC_CLK_APB1(11), 52 STM32_RCC_CLK_SPI2 = STM32_RCC_CLK_APB1(14), 53 STM32_RCC_CLK_USART2 = STM32_RCC_CLK_APB1(17), 54 STM32_RCC_CLK_USART3 = STM32_RCC_CLK_APB1(18), 55 STM32_RCC_CLK_USART4 = STM32_RCC_CLK_APB1(19), 56 STM32_RCC_CLK_USART5 = STM32_RCC_CLK_APB1(20), 57 STM32_RCC_CLK_I2C1 = STM32_RCC_CLK_APB1(21), 58 STM32_RCC_CLK_I2C2 = STM32_RCC_CLK_APB1(22), 59 STM32_RCC_CLK_USB = STM32_RCC_CLK_APB1(23), 60 STM32_RCC_CLK_CAN = STM32_RCC_CLK_APB1(25), 61 STM32_RCC_CLK_CRS = STM32_RCC_CLK_APB1(27), 62 STM32_RCC_CLK_PWR = STM32_RCC_CLK_APB1(28), 63 STM32_RCC_CLK_DAC = STM32_RCC_CLK_APB1(29), 64 STM32_RCC_CLK_CEC = STM32_RCC_CLK_APB1(30), 65 66 // APB2 clocks. 67 STM32_RCC_CLK_SYSCFGCOMP = STM32_RCC_CLK_APB2(0), 68 STM32_RCC_CLK_USART6 = STM32_RCC_CLK_APB2(5), 69 STM32_RCC_CLK_USART7 = STM32_RCC_CLK_APB2(6), 70 STM32_RCC_CLK_USART8 = STM32_RCC_CLK_APB2(7), 71 STM32_RCC_CLK_ADC = STM32_RCC_CLK_APB2(9), 72 STM32_RCC_CLK_TIM1 = STM32_RCC_CLK_APB2(11), 73 STM32_RCC_CLK_SPI1 = STM32_RCC_CLK_APB2(12), 74 STM32_RCC_CLK_USART1 = STM32_RCC_CLK_APB2(14), 75 STM32_RCC_CLK_TIM15 = STM32_RCC_CLK_APB2(16), 76 STM32_RCC_CLK_TIM16 = STM32_RCC_CLK_APB2(17), 77 STM32_RCC_CLK_TIM17 = STM32_RCC_CLK_APB2(18), 78 STM32_RCC_CLK_DBG_MUC = STM32_RCC_CLK_APB2(22), 79 } stm32_rcc_clk_t; 80 81 void stm32_rcc_set_enable(stm32_rcc_clk_t clock, bool enable); 82 void stm32_rcc_set_reset(stm32_rcc_clk_t clock, bool reset); 83