1 //***************************************************************************** 2 // 3 // hw_sysctl.h - Macros used when accessing the system control hardware. 4 // 5 // Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 9453 of the Stellaris Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_SYSCTL_H__ 41 #define __HW_SYSCTL_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the System Control register addresses. 46 // 47 //***************************************************************************** 48 #define SYSCTL_DID0 0x400FE000 // Device Identification 0 49 #define SYSCTL_DID1 0x400FE004 // Device Identification 1 50 #define SYSCTL_DC0 0x400FE008 // Device Capabilities 0 51 #define SYSCTL_DC1 0x400FE010 // Device Capabilities 1 52 #define SYSCTL_DC2 0x400FE014 // Device Capabilities 2 53 #define SYSCTL_DC3 0x400FE018 // Device Capabilities 3 54 #define SYSCTL_DC4 0x400FE01C // Device Capabilities 4 55 #define SYSCTL_DC5 0x400FE020 // Device Capabilities 5 56 #define SYSCTL_DC6 0x400FE024 // Device Capabilities 6 57 #define SYSCTL_DC7 0x400FE028 // Device Capabilities 7 58 #define SYSCTL_DC8 0x400FE02C // Device Capabilities 8 ADC 59 // Channels 60 #define SYSCTL_PBORCTL 0x400FE030 // Brown-Out Reset Control 61 #define SYSCTL_LDOPCTL 0x400FE034 // LDO Power Control 62 #define SYSCTL_SRCR0 0x400FE040 // Software Reset Control 0 63 #define SYSCTL_SRCR1 0x400FE044 // Software Reset Control 1 64 #define SYSCTL_SRCR2 0x400FE048 // Software Reset Control 2 65 #define SYSCTL_RIS 0x400FE050 // Raw Interrupt Status 66 #define SYSCTL_IMC 0x400FE054 // Interrupt Mask Control 67 #define SYSCTL_MISC 0x400FE058 // Masked Interrupt Status and 68 // Clear 69 #define SYSCTL_RESC 0x400FE05C // Reset Cause 70 #define SYSCTL_RCC 0x400FE060 // Run-Mode Clock Configuration 71 #define SYSCTL_PLLCFG 0x400FE064 // XTAL to PLL Translation 72 #define SYSCTL_GPIOHBCTL 0x400FE06C // GPIO High-Performance Bus 73 // Control 74 #define SYSCTL_RCC2 0x400FE070 // Run-Mode Clock Configuration 2 75 #define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control 76 #define SYSCTL_RCGC0 0x400FE100 // Run Mode Clock Gating Control 77 // Register 0 78 #define SYSCTL_RCGC1 0x400FE104 // Run Mode Clock Gating Control 79 // Register 1 80 #define SYSCTL_RCGC2 0x400FE108 // Run Mode Clock Gating Control 81 // Register 2 82 #define SYSCTL_SCGC0 0x400FE110 // Sleep Mode Clock Gating Control 83 // Register 0 84 #define SYSCTL_SCGC1 0x400FE114 // Sleep Mode Clock Gating Control 85 // Register 1 86 #define SYSCTL_SCGC2 0x400FE118 // Sleep Mode Clock Gating Control 87 // Register 2 88 #define SYSCTL_DCGC0 0x400FE120 // Deep Sleep Mode Clock Gating 89 // Control Register 0 90 #define SYSCTL_DCGC1 0x400FE124 // Deep-Sleep Mode Clock Gating 91 // Control Register 1 92 #define SYSCTL_DCGC2 0x400FE128 // Deep Sleep Mode Clock Gating 93 // Control Register 2 94 #define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep Clock Configuration 95 #define SYSCTL_SYSPROP 0x400FE14C // System Properties 96 #define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator 97 // Calibration 98 #define SYSCTL_CLKVCLR 0x400FE150 // Clock Verification Clear 99 #define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator 100 // Statistics 101 #define SYSCTL_LDOARST 0x400FE160 // Allow Unregulated LDO to Reset 102 // the Part 103 #define SYSCTL_PLLFREQ0 0x400FE160 // PLL Frequency 0 104 #define SYSCTL_PLLFREQ1 0x400FE164 // PLL Frequency 1 105 #define SYSCTL_PLLSTAT 0x400FE168 // PLL Status 106 #define SYSCTL_I2SMCLKCFG 0x400FE170 // I2S MCLK Configuration 107 #define SYSCTL_DC9 0x400FE190 // Device Capabilities 9 ADC 108 // Digital Comparators 109 #define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volatile Memory Information 110 #define SYSCTL_PPWD 0x400FE300 // Watchdog Timer Peripheral 111 // Present 112 #define SYSCTL_PPTIMER 0x400FE304 // Timer Peripheral Present 113 #define SYSCTL_PPGPIO 0x400FE308 // General-Purpose Input/Output 114 // Peripheral Present 115 #define SYSCTL_PPDMA 0x400FE30C // Micro Direct Memory Access 116 // Peripheral Present 117 #define SYSCTL_PPHIB 0x400FE314 // Hibernation Peripheral Present 118 #define SYSCTL_PPUART 0x400FE318 // Universal Asynchronous 119 // Receiver/Transmitter Peripheral 120 // Present 121 #define SYSCTL_PPSSI 0x400FE31C // Synchronous Serial Interface 122 // Peripheral Present 123 #define SYSCTL_PPI2C 0x400FE320 // Inter-Integrated Circuit 124 // Peripheral Present 125 #define SYSCTL_PPUSB 0x400FE328 // Universal Serial Bus Peripheral 126 // Present 127 #define SYSCTL_PPCAN 0x400FE334 // Controller Area Network 128 // Peripheral Present 129 #define SYSCTL_PPADC 0x400FE338 // Analog-to-Digital Converter 130 // Peripheral Present 131 #define SYSCTL_PPACMP 0x400FE33C // Analog Comparator Peripheral 132 // Present 133 #define SYSCTL_PPPWM 0x400FE340 // Pulse Width Modulator Peripheral 134 // Present 135 #define SYSCTL_PPQEI 0x400FE344 // Quadrature Encoder Interface 136 // Peripheral Present 137 #define SYSCTL_PPLPC 0x400FE348 // Low Pin Count Interface 138 // Peripheral Present 139 #define SYSCTL_PPPECI 0x400FE350 // Platform Environment Control 140 // Interface Peripheral Present 141 #define SYSCTL_PPFAN 0x400FE354 // Fan Control Peripheral Present 142 #define SYSCTL_PPEEPROM 0x400FE358 // EEPROM Peripheral Present 143 #define SYSCTL_PPWTIMER 0x400FE35C // Wide Timer Peripheral Present 144 #define SYSCTL_SRWD 0x400FE500 // Watchdog Timer Software Reset 145 #define SYSCTL_SRTIMER 0x400FE504 // Timer Software Reset 146 #define SYSCTL_SRGPIO 0x400FE508 // General-Purpose Input/Output 147 // Software Reset 148 #define SYSCTL_SRDMA 0x400FE50C // Micro Direct Memory Access 149 // Software Reset 150 #define SYSCTL_SRHIB 0x400FE514 // Hibernation Software Reset 151 #define SYSCTL_SRUART 0x400FE518 // Universal Asynchronous 152 // Receiver/Transmitter Software 153 // Reset 154 #define SYSCTL_SRSSI 0x400FE51C // Synchronous Serial Interface 155 // Software Reset 156 #define SYSCTL_SRI2C 0x400FE520 // Inter-Integrated Circuit 157 // Software Reset 158 #define SYSCTL_SRUSB 0x400FE528 // Universal Serial Bus Software 159 // Reset 160 #define SYSCTL_SRCAN 0x400FE534 // Controller Area Network Software 161 // Reset 162 #define SYSCTL_SRADC 0x400FE538 // Analog-to-Digital Converter 163 // Software Reset 164 #define SYSCTL_SRACMP 0x400FE53C // Analog Comparator Software Reset 165 #define SYSCTL_SRPWM 0x400FE540 // Pulse Width Modulator Software 166 // Reset 167 #define SYSCTL_SRQEI 0x400FE544 // Quadrature Encoder Interface 168 // Software Reset 169 #define SYSCTL_SRLPC 0x400FE548 // Low Pin Count Interface Software 170 // Reset 171 #define SYSCTL_SRPECI 0x400FE550 // Platform Environment Control 172 // Interface Software Reset 173 #define SYSCTL_SRFAN 0x400FE554 // Fan Software Reset 174 #define SYSCTL_SREEPROM 0x400FE558 // EEPROM Software Reset 175 #define SYSCTL_SRWTIMER 0x400FE55C // Wide Timer Software Reset 176 #define SYSCTL_RCGCWD 0x400FE600 // Watchdog Timer Run Mode Clock 177 // Gating Control 178 #define SYSCTL_RCGCTIMER 0x400FE604 // Timer Run Mode Clock Gating 179 // Control 180 #define SYSCTL_RCGCGPIO 0x400FE608 // General-Purpose Input/Output Run 181 // Mode Clock Gating Control 182 #define SYSCTL_RCGCDMA 0x400FE60C // Micro Direct Memory Access Run 183 // Mode Clock Gating Control 184 #define SYSCTL_RCGCHIB 0x400FE614 // Hibernation Run Mode Clock 185 // Gating Control 186 #define SYSCTL_RCGCUART 0x400FE618 // Universal Asynchronous 187 // Receiver/Transmitter Run Mode 188 // Clock Gating Control 189 #define SYSCTL_RCGCSSI 0x400FE61C // Synchronous Serial Interface Run 190 // Mode Clock Gating Control 191 #define SYSCTL_RCGCI2C 0x400FE620 // Inter-Integrated Circuit Run 192 // Mode Clock Gating Control 193 #define SYSCTL_RCGCUSB 0x400FE628 // Universal Serial Bus Run Mode 194 // Clock Gating Control 195 #define SYSCTL_RCGCCAN 0x400FE634 // Controller Area Network Run Mode 196 // Clock Gating Control 197 #define SYSCTL_RCGCADC 0x400FE638 // Analog-to-Digital Converter Run 198 // Mode Clock Gating Control 199 #define SYSCTL_RCGCACMP 0x400FE63C // Analog Comparator Run Mode Clock 200 // Gating Control 201 #define SYSCTL_RCGCPWM 0x400FE640 // Pulse Width Modulator Run Mode 202 // Clock Gating Control 203 #define SYSCTL_RCGCQEI 0x400FE644 // Quadrature Encoder Interface Run 204 // Mode Clock Gating Control 205 #define SYSCTL_RCGCLPC 0x400FE648 // Low Pin Count Interface Run Mode 206 // Clock Gating Control 207 #define SYSCTL_RCGCPECI 0x400FE650 // Platform Environment Control 208 // Interface Run Mode Clock Gating 209 // Control 210 #define SYSCTL_RCGCFAN 0x400FE654 // Fan Run Mode Clock Gating 211 // Control 212 #define SYSCTL_RCGCEEPROM 0x400FE658 // EEPROM Run Mode Clock Gating 213 // Control 214 #define SYSCTL_RCGCWTIMER 0x400FE65C // Wide Timer Run Mode Clock Gating 215 // Control 216 #define SYSCTL_SCGCWD 0x400FE700 // Watchdog Timer Sleep Mode Clock 217 // Gating Control 218 #define SYSCTL_SCGCTIMER 0x400FE704 // Timer Sleep Mode Clock Gating 219 // Control 220 #define SYSCTL_SCGCGPIO 0x400FE708 // General-Purpose Input/Output 221 // Sleep Mode Clock Gating Control 222 #define SYSCTL_SCGCDMA 0x400FE70C // Micro Direct Memory Access Sleep 223 // Mode Clock Gating Control 224 #define SYSCTL_SCGCHIB 0x400FE714 // Hibernation Sleep Mode Clock 225 // Gating Control 226 #define SYSCTL_SCGCUART 0x400FE718 // Universal Asynchronous 227 // Receiver/Transmitter Sleep Mode 228 // Clock Gating Control 229 #define SYSCTL_SCGCSSI 0x400FE71C // Synchronous Serial Interface 230 // Sleep Mode Clock Gating Control 231 #define SYSCTL_SCGCI2C 0x400FE720 // Inter-Integrated Circuit Sleep 232 // Mode Clock Gating Control 233 #define SYSCTL_SCGCUSB 0x400FE728 // Universal Serial Bus Sleep Mode 234 // Clock Gating Control 235 #define SYSCTL_SCGCCAN 0x400FE734 // Controller Area Network Sleep 236 // Mode Clock Gating Control 237 #define SYSCTL_SCGCADC 0x400FE738 // Analog-to-Digital Converter 238 // Sleep Mode Clock Gating Control 239 #define SYSCTL_SCGCACMP 0x400FE73C // Analog Comparator Sleep Mode 240 // Clock Gating Control 241 #define SYSCTL_SCGCPWM 0x400FE740 // Pulse Width Modulator Sleep Mode 242 // Clock Gating Control 243 #define SYSCTL_SCGCQEI 0x400FE744 // Quadrature Encoder Interface 244 // Sleep Mode Clock Gating Control 245 #define SYSCTL_SCGCLPC 0x400FE748 // Low Pin Count Interface Sleep 246 // Mode Clock Gating Control 247 #define SYSCTL_SCGCPECI 0x400FE750 // Platform Environment Control 248 // Interface Sleep Mode Clock 249 // Gating Control 250 #define SYSCTL_SCGCFAN 0x400FE754 // Fan Sleep Mode Clock Gating 251 // Control 252 #define SYSCTL_SCGCEEPROM 0x400FE758 // EEPROM Sleep Mode Clock Gating 253 // Control 254 #define SYSCTL_SCGCWTIMER 0x400FE75C // Wide Timer Sleep Mode Clock 255 // Gating Control 256 #define SYSCTL_DCGCWD 0x400FE800 // Watchdog Timer Deep-Sleep Mode 257 // Clock Gating Control 258 #define SYSCTL_DCGCTIMER 0x400FE804 // Timer Deep-Sleep Mode Clock 259 // Gating Control 260 #define SYSCTL_DCGCGPIO 0x400FE808 // General-Purpose Input/Output 261 // Deep-Sleep Mode Clock Gating 262 // Control 263 #define SYSCTL_DCGCDMA 0x400FE80C // Micro Direct Memory Access 264 // Deep-Sleep Mode Clock Gating 265 // Control 266 #define SYSCTL_DCGCHIB 0x400FE814 // Hibernation Deep-Sleep Mode 267 // Clock Gating Control 268 #define SYSCTL_DCGCUART 0x400FE818 // Universal Asynchronous 269 // Receiver/Transmitter Deep-Sleep 270 // Mode Clock Gating Control 271 #define SYSCTL_DCGCSSI 0x400FE81C // Synchronous Serial Interface 272 // Deep-Sleep Mode Clock Gating 273 // Control 274 #define SYSCTL_DCGCI2C 0x400FE820 // Inter-Integrated Circuit 275 // Deep-Sleep Mode Clock Gating 276 // Control 277 #define SYSCTL_DCGCUSB 0x400FE828 // Universal Serial Bus Deep-Sleep 278 // Mode Clock Gating Control 279 #define SYSCTL_DCGCCAN 0x400FE834 // Controller Area Network 280 // Deep-Sleep Mode Clock Gating 281 // Control 282 #define SYSCTL_DCGCADC 0x400FE838 // Analog-to-Digital Converter 283 // Deep-Sleep Mode Clock Gating 284 // Control 285 #define SYSCTL_DCGCACMP 0x400FE83C // Analog Comparator Deep-Sleep 286 // Mode Clock Gating Control 287 #define SYSCTL_DCGCPWM 0x400FE840 // Pulse Width Modulator Deep-Sleep 288 // Mode Clock Gating Control 289 #define SYSCTL_DCGCQEI 0x400FE844 // Quadrature Encoder Interface 290 // Deep-Sleep Mode Clock Gating 291 // Control 292 #define SYSCTL_DCGCLPC 0x400FE848 // Low Pin Count Interface 293 // Deep-Sleep Mode Clock Gating 294 // Control 295 #define SYSCTL_DCGCPECI 0x400FE850 // Platform Environment Control 296 // Interface Deep-Sleep Mode Clock 297 // Gating Control 298 #define SYSCTL_DCGCFAN 0x400FE854 // Fan Deep-Sleep Mode Clock Gating 299 // Control 300 #define SYSCTL_DCGCEEPROM 0x400FE858 // EEPROM Deep-Sleep Mode Clock 301 // Gating Control 302 #define SYSCTL_DCGCWTIMER 0x400FE85C // Wide Timer Deep-Sleep Mode Clock 303 // Gating Control 304 #define SYSCTL_PCWD 0x400FE900 // Watchdog Timer Power Control 305 #define SYSCTL_PCTIMER 0x400FE904 // Timer Power Control 306 #define SYSCTL_PCGPIO 0x400FE908 // General-Purpose Input/Output 307 // Power Control 308 #define SYSCTL_PCDMA 0x400FE90C // Micro Direct Memory Access Power 309 // Control 310 #define SYSCTL_PCHIB 0x400FE914 // Hibernation Power Control 311 #define SYSCTL_PCUART 0x400FE918 // Universal Asynchronous 312 // Receiver/Transmitter Power 313 // Control 314 #define SYSCTL_PCSSI 0x400FE91C // Synchronous Serial Interface 315 // Power Control 316 #define SYSCTL_PCI2C 0x400FE920 // Inter-Integrated Circuit Power 317 // Control 318 #define SYSCTL_PCUSB 0x400FE928 // Universal Serial Bus Power 319 // Control 320 #define SYSCTL_PCCAN 0x400FE934 // Controller Area Network Power 321 // Control 322 #define SYSCTL_PCADC 0x400FE938 // Analog-to-Digital Converter 323 // Power Control 324 #define SYSCTL_PCACMP 0x400FE93C // Analog Comparator Power Control 325 #define SYSCTL_PCPWM 0x400FE940 // Pulse Width Modulator Power 326 // Control 327 #define SYSCTL_PCQEI 0x400FE944 // Quadrature Encoder Interface 328 // Power Control 329 #define SYSCTL_PCLPC 0x400FE948 // Low Pin Count Interface Power 330 // Control 331 #define SYSCTL_PCPECI 0x400FE950 // Platform Environment Control 332 // Interface Power Control 333 #define SYSCTL_PCFAN 0x400FE954 // Fan Power Control 334 #define SYSCTL_PCEEPROM 0x400FE958 // EEPROM Power Control 335 #define SYSCTL_PCWTIMER 0x400FE95C // Wide Timer Power Control 336 #define SYSCTL_PRWD 0x400FEA00 // Watchdog Timer Peripheral Ready 337 #define SYSCTL_PRTIMER 0x400FEA04 // Timer Peripheral Ready 338 #define SYSCTL_PRGPIO 0x400FEA08 // General-Purpose Input/Output 339 // Peripheral Ready 340 #define SYSCTL_PRDMA 0x400FEA0C // Micro Direct Memory Access 341 // Peripheral Ready 342 #define SYSCTL_PRHIB 0x400FEA14 // Hibernation Peripheral Ready 343 #define SYSCTL_PRUART 0x400FEA18 // Universal Asynchronous 344 // Receiver/Transmitter Peripheral 345 // Ready 346 #define SYSCTL_PRSSI 0x400FEA1C // Synchronous Serial Interface 347 // Peripheral Ready 348 #define SYSCTL_PRI2C 0x400FEA20 // Inter-Integrated Circuit 349 // Peripheral Ready 350 #define SYSCTL_PRUSB 0x400FEA28 // Universal Serial Bus Peripheral 351 // Ready 352 #define SYSCTL_PRCAN 0x400FEA34 // Controller Area Network 353 // Peripheral Ready 354 #define SYSCTL_PRADC 0x400FEA38 // Analog-to-Digital Converter 355 // Peripheral Ready 356 #define SYSCTL_PRACMP 0x400FEA3C // Analog Comparator Peripheral 357 // Ready 358 #define SYSCTL_PRPWM 0x400FEA40 // Pulse Width Modulator Peripheral 359 // Ready 360 #define SYSCTL_PRQEI 0x400FEA44 // Quadrature Encoder Interface 361 // Peripheral Ready 362 #define SYSCTL_PRLPC 0x400FEA48 // Low Pin Count Interface 363 // Peripheral Ready 364 #define SYSCTL_PRPECI 0x400FEA50 // Platform Environment Control 365 // Interface Peripheral Ready 366 #define SYSCTL_PRFAN 0x400FEA54 // Fan Peripheral Ready 367 #define SYSCTL_PREEPROM 0x400FEA58 // EEPROM Peripheral Ready 368 #define SYSCTL_PRWTIMER 0x400FEA5C // Wide Timer Peripheral Ready 369 370 //***************************************************************************** 371 // 372 // The following are defines for the bit fields in the SYSCTL_DID0 register. 373 // 374 //***************************************************************************** 375 #define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version 376 #define SYSCTL_DID0_VER_0 0x00000000 // Initial DID0 register format 377 // definition for Stellaris(R) 378 // Sandstorm-class devices 379 #define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0 380 // register format 381 #define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class 382 #define SYSCTL_DID0_CLASS_SANDSTORM \ 383 0x00000000 // Sandstorm-class Device 384 #define SYSCTL_DID0_CLASS_FURY 0x00010000 // Stellaris(R) Fury-class devices 385 #define SYSCTL_DID0_CLASS_DUSTDEVIL \ 386 0x00030000 // Stellaris(R) DustDevil-class 387 // devices 388 #define SYSCTL_DID0_CLASS_TEMPEST \ 389 0x00040000 // Stellaris(R) Tempest-class 390 // microcontrollers 391 #define SYSCTL_DID0_CLASS_BLIZZARD \ 392 0x00050000 // Stellaris(R) Blizzard-class 393 // microcontrollers 394 #define SYSCTL_DID0_CLASS_FIRESTORM \ 395 0x00060000 // Stellaris(R) Firestorm-class 396 // microcontrollers 397 #define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision 398 #define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) 399 #define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer 400 // revision) 401 #define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer 402 // revision) 403 #define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision 404 #define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major 405 // revision update 406 #define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change 407 #define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change 408 #define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3 409 #define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4 410 #define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5 411 412 //***************************************************************************** 413 // 414 // The following are defines for the bit fields in the SYSCTL_DID1 register. 415 // 416 //***************************************************************************** 417 #define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version 418 #define SYSCTL_DID1_VER_0 0x00000000 // Initial DID1 register format 419 // definition, indicating a 420 // Stellaris LM3Snnn device 421 #define SYSCTL_DID1_VER_1 0x10000000 // Second version of the DID1 422 // register format 423 #define SYSCTL_DID1_FAM_M 0x0F000000 // Family 424 #define SYSCTL_DID1_FAM_STELLARIS \ 425 0x00000000 // Stellaris family of 426 // microcontollers, that is, all 427 // devices with external part 428 // numbers starting with LM3S 429 #define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number 430 #define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 431 #define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 432 #define SYSCTL_DID1_PRTNO_300 0x00190000 // LM3S300 433 #define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 434 #define SYSCTL_DID1_PRTNO_308 0x001A0000 // LM3S308 435 #define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 436 #define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 437 #define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 438 #define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317 439 #define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 440 #define SYSCTL_DID1_PRTNO_600 0x002A0000 // LM3S600 441 #define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 442 #define SYSCTL_DID1_PRTNO_608 0x002B0000 // LM3S608 443 #define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 444 #define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 445 #define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 446 #define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 447 #define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 448 #define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617 449 #define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618 450 #define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 451 #define SYSCTL_DID1_PRTNO_800 0x00380000 // LM3S800 452 #define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 453 #define SYSCTL_DID1_PRTNO_808 0x00390000 // LM3S808 454 #define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 455 #define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 456 #define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 457 #define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817 458 #define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818 459 #define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 460 #define SYSCTL_DID1_PRTNO_1110 0x00BF0000 // LM3S1110 461 #define SYSCTL_DID1_PRTNO_1133 0x00C30000 // LM3S1133 462 #define SYSCTL_DID1_PRTNO_1138 0x00C50000 // LM3S1138 463 #define SYSCTL_DID1_PRTNO_1150 0x00C10000 // LM3S1150 464 #define SYSCTL_DID1_PRTNO_1162 0x00C40000 // LM3S1162 465 #define SYSCTL_DID1_PRTNO_1165 0x00C20000 // LM3S1165 466 #define SYSCTL_DID1_PRTNO_1166 0x00EC0000 // LM3S1166 467 #define SYSCTL_DID1_PRTNO_1332 0x00C60000 // LM3S1332 468 #define SYSCTL_DID1_PRTNO_1435 0x00BC0000 // LM3S1435 469 #define SYSCTL_DID1_PRTNO_1439 0x00BA0000 // LM3S1439 470 #define SYSCTL_DID1_PRTNO_1512 0x00BB0000 // LM3S1512 471 #define SYSCTL_DID1_PRTNO_1538 0x00C70000 // LM3S1538 472 #define SYSCTL_DID1_PRTNO_1601 0x00DB0000 // LM3S1601 473 #define SYSCTL_DID1_PRTNO_1607 0x00060000 // LM3S1607 474 #define SYSCTL_DID1_PRTNO_1608 0x00DA0000 // LM3S1608 475 #define SYSCTL_DID1_PRTNO_1620 0x00C00000 // LM3S1620 476 #define SYSCTL_DID1_PRTNO_1621 0x00CD0000 // LM3S1621 477 #define SYSCTL_DID1_PRTNO_1625 0x00030000 // LM3S1625 478 #define SYSCTL_DID1_PRTNO_1626 0x00040000 // LM3S1626 479 #define SYSCTL_DID1_PRTNO_1627 0x00050000 // LM3S1627 480 #define SYSCTL_DID1_PRTNO_1635 0x00B30000 // LM3S1635 481 #define SYSCTL_DID1_PRTNO_1636 0x00EB0000 // LM3S1636 482 #define SYSCTL_DID1_PRTNO_1637 0x00BD0000 // LM3S1637 483 #define SYSCTL_DID1_PRTNO_1651 0x00B10000 // LM3S1651 484 #define SYSCTL_DID1_PRTNO_1751 0x00B90000 // LM3S1751 485 #define SYSCTL_DID1_PRTNO_1776 0x00100000 // LM3S1776 486 #define SYSCTL_DID1_PRTNO_1811 0x00160000 // LM3S1811 487 #define SYSCTL_DID1_PRTNO_1816 0x003D0000 // LM3S1816 488 #define SYSCTL_DID1_PRTNO_1850 0x00B40000 // LM3S1850 489 #define SYSCTL_DID1_PRTNO_1911 0x00DD0000 // LM3S1911 490 #define SYSCTL_DID1_PRTNO_1918 0x00DC0000 // LM3S1918 491 #define SYSCTL_DID1_PRTNO_1937 0x00B70000 // LM3S1937 492 #define SYSCTL_DID1_PRTNO_1958 0x00BE0000 // LM3S1958 493 #define SYSCTL_DID1_PRTNO_1960 0x00B50000 // LM3S1960 494 #define SYSCTL_DID1_PRTNO_1968 0x00B80000 // LM3S1968 495 #define SYSCTL_DID1_PRTNO_1969 0x00EA0000 // LM3S1969 496 #define SYSCTL_DID1_PRTNO_1B21 0x00CE0000 // LM3S1B21 497 #define SYSCTL_DID1_PRTNO_1C21 0x00CA0000 // LM3S1C21 498 #define SYSCTL_DID1_PRTNO_1C26 0x00CB0000 // LM3S1C26 499 #define SYSCTL_DID1_PRTNO_1C58 0x00980000 // LM3S1C58 500 #define SYSCTL_DID1_PRTNO_1D21 0x00B00000 // LM3S1D21 501 #define SYSCTL_DID1_PRTNO_1D26 0x00CC0000 // LM3S1D26 502 #define SYSCTL_DID1_PRTNO_1F11 0x001D0000 // LM3S1F11 503 #define SYSCTL_DID1_PRTNO_1F16 0x001B0000 // LM3S1F16 504 #define SYSCTL_DID1_PRTNO_1G21 0x00AF0000 // LM3S1G21 505 #define SYSCTL_DID1_PRTNO_1G58 0x00950000 // LM3S1G58 506 #define SYSCTL_DID1_PRTNO_1H11 0x001E0000 // LM3S1H11 507 #define SYSCTL_DID1_PRTNO_1H16 0x001C0000 // LM3S1H16 508 #define SYSCTL_DID1_PRTNO_1J11 0x000F0000 // LM3S1J11 509 #define SYSCTL_DID1_PRTNO_1J16 0x003C0000 // LM3S1J16 510 #define SYSCTL_DID1_PRTNO_1N11 0x000E0000 // LM3S1N11 511 #define SYSCTL_DID1_PRTNO_1N16 0x003B0000 // LM3S1N16 512 #define SYSCTL_DID1_PRTNO_1P51 0x00B20000 // LM3S1P51 513 #define SYSCTL_DID1_PRTNO_1R21 0x009E0000 // LM3S1R21 514 #define SYSCTL_DID1_PRTNO_1R26 0x00C90000 // LM3S1R26 515 #define SYSCTL_DID1_PRTNO_1W16 0x00300000 // LM3S1W16 516 #define SYSCTL_DID1_PRTNO_1Z16 0x002F0000 // LM3S1Z16 517 #define SYSCTL_DID1_PRTNO_2016 0x00D40000 // LM3S2016 518 #define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110 519 #define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139 520 #define SYSCTL_DID1_PRTNO_2276 0x00390000 // LM3S2276 521 #define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410 522 #define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412 523 #define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432 524 #define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533 525 #define SYSCTL_DID1_PRTNO_2601 0x00E10000 // LM3S2601 526 #define SYSCTL_DID1_PRTNO_2608 0x00E00000 // LM3S2608 527 #define SYSCTL_DID1_PRTNO_2616 0x00330000 // LM3S2616 528 #define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620 529 #define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637 530 #define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651 531 #define SYSCTL_DID1_PRTNO_2671 0x00800000 // LM3S2671 532 #define SYSCTL_DID1_PRTNO_2678 0x00500000 // LM3S2678 533 #define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730 534 #define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739 535 #define SYSCTL_DID1_PRTNO_2776 0x003A0000 // LM3S2776 536 #define SYSCTL_DID1_PRTNO_2793 0x006D0000 // LM3S2793 537 #define SYSCTL_DID1_PRTNO_2911 0x00E30000 // LM3S2911 538 #define SYSCTL_DID1_PRTNO_2918 0x00E20000 // LM3S2918 539 #define SYSCTL_DID1_PRTNO_2919 0x00ED0000 // LM3S2919 540 #define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939 541 #define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948 542 #define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950 543 #define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965 544 #define SYSCTL_DID1_PRTNO_2B93 0x006C0000 // LM3S2B93 545 #define SYSCTL_DID1_PRTNO_2D93 0x00940000 // LM3S2D93 546 #define SYSCTL_DID1_PRTNO_2U93 0x00930000 // LM3S2U93 547 #define SYSCTL_DID1_PRTNO_3634 0x00080000 // LM3S3634 548 #define SYSCTL_DID1_PRTNO_3651 0x00430000 // LM3S3651 549 #define SYSCTL_DID1_PRTNO_3654 0x00C80000 // LM3S3654 550 #define SYSCTL_DID1_PRTNO_3739 0x00440000 // LM3S3739 551 #define SYSCTL_DID1_PRTNO_3748 0x00490000 // LM3S3748 552 #define SYSCTL_DID1_PRTNO_3749 0x00450000 // LM3S3749 553 #define SYSCTL_DID1_PRTNO_3826 0x00420000 // LM3S3826 554 #define SYSCTL_DID1_PRTNO_3J26 0x00410000 // LM3S3J26 555 #define SYSCTL_DID1_PRTNO_3N26 0x00400000 // LM3S3N26 556 #define SYSCTL_DID1_PRTNO_3W26 0x003F0000 // LM3S3W26 557 #define SYSCTL_DID1_PRTNO_3Z26 0x003E0000 // LM3S3Z26 558 #define SYSCTL_DID1_PRTNO_5632 0x00810000 // LM3S5632 559 #define SYSCTL_DID1_PRTNO_5651 0x000C0000 // LM3S5651 560 #define SYSCTL_DID1_PRTNO_5652 0x008A0000 // LM3S5652 561 #define SYSCTL_DID1_PRTNO_5656 0x004D0000 // LM3S5656 562 #define SYSCTL_DID1_PRTNO_5662 0x00910000 // LM3S5662 563 #define SYSCTL_DID1_PRTNO_5732 0x00960000 // LM3S5732 564 #define SYSCTL_DID1_PRTNO_5737 0x00970000 // LM3S5737 565 #define SYSCTL_DID1_PRTNO_5739 0x00A00000 // LM3S5739 566 #define SYSCTL_DID1_PRTNO_5747 0x00990000 // LM3S5747 567 #define SYSCTL_DID1_PRTNO_5749 0x00A70000 // LM3S5749 568 #define SYSCTL_DID1_PRTNO_5752 0x009A0000 // LM3S5752 569 #define SYSCTL_DID1_PRTNO_5762 0x009C0000 // LM3S5762 570 #define SYSCTL_DID1_PRTNO_5791 0x00690000 // LM3S5791 571 #define SYSCTL_DID1_PRTNO_5951 0x000B0000 // LM3S5951 572 #define SYSCTL_DID1_PRTNO_5956 0x004E0000 // LM3S5956 573 #define SYSCTL_DID1_PRTNO_5B91 0x00680000 // LM3S5B91 574 #define SYSCTL_DID1_PRTNO_5C31 0x002E0000 // LM3S5C31 575 #define SYSCTL_DID1_PRTNO_5C36 0x002C0000 // LM3S5C36 576 #define SYSCTL_DID1_PRTNO_5C51 0x005E0000 // LM3S5C51 577 #define SYSCTL_DID1_PRTNO_5C56 0x005B0000 // LM3S5C56 578 #define SYSCTL_DID1_PRTNO_5D51 0x005F0000 // LM3S5D51 579 #define SYSCTL_DID1_PRTNO_5D56 0x005C0000 // LM3S5D56 580 #define SYSCTL_DID1_PRTNO_5D91 0x00870000 // LM3S5D91 581 #define SYSCTL_DID1_PRTNO_5G31 0x002D0000 // LM3S5G31 582 #define SYSCTL_DID1_PRTNO_5G36 0x001F0000 // LM3S5G36 583 #define SYSCTL_DID1_PRTNO_5G51 0x005D0000 // LM3S5G51 584 #define SYSCTL_DID1_PRTNO_5G56 0x004F0000 // LM3S5G56 585 #define SYSCTL_DID1_PRTNO_5K31 0x00090000 // LM3S5K31 586 #define SYSCTL_DID1_PRTNO_5K36 0x004A0000 // LM3S5K36 587 #define SYSCTL_DID1_PRTNO_5P31 0x000A0000 // LM3S5P31 588 #define SYSCTL_DID1_PRTNO_5P36 0x00480000 // LM3S5P36 589 #define SYSCTL_DID1_PRTNO_5P3B 0x00B60000 // LM3S5P3B 590 #define SYSCTL_DID1_PRTNO_5P51 0x000D0000 // LM3S5P51 591 #define SYSCTL_DID1_PRTNO_5P56 0x004C0000 // LM3S5P56 592 #define SYSCTL_DID1_PRTNO_5R31 0x00070000 // LM3S5R31 593 #define SYSCTL_DID1_PRTNO_5R36 0x004B0000 // LM3S5R36 594 #define SYSCTL_DID1_PRTNO_5T36 0x00470000 // LM3S5T36 595 #define SYSCTL_DID1_PRTNO_5U91 0x007F0000 // LM3S5U91 596 #define SYSCTL_DID1_PRTNO_5Y36 0x00460000 // LM3S5Y36 597 #define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100 598 #define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110 599 #define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420 600 #define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422 601 #define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432 602 #define SYSCTL_DID1_PRTNO_6537 0x00760000 // LM3S6537 603 #define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610 604 #define SYSCTL_DID1_PRTNO_6611 0x00E70000 // LM3S6611 605 #define SYSCTL_DID1_PRTNO_6618 0x00E60000 // LM3S6618 606 #define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633 607 #define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637 608 #define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730 609 #define SYSCTL_DID1_PRTNO_6753 0x00770000 // LM3S6753 610 #define SYSCTL_DID1_PRTNO_6816 0x00D10000 // LM3S6816 611 #define SYSCTL_DID1_PRTNO_6911 0x00E90000 // LM3S6911 612 #define SYSCTL_DID1_PRTNO_6916 0x00D30000 // LM3S6916 613 #define SYSCTL_DID1_PRTNO_6918 0x00E80000 // LM3S6918 614 #define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938 615 #define SYSCTL_DID1_PRTNO_6950 0x00720000 // LM3S6950 616 #define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952 617 #define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965 618 #define SYSCTL_DID1_PRTNO_6C11 0x00AA0000 // LM3S6C11 619 #define SYSCTL_DID1_PRTNO_6C65 0x00AC0000 // LM3S6C65 620 #define SYSCTL_DID1_PRTNO_6G11 0x009F0000 // LM3S6G11 621 #define SYSCTL_DID1_PRTNO_6G65 0x00AB0000 // LM3S6G65 622 #define SYSCTL_DID1_PRTNO_8530 0x00640000 // LM3S8530 623 #define SYSCTL_DID1_PRTNO_8538 0x008E0000 // LM3S8538 624 #define SYSCTL_DID1_PRTNO_8630 0x00610000 // LM3S8630 625 #define SYSCTL_DID1_PRTNO_8730 0x00630000 // LM3S8730 626 #define SYSCTL_DID1_PRTNO_8733 0x008D0000 // LM3S8733 627 #define SYSCTL_DID1_PRTNO_8738 0x00860000 // LM3S8738 628 #define SYSCTL_DID1_PRTNO_8930 0x00650000 // LM3S8930 629 #define SYSCTL_DID1_PRTNO_8933 0x008C0000 // LM3S8933 630 #define SYSCTL_DID1_PRTNO_8938 0x00880000 // LM3S8938 631 #define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962 632 #define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970 633 #define SYSCTL_DID1_PRTNO_8971 0x00D70000 // LM3S8971 634 #define SYSCTL_DID1_PRTNO_8C62 0x00AE0000 // LM3S8C62 635 #define SYSCTL_DID1_PRTNO_8G62 0x00AD0000 // LM3S8G62 636 #define SYSCTL_DID1_PRTNO_9781 0x00CF0000 // LM3S9781 637 #define SYSCTL_DID1_PRTNO_9790 0x00670000 // LM3S9790 638 #define SYSCTL_DID1_PRTNO_9792 0x006B0000 // LM3S9792 639 #define SYSCTL_DID1_PRTNO_9971 0x002D0000 // LM3S9971 640 #define SYSCTL_DID1_PRTNO_9997 0x00200000 // LM3S9997 641 #define SYSCTL_DID1_PRTNO_9B81 0x00D00000 // LM3S9B81 642 #define SYSCTL_DID1_PRTNO_9B90 0x00660000 // LM3S9B90 643 #define SYSCTL_DID1_PRTNO_9B92 0x006A0000 // LM3S9B92 644 #define SYSCTL_DID1_PRTNO_9B95 0x006E0000 // LM3S9B95 645 #define SYSCTL_DID1_PRTNO_9B96 0x006F0000 // LM3S9B96 646 #define SYSCTL_DID1_PRTNO_9BN2 0x001D0000 // LM3S9BN2 647 #define SYSCTL_DID1_PRTNO_9BN5 0x001E0000 // LM3S9BN5 648 #define SYSCTL_DID1_PRTNO_9BN6 0x001F0000 // LM3S9BN6 649 #define SYSCTL_DID1_PRTNO_9C97 0x00700000 // LM3S9C97 650 #define SYSCTL_DID1_PRTNO_9CN5 0x007A0000 // LM3S9CN5 651 #define SYSCTL_DID1_PRTNO_9D81 0x00A90000 // LM3S9D81 652 #define SYSCTL_DID1_PRTNO_9D90 0x007E0000 // LM3S9D90 653 #define SYSCTL_DID1_PRTNO_9D92 0x00920000 // LM3S9D92 654 #define SYSCTL_DID1_PRTNO_9D95 0x00C80000 // LM3S9D95 655 #define SYSCTL_DID1_PRTNO_9D96 0x009D0000 // LM3S9D96 656 #define SYSCTL_DID1_PRTNO_9DN5 0x007B0000 // LM3S9DN5 657 #define SYSCTL_DID1_PRTNO_9DN6 0x007C0000 // LM3S9DN6 658 #define SYSCTL_DID1_PRTNO_9G97 0x00600000 // LM3S9G97 659 #define SYSCTL_DID1_PRTNO_9GN5 0x00790000 // LM3S9GN5 660 #define SYSCTL_DID1_PRTNO_9L71 0x001B0000 // LM3S9L71 661 #define SYSCTL_DID1_PRTNO_9L97 0x00180000 // LM3S9L97 662 #define SYSCTL_DID1_PRTNO_9U81 0x00A80000 // LM3S9U81 663 #define SYSCTL_DID1_PRTNO_9U90 0x007D0000 // LM3S9U90 664 #define SYSCTL_DID1_PRTNO_9U92 0x00900000 // LM3S9U92 665 #define SYSCTL_DID1_PRTNO_9U95 0x00B70000 // LM3S9U95 666 #define SYSCTL_DID1_PRTNO_9U96 0x009B0000 // LM3S9U96 667 #define SYSCTL_DID1_PRTNO_LM4F110B2QR \ 668 0x00180000 // LM4F110B2QR 669 #define SYSCTL_DID1_PRTNO_LM4F110C4QR \ 670 0x00190000 // LM4F110C4QR 671 #define SYSCTL_DID1_PRTNO_LM4F110E5QR \ 672 0x00100000 // LM4F110E5QR 673 #define SYSCTL_DID1_PRTNO_LM4F110H5QR \ 674 0x00110000 // LM4F110H5QR 675 #define SYSCTL_DID1_PRTNO_LM4F111B2QR \ 676 0x00220000 // LM4F111B2QR 677 #define SYSCTL_DID1_PRTNO_LM4F111C4QR \ 678 0x00230000 // LM4F111C4QR 679 #define SYSCTL_DID1_PRTNO_LM4F111E5QR \ 680 0x00200000 // LM4F111E5QR 681 #define SYSCTL_DID1_PRTNO_LM4F111H5QR \ 682 0x00210000 // LM4F111H5QR 683 #define SYSCTL_DID1_PRTNO_LM4F112C4QC \ 684 0x00360000 // LM4F112C4QC 685 #define SYSCTL_DID1_PRTNO_LM4F112E5QC \ 686 0x00300000 // LM4F112E5QC 687 #define SYSCTL_DID1_PRTNO_LM4F112H5QC \ 688 0x00310000 // LM4F112H5QC 689 #define SYSCTL_DID1_PRTNO_LM4F112H5QD \ 690 0x00350000 // LM4F112H5QD 691 #define SYSCTL_DID1_PRTNO_LM4F120B2QR \ 692 0x00010000 // LM4F120B2QR 693 #define SYSCTL_DID1_PRTNO_LM4F120C4QR \ 694 0x00020000 // LM4F120C4QR 695 #define SYSCTL_DID1_PRTNO_LM4F120E5QR \ 696 0x00030000 // LM4F120E5QR 697 #define SYSCTL_DID1_PRTNO_LM4F120H5QR \ 698 0x00040000 // LM4F120H5QR 699 #define SYSCTL_DID1_PRTNO_LM4F121B2QR \ 700 0x00080000 // LM4F121B2QR 701 #define SYSCTL_DID1_PRTNO_LM4F121C4QR \ 702 0x00090000 // LM4F121C4QR 703 #define SYSCTL_DID1_PRTNO_LM4F121E5QR \ 704 0x000A0000 // LM4F121E5QR 705 #define SYSCTL_DID1_PRTNO_LM4F121H5QR \ 706 0x000B0000 // LM4F121H5QR 707 #define SYSCTL_DID1_PRTNO_LM4F122C4QC \ 708 0x00D00000 // LM4F122C4QC 709 #define SYSCTL_DID1_PRTNO_LM4F122E5QC \ 710 0x00D10000 // LM4F122E5QC 711 #define SYSCTL_DID1_PRTNO_LM4F122H5QC \ 712 0x00D20000 // LM4F122H5QC 713 #define SYSCTL_DID1_PRTNO_LM4F122H5QD \ 714 0x00D60000 // LM4F122H5QD 715 #define SYSCTL_DID1_PRTNO_LM4F130C4QR \ 716 0x00480000 // LM4F130C4QR 717 #define SYSCTL_DID1_PRTNO_LM4F130E5QR \ 718 0x00400000 // LM4F130E5QR 719 #define SYSCTL_DID1_PRTNO_LM4F130H5QR \ 720 0x00410000 // LM4F130H5QR 721 #define SYSCTL_DID1_PRTNO_LM4F131C4QR \ 722 0x00520000 // LM4F131C4QR 723 #define SYSCTL_DID1_PRTNO_LM4F131E5QR \ 724 0x00500000 // LM4F131E5QR 725 #define SYSCTL_DID1_PRTNO_LM4F131H5QR \ 726 0x00510000 // LM4F131H5QR 727 #define SYSCTL_DID1_PRTNO_LM4F132C4QC \ 728 0x00660000 // LM4F132C4QC 729 #define SYSCTL_DID1_PRTNO_LM4F132E5QC \ 730 0x00600000 // LM4F132E5QC 731 #define SYSCTL_DID1_PRTNO_LM4F132H5QC \ 732 0x00610000 // LM4F132H5QC 733 #define SYSCTL_DID1_PRTNO_LM4F132H5QD \ 734 0x00650000 // LM4F132H5QD 735 #define SYSCTL_DID1_PRTNO_LM4F210E5QR \ 736 0x00700000 // LM4F210E5QR 737 #define SYSCTL_DID1_PRTNO_LM4F210H5QR \ 738 0x00730000 // LM4F210H5QR 739 #define SYSCTL_DID1_PRTNO_LM4F211E5QR \ 740 0x00800000 // LM4F211E5QR 741 #define SYSCTL_DID1_PRTNO_LM4F211H5QR \ 742 0x00830000 // LM4F211H5QR 743 #define SYSCTL_DID1_PRTNO_LM4F212H5BB \ 744 0x00E90000 // LM4F212H5BB 745 #define SYSCTL_DID1_PRTNO_LM4F212H5QC \ 746 0x00C40000 // LM4F212H5QC 747 #define SYSCTL_DID1_PRTNO_LM4F212H5QD \ 748 0x00C60000 // LM4F212H5QD 749 #define SYSCTL_DID1_PRTNO_LM4F230E5QR \ 750 0x00A00000 // LM4F230E5QR 751 #define SYSCTL_DID1_PRTNO_LM4F230H5QR \ 752 0x00A10000 // LM4F230H5QR 753 #define SYSCTL_DID1_PRTNO_LM4F231E5QR \ 754 0x00B00000 // LM4F231E5QR 755 #define SYSCTL_DID1_PRTNO_LM4F231H5QR \ 756 0x00B10000 // LM4F231H5QR 757 #define SYSCTL_DID1_PRTNO_LM4F232E5QC \ 758 0x00C00000 // LM4F232E5QC 759 #define SYSCTL_DID1_PRTNO_LM4F232H5BB \ 760 0x00E30000 // LM4F232H5BB 761 #define SYSCTL_DID1_PRTNO_LM4F232H5QC \ 762 0x00C10000 // LM4F232H5QC 763 #define SYSCTL_DID1_PRTNO_LM4F232H5QD \ 764 0x00C50000 // LM4F232H5QD 765 #define SYSCTL_DID1_PRTNO_LM4FS1AH5BB \ 766 0x00E50000 // LM4FS1AH5BB 767 #define SYSCTL_DID1_PRTNO_LM4FS1GH5BB \ 768 0x00EA0000 // LM4FS1GH5BB 769 #define SYSCTL_DID1_PRTNO_LM4FS99H5BB \ 770 0x00E40000 // LM4FS99H5BB 771 #define SYSCTL_DID1_PRTNO_LM4FSXAH5BB \ 772 0x00E00000 // LM4FSXAH5BB 773 #define SYSCTL_DID1_PRTNO_LM4FSXLH5BB \ 774 0x00E10000 // LM4FSXLH5BB 775 #define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count 776 #define SYSCTL_DID1_PINCNT_28 0x00000000 // 28-pin package 777 #define SYSCTL_DID1_PINCNT_48 0x00002000 // 48-pin package 778 #define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin package 779 #define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin package 780 #define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin package 781 #define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin package 782 #define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range 783 #define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C 784 // to 70C) 785 #define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range 786 // (-40C to 85C) 787 #define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C 788 // to 105C) 789 #define SYSCTL_DID1_PKG_M 0x00000018 // Package Type 790 #define SYSCTL_DID1_PKG_SOIC 0x00000000 // SOIC package 791 #define SYSCTL_DID1_PKG_QFP 0x00000008 // LQFP package 792 #define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package 793 #define SYSCTL_DID1_PKG_QFN 0x00000018 // QFN package 794 #define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance 795 #define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status 796 #define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified) 797 #define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified) 798 #define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified 799 #define SYSCTL_DID1_PRTNO_S 16 // Part number shift 800 801 //***************************************************************************** 802 // 803 // The following are defines for the bit fields in the SYSCTL_DC0 register. 804 // 805 //***************************************************************************** 806 #define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size 807 #define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM 808 #define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM 809 #define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM 810 #define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM 811 #define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM 812 #define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM 813 #define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM 814 #define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM 815 #define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM 816 #define SYSCTL_DC0_SRAMSZ_48KB 0x00BF0000 // 48 KB of SRAM 817 #define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM 818 #define SYSCTL_DC0_SRAMSZ_96KB 0x017F0000 // 96 KB of SRAM 819 #define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size 820 #define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash 821 #define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash 822 #define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash 823 #define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash 824 #define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash 825 #define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash 826 #define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash 827 #define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash 828 #define SYSCTL_DC0_FLASHSZ_384K 0x000000BF // 384 KB of Flash 829 #define SYSCTL_DC0_FLASHSZ_512K 0x000000FF // 512 KB of Flash 830 #define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift 831 #define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift 832 833 //***************************************************************************** 834 // 835 // The following are defines for the bit fields in the SYSCTL_DC1 register. 836 // 837 //***************************************************************************** 838 #define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present 839 #define SYSCTL_DC1_CAN2 0x04000000 // CAN Module 2 Present 840 #define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present 841 #define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present 842 #define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present 843 #define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present 844 #define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present 845 #define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present 846 #define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider 847 #define SYSCTL_DC1_MINSYSDIV_100 \ 848 0x00001000 // Divide VCO (400MHZ) by 5 minimum 849 #define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Divide VCO (400MHZ) by 2*2 + 2 = 850 // 6 minimum 851 #define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock 852 // with a PLL divider of 4 853 #define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock 854 // with a PLL divider of 5 855 #define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a 856 // PLL divider of 8 857 #define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a 858 // PLL divider of 10 859 #define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed 860 #define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second 861 #define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second 862 #define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second 863 #define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second 864 #define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed 865 #define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second 866 #define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second 867 #define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second 868 #define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second 869 #define SYSCTL_DC1_MPU 0x00000080 // MPU Present 870 #define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present 871 #define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present 872 #define SYSCTL_DC1_PLL 0x00000010 // PLL Present 873 #define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present 874 #define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present 875 #define SYSCTL_DC1_SWD 0x00000002 // SWD Present 876 #define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present 877 878 //***************************************************************************** 879 // 880 // The following are defines for the bit fields in the SYSCTL_DC2 register. 881 // 882 //***************************************************************************** 883 #define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present 884 #define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present 885 #define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present 886 #define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present 887 #define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present 888 #define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present 889 #define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present 890 #define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present 891 #define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present 892 #define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed 893 #define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present 894 #define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed 895 #define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present 896 #define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present 897 #define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present 898 #define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present 899 #define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present 900 #define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present 901 #define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present 902 #define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present 903 904 //***************************************************************************** 905 // 906 // The following are defines for the bit fields in the SYSCTL_DC3 register. 907 // 908 //***************************************************************************** 909 #define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available 910 #define SYSCTL_DC3_CCP5 0x20000000 // CCP5 Pin Present 911 #define SYSCTL_DC3_CCP4 0x10000000 // CCP4 Pin Present 912 #define SYSCTL_DC3_CCP3 0x08000000 // CCP3 Pin Present 913 #define SYSCTL_DC3_CCP2 0x04000000 // CCP2 Pin Present 914 #define SYSCTL_DC3_CCP1 0x02000000 // CCP1 Pin Present 915 #define SYSCTL_DC3_CCP0 0x01000000 // CCP0 Pin Present 916 #define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present 917 #define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present 918 #define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present 919 #define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present 920 #define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present 921 #define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present 922 #define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present 923 #define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present 924 #define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present 925 #define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present 926 #define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present 927 #define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present 928 #define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present 929 #define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present 930 #define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present 931 #define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present 932 #define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present 933 #define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present 934 #define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present 935 #define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present 936 #define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present 937 #define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present 938 #define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present 939 #define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present 940 941 //***************************************************************************** 942 // 943 // The following are defines for the bit fields in the SYSCTL_DC4 register. 944 // 945 //***************************************************************************** 946 #define SYSCTL_DC4_ETH 0x50000000 // Ethernet present 947 #define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present 948 #define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present 949 #define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable 950 #define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate 951 #define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present 952 #define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present 953 #define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present 954 #define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present 955 #define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present 956 #define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present 957 #define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present 958 #define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present 959 #define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present 960 #define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present 961 #define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present 962 #define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present 963 #define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present 964 965 //***************************************************************************** 966 // 967 // The following are defines for the bit fields in the SYSCTL_DC5 register. 968 // 969 //***************************************************************************** 970 #define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present 971 #define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present 972 #define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present 973 #define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present 974 #define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active 975 #define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active 976 #define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present 977 #define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present 978 #define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present 979 #define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present 980 #define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present 981 #define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present 982 #define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present 983 #define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present 984 985 //***************************************************************************** 986 // 987 // The following are defines for the bit fields in the SYSCTL_DC6 register. 988 // 989 //***************************************************************************** 990 #define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present 991 #define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present 992 #define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only 993 #define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host 994 #define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG 995 996 //***************************************************************************** 997 // 998 // The following are defines for the bit fields in the SYSCTL_DC7 register. 999 // 1000 //***************************************************************************** 1001 #define SYSCTL_DC7_SW 0x40000000 // Software transfer on uDMA Ch30 1002 #define SYSCTL_DC7_DMACH30 0x40000000 // SW 1003 #define SYSCTL_DC7_DMACH29 0x20000000 // I2S0_TX / CAN1_TX 1004 #define SYSCTL_DC7_DMACH28 0x10000000 // I2S0_RX / CAN1_RX 1005 #define SYSCTL_DC7_DMACH27 0x08000000 // CAN1_TX / ADC1_SS3 1006 #define SYSCTL_DC7_DMACH26 0x04000000 // CAN1_RX / ADC1_SS2 1007 #define SYSCTL_DC7_DMACH25 0x02000000 // SSI1_TX / ADC1_SS1 1008 #define SYSCTL_DC7_SSI1_TX 0x02000000 // SSI1 TX on uDMA Ch25 1009 #define SYSCTL_DC7_SSI1_RX 0x01000000 // SSI1 RX on uDMA Ch24 1010 #define SYSCTL_DC7_DMACH24 0x01000000 // SSI1_RX / ADC1_SS0 1011 #define SYSCTL_DC7_UART1_TX 0x00800000 // UART1 TX on uDMA Ch23 1012 #define SYSCTL_DC7_DMACH23 0x00800000 // UART1_TX / CAN2_TX 1013 #define SYSCTL_DC7_DMACH22 0x00400000 // UART1_RX / CAN2_RX 1014 #define SYSCTL_DC7_UART1_RX 0x00400000 // UART1 RX on uDMA Ch22 1015 #define SYSCTL_DC7_DMACH21 0x00200000 // Timer1B / EPI0_WFIFO 1016 #define SYSCTL_DC7_DMACH20 0x00100000 // Timer1A / EPI0_NBRFIFO 1017 #define SYSCTL_DC7_DMACH19 0x00080000 // Timer0B / Timer1B 1018 #define SYSCTL_DC7_DMACH18 0x00040000 // Timer0A / Timer1A 1019 #define SYSCTL_DC7_DMACH17 0x00020000 // ADC0_SS3 1020 #define SYSCTL_DC7_DMACH16 0x00010000 // ADC0_SS2 1021 #define SYSCTL_DC7_DMACH15 0x00008000 // ADC0_SS1 / Timer2B 1022 #define SYSCTL_DC7_DMACH14 0x00004000 // ADC0_SS0 / Timer2A 1023 #define SYSCTL_DC7_DMACH13 0x00002000 // CAN0_TX / UART2_TX 1024 #define SYSCTL_DC7_DMACH12 0x00001000 // CAN0_RX / UART2_RX 1025 #define SYSCTL_DC7_SSI0_TX 0x00000800 // SSI0 TX on uDMA Ch11 1026 #define SYSCTL_DC7_DMACH11 0x00000800 // SSI0_TX / SSI1_TX 1027 #define SYSCTL_DC7_SSI0_RX 0x00000400 // SSI0 RX on uDMA Ch10 1028 #define SYSCTL_DC7_DMACH10 0x00000400 // SSI0_RX / SSI1_RX 1029 #define SYSCTL_DC7_UART0_TX 0x00000200 // UART0 TX on uDMA Ch9 1030 #define SYSCTL_DC7_DMACH9 0x00000200 // UART0_TX / UART1_TX 1031 #define SYSCTL_DC7_DMACH8 0x00000100 // UART0_RX / UART1_RX 1032 #define SYSCTL_DC7_UART0_RX 0x00000100 // UART0 RX on uDMA Ch8 1033 #define SYSCTL_DC7_DMACH7 0x00000080 // ETH_TX / Timer2B 1034 #define SYSCTL_DC7_DMACH6 0x00000040 // ETH_RX / Timer2A 1035 #define SYSCTL_DC7_DMACH5 0x00000020 // USB_EP3_TX / Timer2B 1036 #define SYSCTL_DC7_USB_EP3_TX 0x00000020 // USB EP3 TX on uDMA Ch5 1037 #define SYSCTL_DC7_USB_EP3_RX 0x00000010 // USB EP3 RX on uDMA Ch4 1038 #define SYSCTL_DC7_DMACH4 0x00000010 // USB_EP3_RX / Timer2A 1039 #define SYSCTL_DC7_USB_EP2_TX 0x00000008 // USB EP2 TX on uDMA Ch3 1040 #define SYSCTL_DC7_DMACH3 0x00000008 // USB_EP2_TX / Timer3B 1041 #define SYSCTL_DC7_USB_EP2_RX 0x00000004 // USB EP2 RX on uDMA Ch2 1042 #define SYSCTL_DC7_DMACH2 0x00000004 // USB_EP2_RX / Timer3A 1043 #define SYSCTL_DC7_USB_EP1_TX 0x00000002 // USB EP1 TX on uDMA Ch1 1044 #define SYSCTL_DC7_DMACH1 0x00000002 // USB_EP1_TX / UART2_TX 1045 #define SYSCTL_DC7_DMACH0 0x00000001 // USB_EP1_RX / UART2_RX 1046 #define SYSCTL_DC7_USB_EP1_RX 0x00000001 // USB EP1 RX on uDMA Ch0 1047 1048 //***************************************************************************** 1049 // 1050 // The following are defines for the bit fields in the SYSCTL_DC8 register. 1051 // 1052 //***************************************************************************** 1053 #define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present 1054 #define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present 1055 #define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present 1056 #define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present 1057 #define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present 1058 #define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present 1059 #define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present 1060 #define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present 1061 #define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present 1062 #define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present 1063 #define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present 1064 #define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present 1065 #define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present 1066 #define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present 1067 #define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present 1068 #define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present 1069 #define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present 1070 #define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present 1071 #define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present 1072 #define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present 1073 #define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present 1074 #define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present 1075 #define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present 1076 #define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present 1077 #define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present 1078 #define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present 1079 #define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present 1080 #define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present 1081 #define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present 1082 #define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present 1083 #define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present 1084 #define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present 1085 1086 //***************************************************************************** 1087 // 1088 // The following are defines for the bit fields in the SYSCTL_PBORCTL register. 1089 // 1090 //***************************************************************************** 1091 #define SYSCTL_PBORCTL_BORTIM_M 0x0000FFFC // BOR Time Delay 1092 #define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR Interrupt or Reset 1093 #define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR Wait and Check for Noise 1094 #define SYSCTL_PBORCTL_BORTIM_S 2 1095 1096 //***************************************************************************** 1097 // 1098 // The following are defines for the bit fields in the SYSCTL_LDOPCTL register. 1099 // 1100 //***************************************************************************** 1101 #define SYSCTL_LDOPCTL_M 0x0000003F // LDO Output Voltage 1102 #define SYSCTL_LDOPCTL_2_50V 0x00000000 // 2.50 1103 #define SYSCTL_LDOPCTL_2_45V 0x00000001 // 2.45 1104 #define SYSCTL_LDOPCTL_2_40V 0x00000002 // 2.40 1105 #define SYSCTL_LDOPCTL_2_35V 0x00000003 // 2.35 1106 #define SYSCTL_LDOPCTL_2_30V 0x00000004 // 2.30 1107 #define SYSCTL_LDOPCTL_2_25V 0x00000005 // 2.25 1108 #define SYSCTL_LDOPCTL_2_75V 0x0000001B // 2.75 1109 #define SYSCTL_LDOPCTL_2_70V 0x0000001C // 2.70 1110 #define SYSCTL_LDOPCTL_2_65V 0x0000001D // 2.65 1111 #define SYSCTL_LDOPCTL_2_60V 0x0000001E // 2.60 1112 #define SYSCTL_LDOPCTL_2_55V 0x0000001F // 2.55 1113 1114 //***************************************************************************** 1115 // 1116 // The following are defines for the bit fields in the SYSCTL_SRCR0 register. 1117 // 1118 //***************************************************************************** 1119 #define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control 1120 #define SYSCTL_SRCR0_CAN2 0x04000000 // CAN2 Reset Control 1121 #define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control 1122 #define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control 1123 #define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control 1124 #define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control 1125 #define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control 1126 #define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control 1127 #define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control 1128 1129 //***************************************************************************** 1130 // 1131 // The following are defines for the bit fields in the SYSCTL_SRCR1 register. 1132 // 1133 //***************************************************************************** 1134 #define SYSCTL_SRCR1_EPI0 0x40000000 // EPI0 Reset Control 1135 #define SYSCTL_SRCR1_I2S0 0x10000000 // I2S0 Reset Control 1136 #define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control 1137 #define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control 1138 #define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control 1139 #define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control 1140 #define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control 1141 #define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control 1142 #define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control 1143 #define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control 1144 #define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control 1145 #define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control 1146 #define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control 1147 #define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control 1148 #define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control 1149 #define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control 1150 #define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control 1151 #define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control 1152 1153 //***************************************************************************** 1154 // 1155 // The following are defines for the bit fields in the SYSCTL_SRCR2 register. 1156 // 1157 //***************************************************************************** 1158 #define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control 1159 #define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control 1160 #define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control 1161 #define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control 1162 #define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control 1163 #define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control 1164 #define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control 1165 #define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control 1166 #define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control 1167 #define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control 1168 #define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control 1169 #define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control 1170 #define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control 1171 1172 //***************************************************************************** 1173 // 1174 // The following are defines for the bit fields in the SYSCTL_RIS register. 1175 // 1176 //***************************************************************************** 1177 #define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt 1178 // Status 1179 #define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt 1180 // Status 1181 #define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status 1182 #define SYSCTL_RIS_CLRIS 0x00000020 // Current Limit Raw Interrupt 1183 // Status 1184 #define SYSCTL_RIS_IOFRIS 0x00000010 // Internal Oscillator Fault Raw 1185 // Interrupt Status 1186 #define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw 1187 // Interrupt Status 1188 #define SYSCTL_RIS_LDORIS 0x00000004 // LDO Power Unregulated Raw 1189 // Interrupt Status 1190 #define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt 1191 // Status 1192 #define SYSCTL_RIS_PLLFRIS 0x00000001 // PLL Fault Raw Interrupt Status 1193 1194 //***************************************************************************** 1195 // 1196 // The following are defines for the bit fields in the SYSCTL_IMC register. 1197 // 1198 //***************************************************************************** 1199 #define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask 1200 #define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask 1201 #define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask 1202 #define SYSCTL_IMC_CLIM 0x00000020 // Current Limit Interrupt Mask 1203 #define SYSCTL_IMC_IOFIM 0x00000010 // Internal Oscillator Fault 1204 // Interrupt Mask 1205 #define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt 1206 // Mask 1207 #define SYSCTL_IMC_LDOIM 0x00000004 // LDO Power Unregulated Interrupt 1208 // Mask 1209 #define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask 1210 #define SYSCTL_IMC_PLLFIM 0x00000001 // PLL Fault Interrupt Mask 1211 1212 //***************************************************************************** 1213 // 1214 // The following are defines for the bit fields in the SYSCTL_MISC register. 1215 // 1216 //***************************************************************************** 1217 #define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt 1218 // Status 1219 #define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt 1220 // Status 1221 #define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status 1222 #define SYSCTL_MISC_CLMIS 0x00000020 // Current Limit Masked Interrupt 1223 // Status 1224 #define SYSCTL_MISC_IOFMIS 0x00000010 // Internal Oscillator Fault Masked 1225 // Interrupt Status 1226 #define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked 1227 // Interrupt Status 1228 #define SYSCTL_MISC_LDOMIS 0x00000004 // LDO Power Unregulated Masked 1229 // Interrupt Status 1230 #define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status 1231 1232 //***************************************************************************** 1233 // 1234 // The following are defines for the bit fields in the SYSCTL_RESC register. 1235 // 1236 //***************************************************************************** 1237 #define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset 1238 #define SYSCTL_RESC_LDO 0x00000020 // LDO Reset 1239 #define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset 1240 #define SYSCTL_RESC_SW 0x00000010 // Software Reset 1241 #define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset 1242 #define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset 1243 #define SYSCTL_RESC_POR 0x00000002 // Power-On Reset 1244 #define SYSCTL_RESC_EXT 0x00000001 // External Reset 1245 1246 //***************************************************************************** 1247 // 1248 // The following are defines for the bit fields in the SYSCTL_RCC register. 1249 // 1250 //***************************************************************************** 1251 #define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating 1252 #define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor 1253 #define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 1254 #define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 1255 #define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 1256 #define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 1257 #define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 1258 #define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 1259 #define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 1260 #define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 1261 #define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 1262 #define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 1263 #define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 1264 #define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 1265 #define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 1266 #define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 1267 #define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 1268 #define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider 1269 #define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor 1270 #define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor 1271 #define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 1272 #define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 1273 #define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 1274 #define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 1275 #define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 1276 #define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 1277 #define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down 1278 #define SYSCTL_RCC_OEN 0x00001000 // PLL Output Enable 1279 #define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass 1280 #define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value 1281 #define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // 1 MHz 1282 #define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // 1.8432 MHz 1283 #define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // 2 MHz 1284 #define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // 2.4576 MHz 1285 #define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // 3.579545 MHz 1286 #define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // 3.6864 MHz 1287 #define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz 1288 #define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz 1289 #define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz 1290 #define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz 1291 #define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz 1292 #define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz 1293 #define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz 1294 #define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz 1295 #define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz 1296 #define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz 1297 #define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz 1298 #define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz 1299 #define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz 1300 #define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz 1301 #define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz 1302 #define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz 1303 #define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz 1304 #define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz 1305 #define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz 1306 #define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz 1307 #define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz 1308 #define SYSCTL_RCC_PLLVER 0x00000400 // PLL Verification 1309 #define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source 1310 #define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC 1311 #define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC 1312 #define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4 1313 #define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 kHz 1314 #define SYSCTL_RCC_IOSCVER 0x00000008 // Internal Oscillator Verification 1315 // Timer 1316 #define SYSCTL_RCC_MOSCVER 0x00000004 // Main Oscillator Verification 1317 // Timer 1318 #define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal Oscillator Disable 1319 #define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable 1320 #define SYSCTL_RCC_SYSDIV_S 23 1321 #define SYSCTL_RCC_PWMDIV_S 17 // Shift to the PWMDIV field 1322 #define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field 1323 #define SYSCTL_RCC_OSCSRC_S 4 // Shift to the OSCSRC field 1324 1325 //***************************************************************************** 1326 // 1327 // The following are defines for the bit fields in the SYSCTL_PLLCFG register. 1328 // 1329 //***************************************************************************** 1330 #define SYSCTL_PLLCFG_OD_M 0x0000C000 // PLL OD Value 1331 #define SYSCTL_PLLCFG_OD_1 0x00000000 // Divide by 1 1332 #define SYSCTL_PLLCFG_OD_2 0x00004000 // Divide by 2 1333 #define SYSCTL_PLLCFG_OD_4 0x00008000 // Divide by 4 1334 #define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value 1335 #define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value 1336 #define SYSCTL_PLLCFG_F_S 5 1337 #define SYSCTL_PLLCFG_R_S 0 1338 1339 //***************************************************************************** 1340 // 1341 // The following are defines for the bit fields in the SYSCTL_GPIOHBCTL 1342 // register. 1343 // 1344 //***************************************************************************** 1345 #define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced High-Performance 1346 // Bus 1347 #define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced High-Performance 1348 // Bus 1349 #define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced High-Performance 1350 // Bus 1351 #define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance 1352 // Bus 1353 #define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance 1354 // Bus 1355 #define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance 1356 // Bus 1357 #define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance 1358 // Bus 1359 #define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance 1360 // Bus 1361 #define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance 1362 // Bus 1363 1364 //***************************************************************************** 1365 // 1366 // The following are defines for the bit fields in the SYSCTL_RCC2 register. 1367 // 1368 //***************************************************************************** 1369 #define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 1370 #define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200 1371 // MHz 1372 #define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2 1373 #define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2 1374 #define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3 1375 #define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4 1376 #define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5 1377 #define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6 1378 #define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7 1379 #define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8 1380 #define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9 1381 #define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10 1382 #define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11 1383 #define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12 1384 #define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13 1385 #define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14 1386 #define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15 1387 #define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16 1388 #define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17 1389 #define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18 1390 #define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19 1391 #define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20 1392 #define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21 1393 #define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22 1394 #define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23 1395 #define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24 1396 #define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25 1397 #define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26 1398 #define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27 1399 #define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28 1400 #define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29 1401 #define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30 1402 #define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31 1403 #define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32 1404 #define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33 1405 #define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34 1406 #define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35 1407 #define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36 1408 #define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37 1409 #define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38 1410 #define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39 1411 #define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40 1412 #define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41 1413 #define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42 1414 #define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43 1415 #define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44 1416 #define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45 1417 #define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46 1418 #define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47 1419 #define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48 1420 #define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49 1421 #define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50 1422 #define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51 1423 #define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52 1424 #define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53 1425 #define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54 1426 #define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55 1427 #define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56 1428 #define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57 1429 #define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58 1430 #define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59 1431 #define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60 1432 #define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61 1433 #define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62 1434 #define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63 1435 #define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64 1436 #define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2 1437 #define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL 1438 #define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2 1439 #define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2 1440 #define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2 1441 #define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC 1442 #define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC 1443 #define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4 1444 #define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // 30 kHz 1445 #define SYSCTL_RCC2_OSCSRC2_419 0x00000060 // 4.194304 MHz 1446 #define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz 1447 #define SYSCTL_RCC2_SYSDIV2_S 23 1448 1449 //***************************************************************************** 1450 // 1451 // The following are defines for the bit fields in the SYSCTL_MOSCCTL register. 1452 // 1453 //***************************************************************************** 1454 #define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected 1455 #define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action 1456 #define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC 1457 1458 //***************************************************************************** 1459 // 1460 // The following are defines for the bit fields in the SYSCTL_RCGC0 register. 1461 // 1462 //***************************************************************************** 1463 #define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control 1464 #define SYSCTL_RCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control 1465 #define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control 1466 #define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control 1467 #define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control 1468 #define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control 1469 #define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control 1470 #define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed 1471 #define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second 1472 #define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second 1473 #define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second 1474 #define SYSCTL_RCGC0_ADCSPD1M 0x00000300 // 1M samples/second 1475 #define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed 1476 #define SYSCTL_RCGC0_ADC1SPD_125K \ 1477 0x00000000 // 125K samples/second 1478 #define SYSCTL_RCGC0_ADC1SPD_250K \ 1479 0x00000400 // 250K samples/second 1480 #define SYSCTL_RCGC0_ADC1SPD_500K \ 1481 0x00000800 // 500K samples/second 1482 #define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second 1483 #define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed 1484 #define SYSCTL_RCGC0_ADC0SPD_125K \ 1485 0x00000000 // 125K samples/second 1486 #define SYSCTL_RCGC0_ADC0SPD_250K \ 1487 0x00000100 // 250K samples/second 1488 #define SYSCTL_RCGC0_ADC0SPD_500K \ 1489 0x00000200 // 500K samples/second 1490 #define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second 1491 #define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control 1492 #define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control 1493 1494 //***************************************************************************** 1495 // 1496 // The following are defines for the bit fields in the SYSCTL_RCGC1 register. 1497 // 1498 //***************************************************************************** 1499 #define SYSCTL_RCGC1_EPI0 0x40000000 // EPI0 Clock Gating 1500 #define SYSCTL_RCGC1_I2S0 0x10000000 // I2S0 Clock Gating 1501 #define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating 1502 #define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating 1503 #define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating 1504 #define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control 1505 #define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control 1506 #define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control 1507 #define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control 1508 #define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control 1509 #define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control 1510 #define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control 1511 #define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control 1512 #define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control 1513 #define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control 1514 #define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control 1515 #define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control 1516 #define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control 1517 1518 //***************************************************************************** 1519 // 1520 // The following are defines for the bit fields in the SYSCTL_RCGC2 register. 1521 // 1522 //***************************************************************************** 1523 #define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control 1524 #define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control 1525 #define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control 1526 #define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control 1527 #define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control 1528 #define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control 1529 #define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control 1530 #define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control 1531 #define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control 1532 #define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control 1533 #define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control 1534 #define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control 1535 #define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control 1536 1537 //***************************************************************************** 1538 // 1539 // The following are defines for the bit fields in the SYSCTL_SCGC0 register. 1540 // 1541 //***************************************************************************** 1542 #define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control 1543 #define SYSCTL_SCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control 1544 #define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control 1545 #define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control 1546 #define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control 1547 #define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control 1548 #define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control 1549 #define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed 1550 #define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second 1551 #define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second 1552 #define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second 1553 #define SYSCTL_SCGC0_ADCSPD1M 0x00000300 // 1M samples/second 1554 #define SYSCTL_SCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed 1555 #define SYSCTL_SCGC0_ADC1SPD_125K \ 1556 0x00000000 // 125K samples/second 1557 #define SYSCTL_SCGC0_ADC1SPD_250K \ 1558 0x00000400 // 250K samples/second 1559 #define SYSCTL_SCGC0_ADC1SPD_500K \ 1560 0x00000800 // 500K samples/second 1561 #define SYSCTL_SCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second 1562 #define SYSCTL_SCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed 1563 #define SYSCTL_SCGC0_ADC0SPD_125K \ 1564 0x00000000 // 125K samples/second 1565 #define SYSCTL_SCGC0_ADC0SPD_250K \ 1566 0x00000100 // 250K samples/second 1567 #define SYSCTL_SCGC0_ADC0SPD_500K \ 1568 0x00000200 // 500K samples/second 1569 #define SYSCTL_SCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second 1570 #define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control 1571 #define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control 1572 1573 //***************************************************************************** 1574 // 1575 // The following are defines for the bit fields in the SYSCTL_SCGC1 register. 1576 // 1577 //***************************************************************************** 1578 #define SYSCTL_SCGC1_EPI0 0x40000000 // EPI0 Clock Gating 1579 #define SYSCTL_SCGC1_I2S0 0x10000000 // I2S0 Clock Gating 1580 #define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating 1581 #define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating 1582 #define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating 1583 #define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control 1584 #define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control 1585 #define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control 1586 #define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control 1587 #define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control 1588 #define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control 1589 #define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control 1590 #define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control 1591 #define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control 1592 #define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control 1593 #define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control 1594 #define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control 1595 #define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control 1596 1597 //***************************************************************************** 1598 // 1599 // The following are defines for the bit fields in the SYSCTL_SCGC2 register. 1600 // 1601 //***************************************************************************** 1602 #define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control 1603 #define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control 1604 #define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control 1605 #define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control 1606 #define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control 1607 #define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control 1608 #define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control 1609 #define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control 1610 #define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control 1611 #define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control 1612 #define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control 1613 #define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control 1614 #define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control 1615 1616 //***************************************************************************** 1617 // 1618 // The following are defines for the bit fields in the SYSCTL_DCGC0 register. 1619 // 1620 //***************************************************************************** 1621 #define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control 1622 #define SYSCTL_DCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control 1623 #define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control 1624 #define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control 1625 #define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control 1626 #define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control 1627 #define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control 1628 #define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control 1629 #define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control 1630 1631 //***************************************************************************** 1632 // 1633 // The following are defines for the bit fields in the SYSCTL_DCGC1 register. 1634 // 1635 //***************************************************************************** 1636 #define SYSCTL_DCGC1_EPI0 0x40000000 // EPI0 Clock Gating 1637 #define SYSCTL_DCGC1_I2S0 0x10000000 // I2S0 Clock Gating 1638 #define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating 1639 #define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating 1640 #define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating 1641 #define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control 1642 #define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control 1643 #define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control 1644 #define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control 1645 #define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control 1646 #define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control 1647 #define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control 1648 #define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control 1649 #define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control 1650 #define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control 1651 #define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control 1652 #define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control 1653 #define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control 1654 1655 //***************************************************************************** 1656 // 1657 // The following are defines for the bit fields in the SYSCTL_DCGC2 register. 1658 // 1659 //***************************************************************************** 1660 #define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control 1661 #define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control 1662 #define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control 1663 #define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control 1664 #define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control 1665 #define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control 1666 #define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control 1667 #define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control 1668 #define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control 1669 #define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control 1670 #define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control 1671 #define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control 1672 #define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control 1673 1674 //***************************************************************************** 1675 // 1676 // The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG 1677 // register. 1678 // 1679 //***************************************************************************** 1680 #define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override 1681 #define SYSCTL_DSLPCLKCFG_D_1 0x00000000 // System clock /1 1682 #define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2 1683 #define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3 1684 #define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4 1685 #define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5 1686 #define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6 1687 #define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7 1688 #define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8 1689 #define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9 1690 #define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10 1691 #define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11 1692 #define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12 1693 #define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13 1694 #define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14 1695 #define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15 1696 #define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16 1697 #define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17 1698 #define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18 1699 #define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19 1700 #define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20 1701 #define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21 1702 #define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22 1703 #define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23 1704 #define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24 1705 #define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25 1706 #define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26 1707 #define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27 1708 #define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28 1709 #define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29 1710 #define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30 1711 #define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31 1712 #define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32 1713 #define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33 1714 #define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34 1715 #define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35 1716 #define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36 1717 #define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37 1718 #define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38 1719 #define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39 1720 #define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40 1721 #define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41 1722 #define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42 1723 #define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43 1724 #define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44 1725 #define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45 1726 #define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46 1727 #define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47 1728 #define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48 1729 #define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49 1730 #define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50 1731 #define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51 1732 #define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52 1733 #define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53 1734 #define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54 1735 #define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55 1736 #define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56 1737 #define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57 1738 #define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58 1739 #define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59 1740 #define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60 1741 #define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61 1742 #define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62 1743 #define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63 1744 #define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64 1745 #define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source 1746 #define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC 1747 #define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC 1748 #define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz 1749 #define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz 1750 #define SYSCTL_DSLPCLKCFG_PIOSCPD \ 1751 0x00000002 // PIOSC Power Down Request 1752 #define SYSCTL_DSLPCLKCFG_IOSC 0x00000001 // IOSC Clock Source 1753 #define SYSCTL_DSLPCLKCFG_D_S 23 1754 1755 //***************************************************************************** 1756 // 1757 // The following are defines for the bit fields in the SYSCTL_SYSPROP register. 1758 // 1759 //***************************************************************************** 1760 #define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present 1761 1762 //***************************************************************************** 1763 // 1764 // The following are defines for the bit fields in the SYSCTL_PIOSCCAL 1765 // register. 1766 // 1767 //***************************************************************************** 1768 #define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value 1769 #define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration 1770 #define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim 1771 #define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value 1772 #define SYSCTL_PIOSCCAL_UT_S 0 1773 1774 //***************************************************************************** 1775 // 1776 // The following are defines for the bit fields in the SYSCTL_CLKVCLR register. 1777 // 1778 //***************************************************************************** 1779 #define SYSCTL_CLKVCLR_VERCLR 0x00000001 // Clock Verification Clear 1780 1781 //***************************************************************************** 1782 // 1783 // The following are defines for the bit fields in the SYSCTL_PIOSCSTAT 1784 // register. 1785 // 1786 //***************************************************************************** 1787 #define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value 1788 #define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result 1789 #define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been 1790 // attempted 1791 #define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation 1792 // completed to meet 1% accuracy 1793 #define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation 1794 // failed to meet 1% accuracy 1795 #define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value 1796 #define SYSCTL_PIOSCSTAT_DT_S 16 1797 #define SYSCTL_PIOSCSTAT_CT_S 0 1798 1799 //***************************************************************************** 1800 // 1801 // The following are defines for the bit fields in the SYSCTL_LDOARST register. 1802 // 1803 //***************************************************************************** 1804 #define SYSCTL_LDOARST_LDOARST 0x00000001 // LDO Reset 1805 1806 //***************************************************************************** 1807 // 1808 // The following are defines for the bit fields in the SYSCTL_PLLFREQ0 1809 // register. 1810 // 1811 //***************************************************************************** 1812 #define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value 1813 #define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value 1814 #define SYSCTL_PLLFREQ0_MFRAC_S 10 1815 #define SYSCTL_PLLFREQ0_MINT_S 0 1816 1817 //***************************************************************************** 1818 // 1819 // The following are defines for the bit fields in the SYSCTL_PLLFREQ1 1820 // register. 1821 // 1822 //***************************************************************************** 1823 #define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value 1824 #define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value 1825 #define SYSCTL_PLLFREQ1_Q_S 8 1826 #define SYSCTL_PLLFREQ1_N_S 0 1827 1828 //***************************************************************************** 1829 // 1830 // The following are defines for the bit fields in the SYSCTL_PLLSTAT register. 1831 // 1832 //***************************************************************************** 1833 #define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock 1834 1835 //***************************************************************************** 1836 // 1837 // The following are defines for the bit fields in the SYSCTL_I2SMCLKCFG 1838 // register. 1839 // 1840 //***************************************************************************** 1841 #define SYSCTL_I2SMCLKCFG_RXEN 0x80000000 // RX Clock Enable 1842 #define SYSCTL_I2SMCLKCFG_RXI_M 0x3FF00000 // RX Clock Integer Input 1843 #define SYSCTL_I2SMCLKCFG_RXF_M 0x000F0000 // RX Clock Fractional Input 1844 #define SYSCTL_I2SMCLKCFG_TXEN 0x00008000 // TX Clock Enable 1845 #define SYSCTL_I2SMCLKCFG_TXI_M 0x00003FF0 // TX Clock Integer Input 1846 #define SYSCTL_I2SMCLKCFG_TXF_M 0x0000000F // TX Clock Fractional Input 1847 #define SYSCTL_I2SMCLKCFG_RXI_S 20 1848 #define SYSCTL_I2SMCLKCFG_RXF_S 16 1849 #define SYSCTL_I2SMCLKCFG_TXI_S 4 1850 #define SYSCTL_I2SMCLKCFG_TXF_S 0 1851 1852 //***************************************************************************** 1853 // 1854 // The following are defines for the bit fields in the SYSCTL_DC9 register. 1855 // 1856 //***************************************************************************** 1857 #define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present 1858 #define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present 1859 #define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present 1860 #define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present 1861 #define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present 1862 #define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present 1863 #define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present 1864 #define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present 1865 #define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present 1866 #define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present 1867 #define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present 1868 #define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present 1869 #define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present 1870 #define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present 1871 #define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present 1872 #define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present 1873 1874 //***************************************************************************** 1875 // 1876 // The following are defines for the bit fields in the SYSCTL_NVMSTAT register. 1877 // 1878 //***************************************************************************** 1879 #define SYSCTL_NVMSTAT_TPSW 0x00000010 // Third Party Software Present 1880 #define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer 1881 // Active 1882 1883 //***************************************************************************** 1884 // 1885 // The following are defines for the bit fields in the SYSCTL_PPWD register. 1886 // 1887 //***************************************************************************** 1888 #define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present 1889 #define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present 1890 1891 //***************************************************************************** 1892 // 1893 // The following are defines for the bit fields in the SYSCTL_PPTIMER register. 1894 // 1895 //***************************************************************************** 1896 #define SYSCTL_PPTIMER_P5 0x00000020 // Timer 5 Present 1897 #define SYSCTL_PPTIMER_P4 0x00000010 // Timer 4 Present 1898 #define SYSCTL_PPTIMER_P3 0x00000008 // Timer 3 Present 1899 #define SYSCTL_PPTIMER_P2 0x00000004 // Timer 2 Present 1900 #define SYSCTL_PPTIMER_P1 0x00000002 // Timer 1 Present 1901 #define SYSCTL_PPTIMER_P0 0x00000001 // Timer 0 Present 1902 1903 //***************************************************************************** 1904 // 1905 // The following are defines for the bit fields in the SYSCTL_PPGPIO register. 1906 // 1907 //***************************************************************************** 1908 #define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present 1909 #define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present 1910 #define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present 1911 #define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present 1912 #define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present 1913 #define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present 1914 #define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present 1915 #define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present 1916 #define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present 1917 #define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present 1918 #define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present 1919 #define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present 1920 #define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present 1921 #define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present 1922 #define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present 1923 1924 //***************************************************************************** 1925 // 1926 // The following are defines for the bit fields in the SYSCTL_PPDMA register. 1927 // 1928 //***************************************************************************** 1929 #define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present 1930 1931 //***************************************************************************** 1932 // 1933 // The following are defines for the bit fields in the SYSCTL_PPHIB register. 1934 // 1935 //***************************************************************************** 1936 #define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present 1937 1938 //***************************************************************************** 1939 // 1940 // The following are defines for the bit fields in the SYSCTL_PPUART register. 1941 // 1942 //***************************************************************************** 1943 #define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present 1944 #define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present 1945 #define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present 1946 #define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present 1947 #define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present 1948 #define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present 1949 #define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present 1950 #define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present 1951 1952 //***************************************************************************** 1953 // 1954 // The following are defines for the bit fields in the SYSCTL_PPSSI register. 1955 // 1956 //***************************************************************************** 1957 #define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present 1958 #define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present 1959 #define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present 1960 #define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present 1961 1962 //***************************************************************************** 1963 // 1964 // The following are defines for the bit fields in the SYSCTL_PPI2C register. 1965 // 1966 //***************************************************************************** 1967 #define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present 1968 #define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present 1969 #define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present 1970 #define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present 1971 #define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present 1972 #define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present 1973 1974 //***************************************************************************** 1975 // 1976 // The following are defines for the bit fields in the SYSCTL_PPUSB register. 1977 // 1978 //***************************************************************************** 1979 #define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present 1980 1981 //***************************************************************************** 1982 // 1983 // The following are defines for the bit fields in the SYSCTL_PPCAN register. 1984 // 1985 //***************************************************************************** 1986 #define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present 1987 #define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present 1988 1989 //***************************************************************************** 1990 // 1991 // The following are defines for the bit fields in the SYSCTL_PPADC register. 1992 // 1993 //***************************************************************************** 1994 #define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present 1995 #define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present 1996 1997 //***************************************************************************** 1998 // 1999 // The following are defines for the bit fields in the SYSCTL_PPACMP register. 2000 // 2001 //***************************************************************************** 2002 #define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present 2003 2004 //***************************************************************************** 2005 // 2006 // The following are defines for the bit fields in the SYSCTL_PPPWM register. 2007 // 2008 //***************************************************************************** 2009 #define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present 2010 #define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present 2011 2012 //***************************************************************************** 2013 // 2014 // The following are defines for the bit fields in the SYSCTL_PPQEI register. 2015 // 2016 //***************************************************************************** 2017 #define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present 2018 #define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present 2019 2020 //***************************************************************************** 2021 // 2022 // The following are defines for the bit fields in the SYSCTL_PPLPC register. 2023 // 2024 //***************************************************************************** 2025 #define SYSCTL_PPLPC_P0 0x00000001 // LPC Module Present 2026 2027 //***************************************************************************** 2028 // 2029 // The following are defines for the bit fields in the SYSCTL_PPPECI register. 2030 // 2031 //***************************************************************************** 2032 #define SYSCTL_PPPECI_P0 0x00000001 // PECI Module Present 2033 2034 //***************************************************************************** 2035 // 2036 // The following are defines for the bit fields in the SYSCTL_PPFAN register. 2037 // 2038 //***************************************************************************** 2039 #define SYSCTL_PPFAN_P0 0x00000001 // FAN Module Present 2040 2041 //***************************************************************************** 2042 // 2043 // The following are defines for the bit fields in the SYSCTL_PPEEPROM 2044 // register. 2045 // 2046 //***************************************************************************** 2047 #define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present 2048 2049 //***************************************************************************** 2050 // 2051 // The following are defines for the bit fields in the SYSCTL_PPWTIMER 2052 // register. 2053 // 2054 //***************************************************************************** 2055 #define SYSCTL_PPWTIMER_P5 0x00000020 // Wide Timer 5 Present 2056 #define SYSCTL_PPWTIMER_P4 0x00000010 // Wide Timer 4 Present 2057 #define SYSCTL_PPWTIMER_P3 0x00000008 // Wide Timer 3 Present 2058 #define SYSCTL_PPWTIMER_P2 0x00000004 // Wide Timer 2 Present 2059 #define SYSCTL_PPWTIMER_P1 0x00000002 // Wide Timer 1 Present 2060 #define SYSCTL_PPWTIMER_P0 0x00000001 // Wide Timer 0 Present 2061 2062 //***************************************************************************** 2063 // 2064 // The following are defines for the bit fields in the SYSCTL_SRWD register. 2065 // 2066 //***************************************************************************** 2067 #define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset 2068 #define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset 2069 2070 //***************************************************************************** 2071 // 2072 // The following are defines for the bit fields in the SYSCTL_SRTIMER register. 2073 // 2074 //***************************************************************************** 2075 #define SYSCTL_SRTIMER_R5 0x00000020 // Timer 5 Software Reset 2076 #define SYSCTL_SRTIMER_R4 0x00000010 // Timer 4 Software Reset 2077 #define SYSCTL_SRTIMER_R3 0x00000008 // Timer 3 Software Reset 2078 #define SYSCTL_SRTIMER_R2 0x00000004 // Timer 2 Software Reset 2079 #define SYSCTL_SRTIMER_R1 0x00000002 // Timer 1 Software Reset 2080 #define SYSCTL_SRTIMER_R0 0x00000001 // Timer 0 Software Reset 2081 2082 //***************************************************************************** 2083 // 2084 // The following are defines for the bit fields in the SYSCTL_SRGPIO register. 2085 // 2086 //***************************************************************************** 2087 #define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset 2088 #define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset 2089 #define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset 2090 #define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset 2091 #define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset 2092 #define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset 2093 #define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset 2094 #define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset 2095 #define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset 2096 #define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset 2097 #define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset 2098 #define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset 2099 #define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset 2100 #define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset 2101 #define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset 2102 2103 //***************************************************************************** 2104 // 2105 // The following are defines for the bit fields in the SYSCTL_SRDMA register. 2106 // 2107 //***************************************************************************** 2108 #define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset 2109 2110 //***************************************************************************** 2111 // 2112 // The following are defines for the bit fields in the SYSCTL_SRHIB register. 2113 // 2114 //***************************************************************************** 2115 #define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software 2116 // Reset 2117 2118 //***************************************************************************** 2119 // 2120 // The following are defines for the bit fields in the SYSCTL_SRUART register. 2121 // 2122 //***************************************************************************** 2123 #define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset 2124 #define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset 2125 #define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset 2126 #define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset 2127 #define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset 2128 #define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset 2129 #define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset 2130 #define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset 2131 2132 //***************************************************************************** 2133 // 2134 // The following are defines for the bit fields in the SYSCTL_SRSSI register. 2135 // 2136 //***************************************************************************** 2137 #define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset 2138 #define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset 2139 #define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset 2140 #define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset 2141 2142 //***************************************************************************** 2143 // 2144 // The following are defines for the bit fields in the SYSCTL_SRI2C register. 2145 // 2146 //***************************************************************************** 2147 #define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset 2148 #define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset 2149 #define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset 2150 #define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset 2151 #define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset 2152 #define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset 2153 2154 //***************************************************************************** 2155 // 2156 // The following are defines for the bit fields in the SYSCTL_SRUSB register. 2157 // 2158 //***************************************************************************** 2159 #define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset 2160 2161 //***************************************************************************** 2162 // 2163 // The following are defines for the bit fields in the SYSCTL_SRCAN register. 2164 // 2165 //***************************************************************************** 2166 #define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset 2167 #define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset 2168 2169 //***************************************************************************** 2170 // 2171 // The following are defines for the bit fields in the SYSCTL_SRADC register. 2172 // 2173 //***************************************************************************** 2174 #define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset 2175 #define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset 2176 2177 //***************************************************************************** 2178 // 2179 // The following are defines for the bit fields in the SYSCTL_SRACMP register. 2180 // 2181 //***************************************************************************** 2182 #define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0 2183 // Software Reset 2184 2185 //***************************************************************************** 2186 // 2187 // The following are defines for the bit fields in the SYSCTL_SRPWM register. 2188 // 2189 //***************************************************************************** 2190 #define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset 2191 #define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset 2192 2193 //***************************************************************************** 2194 // 2195 // The following are defines for the bit fields in the SYSCTL_SRQEI register. 2196 // 2197 //***************************************************************************** 2198 #define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset 2199 #define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset 2200 2201 //***************************************************************************** 2202 // 2203 // The following are defines for the bit fields in the SYSCTL_SRLPC register. 2204 // 2205 //***************************************************************************** 2206 #define SYSCTL_SRLPC_R0 0x00000001 // LPC Module Software Reset 2207 2208 //***************************************************************************** 2209 // 2210 // The following are defines for the bit fields in the SYSCTL_SRPECI register. 2211 // 2212 //***************************************************************************** 2213 #define SYSCTL_SRPECI_R0 0x00000001 // PECI Module Software Reset 2214 2215 //***************************************************************************** 2216 // 2217 // The following are defines for the bit fields in the SYSCTL_SRFAN register. 2218 // 2219 //***************************************************************************** 2220 #define SYSCTL_SRFAN_R0 0x00000001 // FAN Module Software Reset 2221 2222 //***************************************************************************** 2223 // 2224 // The following are defines for the bit fields in the SYSCTL_SREEPROM 2225 // register. 2226 // 2227 //***************************************************************************** 2228 #define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset 2229 2230 //***************************************************************************** 2231 // 2232 // The following are defines for the bit fields in the SYSCTL_SRWTIMER 2233 // register. 2234 // 2235 //***************************************************************************** 2236 #define SYSCTL_SRWTIMER_R5 0x00000020 // Wide Timer 5 Software Reset 2237 #define SYSCTL_SRWTIMER_R4 0x00000010 // Wide Timer 4 Software Reset 2238 #define SYSCTL_SRWTIMER_R3 0x00000008 // Wide Timer 3 Software Reset 2239 #define SYSCTL_SRWTIMER_R2 0x00000004 // Wide Timer 2 Software Reset 2240 #define SYSCTL_SRWTIMER_R1 0x00000002 // Wide Timer 1 Software Reset 2241 #define SYSCTL_SRWTIMER_R0 0x00000001 // Wide Timer 0 Software Reset 2242 2243 //***************************************************************************** 2244 // 2245 // The following are defines for the bit fields in the SYSCTL_RCGCWD register. 2246 // 2247 //***************************************************************************** 2248 #define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock 2249 // Gating Control 2250 #define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock 2251 // Gating Control 2252 2253 //***************************************************************************** 2254 // 2255 // The following are defines for the bit fields in the SYSCTL_RCGCTIMER 2256 // register. 2257 // 2258 //***************************************************************************** 2259 #define SYSCTL_RCGCTIMER_R5 0x00000020 // Timer 5 Run Mode Clock Gating 2260 // Control 2261 #define SYSCTL_RCGCTIMER_R4 0x00000010 // Timer 4 Run Mode Clock Gating 2262 // Control 2263 #define SYSCTL_RCGCTIMER_R3 0x00000008 // Timer 3 Run Mode Clock Gating 2264 // Control 2265 #define SYSCTL_RCGCTIMER_R2 0x00000004 // Timer 2 Run Mode Clock Gating 2266 // Control 2267 #define SYSCTL_RCGCTIMER_R1 0x00000002 // Timer 1 Run Mode Clock Gating 2268 // Control 2269 #define SYSCTL_RCGCTIMER_R0 0x00000001 // Timer 0 Run Mode Clock Gating 2270 // Control 2271 2272 //***************************************************************************** 2273 // 2274 // The following are defines for the bit fields in the SYSCTL_RCGCGPIO 2275 // register. 2276 // 2277 //***************************************************************************** 2278 #define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock 2279 // Gating Control 2280 #define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock 2281 // Gating Control 2282 #define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock 2283 // Gating Control 2284 #define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock 2285 // Gating Control 2286 #define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock 2287 // Gating Control 2288 #define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock 2289 // Gating Control 2290 #define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock 2291 // Gating Control 2292 #define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock 2293 // Gating Control 2294 #define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock 2295 // Gating Control 2296 #define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock 2297 // Gating Control 2298 #define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock 2299 // Gating Control 2300 #define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock 2301 // Gating Control 2302 #define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock 2303 // Gating Control 2304 #define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock 2305 // Gating Control 2306 #define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock 2307 // Gating Control 2308 2309 //***************************************************************************** 2310 // 2311 // The following are defines for the bit fields in the SYSCTL_RCGCDMA register. 2312 // 2313 //***************************************************************************** 2314 #define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock 2315 // Gating Control 2316 2317 //***************************************************************************** 2318 // 2319 // The following are defines for the bit fields in the SYSCTL_RCGCHIB register. 2320 // 2321 //***************************************************************************** 2322 #define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode 2323 // Clock Gating Control 2324 2325 //***************************************************************************** 2326 // 2327 // The following are defines for the bit fields in the SYSCTL_RCGCUART 2328 // register. 2329 // 2330 //***************************************************************************** 2331 #define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock 2332 // Gating Control 2333 #define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock 2334 // Gating Control 2335 #define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock 2336 // Gating Control 2337 #define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock 2338 // Gating Control 2339 #define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock 2340 // Gating Control 2341 #define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock 2342 // Gating Control 2343 #define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock 2344 // Gating Control 2345 #define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock 2346 // Gating Control 2347 2348 //***************************************************************************** 2349 // 2350 // The following are defines for the bit fields in the SYSCTL_RCGCSSI register. 2351 // 2352 //***************************************************************************** 2353 #define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock 2354 // Gating Control 2355 #define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock 2356 // Gating Control 2357 #define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock 2358 // Gating Control 2359 #define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock 2360 // Gating Control 2361 2362 //***************************************************************************** 2363 // 2364 // The following are defines for the bit fields in the SYSCTL_RCGCI2C register. 2365 // 2366 //***************************************************************************** 2367 #define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock 2368 // Gating Control 2369 #define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock 2370 // Gating Control 2371 #define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock 2372 // Gating Control 2373 #define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock 2374 // Gating Control 2375 #define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock 2376 // Gating Control 2377 #define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock 2378 // Gating Control 2379 2380 //***************************************************************************** 2381 // 2382 // The following are defines for the bit fields in the SYSCTL_RCGCUSB register. 2383 // 2384 //***************************************************************************** 2385 #define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating 2386 // Control 2387 2388 //***************************************************************************** 2389 // 2390 // The following are defines for the bit fields in the SYSCTL_RCGCCAN register. 2391 // 2392 //***************************************************************************** 2393 #define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock 2394 // Gating Control 2395 #define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock 2396 // Gating Control 2397 2398 //***************************************************************************** 2399 // 2400 // The following are defines for the bit fields in the SYSCTL_RCGCADC register. 2401 // 2402 //***************************************************************************** 2403 #define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock 2404 // Gating Control 2405 #define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock 2406 // Gating Control 2407 2408 //***************************************************************************** 2409 // 2410 // The following are defines for the bit fields in the SYSCTL_RCGCACMP 2411 // register. 2412 // 2413 //***************************************************************************** 2414 #define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run 2415 // Mode Clock Gating Control 2416 2417 //***************************************************************************** 2418 // 2419 // The following are defines for the bit fields in the SYSCTL_RCGCPWM register. 2420 // 2421 //***************************************************************************** 2422 #define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock 2423 // Gating Control 2424 #define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock 2425 // Gating Control 2426 2427 //***************************************************************************** 2428 // 2429 // The following are defines for the bit fields in the SYSCTL_RCGCQEI register. 2430 // 2431 //***************************************************************************** 2432 #define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock 2433 // Gating Control 2434 #define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock 2435 // Gating Control 2436 2437 //***************************************************************************** 2438 // 2439 // The following are defines for the bit fields in the SYSCTL_RCGCLPC register. 2440 // 2441 //***************************************************************************** 2442 #define SYSCTL_RCGCLPC_R0 0x00000001 // LPC Module Run Mode Clock Gating 2443 // Control 2444 2445 //***************************************************************************** 2446 // 2447 // The following are defines for the bit fields in the SYSCTL_RCGCPECI 2448 // register. 2449 // 2450 //***************************************************************************** 2451 #define SYSCTL_RCGCPECI_R0 0x00000001 // PECI Module Run Mode Clock 2452 // Gating Control 2453 2454 //***************************************************************************** 2455 // 2456 // The following are defines for the bit fields in the SYSCTL_RCGCFAN register. 2457 // 2458 //***************************************************************************** 2459 #define SYSCTL_RCGCFAN_R0 0x00000001 // FAN Module Run Mode Clock Gating 2460 // Control 2461 2462 //***************************************************************************** 2463 // 2464 // The following are defines for the bit fields in the SYSCTL_RCGCEEPROM 2465 // register. 2466 // 2467 //***************************************************************************** 2468 #define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock 2469 // Gating Control 2470 2471 //***************************************************************************** 2472 // 2473 // The following are defines for the bit fields in the SYSCTL_RCGCWTIMER 2474 // register. 2475 // 2476 //***************************************************************************** 2477 #define SYSCTL_RCGCWTIMER_R5 0x00000020 // Wide Timer 5 Run Mode Clock 2478 // Gating Control 2479 #define SYSCTL_RCGCWTIMER_R4 0x00000010 // Wide Timer 4 Run Mode Clock 2480 // Gating Control 2481 #define SYSCTL_RCGCWTIMER_R3 0x00000008 // Wide Timer 3 Run Mode Clock 2482 // Gating Control 2483 #define SYSCTL_RCGCWTIMER_R2 0x00000004 // Wide Timer 2 Run Mode Clock 2484 // Gating Control 2485 #define SYSCTL_RCGCWTIMER_R1 0x00000002 // Wide Timer 1 Run Mode Clock 2486 // Gating Control 2487 #define SYSCTL_RCGCWTIMER_R0 0x00000001 // Wide Timer 0 Run Mode Clock 2488 // Gating Control 2489 2490 //***************************************************************************** 2491 // 2492 // The following are defines for the bit fields in the SYSCTL_SCGCWD register. 2493 // 2494 //***************************************************************************** 2495 #define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode 2496 // Clock Gating Control 2497 #define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode 2498 // Clock Gating Control 2499 2500 //***************************************************************************** 2501 // 2502 // The following are defines for the bit fields in the SYSCTL_SCGCTIMER 2503 // register. 2504 // 2505 //***************************************************************************** 2506 #define SYSCTL_SCGCTIMER_S5 0x00000020 // Timer 5 Sleep Mode Clock Gating 2507 // Control 2508 #define SYSCTL_SCGCTIMER_S4 0x00000010 // Timer 4 Sleep Mode Clock Gating 2509 // Control 2510 #define SYSCTL_SCGCTIMER_S3 0x00000008 // Timer 3 Sleep Mode Clock Gating 2511 // Control 2512 #define SYSCTL_SCGCTIMER_S2 0x00000004 // Timer 2 Sleep Mode Clock Gating 2513 // Control 2514 #define SYSCTL_SCGCTIMER_S1 0x00000002 // Timer 1 Sleep Mode Clock Gating 2515 // Control 2516 #define SYSCTL_SCGCTIMER_S0 0x00000001 // Timer 0 Sleep Mode Clock Gating 2517 // Control 2518 2519 //***************************************************************************** 2520 // 2521 // The following are defines for the bit fields in the SYSCTL_SCGCGPIO 2522 // register. 2523 // 2524 //***************************************************************************** 2525 #define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock 2526 // Gating Control 2527 #define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock 2528 // Gating Control 2529 #define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock 2530 // Gating Control 2531 #define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock 2532 // Gating Control 2533 #define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock 2534 // Gating Control 2535 #define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock 2536 // Gating Control 2537 #define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock 2538 // Gating Control 2539 #define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock 2540 // Gating Control 2541 #define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock 2542 // Gating Control 2543 #define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock 2544 // Gating Control 2545 #define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock 2546 // Gating Control 2547 #define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock 2548 // Gating Control 2549 #define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock 2550 // Gating Control 2551 #define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock 2552 // Gating Control 2553 #define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock 2554 // Gating Control 2555 2556 //***************************************************************************** 2557 // 2558 // The following are defines for the bit fields in the SYSCTL_SCGCDMA register. 2559 // 2560 //***************************************************************************** 2561 #define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock 2562 // Gating Control 2563 2564 //***************************************************************************** 2565 // 2566 // The following are defines for the bit fields in the SYSCTL_SCGCHIB register. 2567 // 2568 //***************************************************************************** 2569 #define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode 2570 // Clock Gating Control 2571 2572 //***************************************************************************** 2573 // 2574 // The following are defines for the bit fields in the SYSCTL_SCGCUART 2575 // register. 2576 // 2577 //***************************************************************************** 2578 #define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock 2579 // Gating Control 2580 #define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock 2581 // Gating Control 2582 #define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock 2583 // Gating Control 2584 #define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock 2585 // Gating Control 2586 #define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock 2587 // Gating Control 2588 #define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock 2589 // Gating Control 2590 #define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock 2591 // Gating Control 2592 #define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock 2593 // Gating Control 2594 2595 //***************************************************************************** 2596 // 2597 // The following are defines for the bit fields in the SYSCTL_SCGCSSI register. 2598 // 2599 //***************************************************************************** 2600 #define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock 2601 // Gating Control 2602 #define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock 2603 // Gating Control 2604 #define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock 2605 // Gating Control 2606 #define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock 2607 // Gating Control 2608 2609 //***************************************************************************** 2610 // 2611 // The following are defines for the bit fields in the SYSCTL_SCGCI2C register. 2612 // 2613 //***************************************************************************** 2614 #define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock 2615 // Gating Control 2616 #define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock 2617 // Gating Control 2618 #define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock 2619 // Gating Control 2620 #define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock 2621 // Gating Control 2622 #define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock 2623 // Gating Control 2624 #define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock 2625 // Gating Control 2626 2627 //***************************************************************************** 2628 // 2629 // The following are defines for the bit fields in the SYSCTL_SCGCUSB register. 2630 // 2631 //***************************************************************************** 2632 #define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock 2633 // Gating Control 2634 2635 //***************************************************************************** 2636 // 2637 // The following are defines for the bit fields in the SYSCTL_SCGCCAN register. 2638 // 2639 //***************************************************************************** 2640 #define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock 2641 // Gating Control 2642 #define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock 2643 // Gating Control 2644 2645 //***************************************************************************** 2646 // 2647 // The following are defines for the bit fields in the SYSCTL_SCGCADC register. 2648 // 2649 //***************************************************************************** 2650 #define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock 2651 // Gating Control 2652 #define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock 2653 // Gating Control 2654 2655 //***************************************************************************** 2656 // 2657 // The following are defines for the bit fields in the SYSCTL_SCGCACMP 2658 // register. 2659 // 2660 //***************************************************************************** 2661 #define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep 2662 // Mode Clock Gating Control 2663 2664 //***************************************************************************** 2665 // 2666 // The following are defines for the bit fields in the SYSCTL_SCGCPWM register. 2667 // 2668 //***************************************************************************** 2669 #define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock 2670 // Gating Control 2671 #define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock 2672 // Gating Control 2673 2674 //***************************************************************************** 2675 // 2676 // The following are defines for the bit fields in the SYSCTL_SCGCQEI register. 2677 // 2678 //***************************************************************************** 2679 #define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock 2680 // Gating Control 2681 #define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock 2682 // Gating Control 2683 2684 //***************************************************************************** 2685 // 2686 // The following are defines for the bit fields in the SYSCTL_SCGCLPC register. 2687 // 2688 //***************************************************************************** 2689 #define SYSCTL_SCGCLPC_S0 0x00000001 // LPC Module Sleep Mode Clock 2690 // Gating Control 2691 2692 //***************************************************************************** 2693 // 2694 // The following are defines for the bit fields in the SYSCTL_SCGCPECI 2695 // register. 2696 // 2697 //***************************************************************************** 2698 #define SYSCTL_SCGCPECI_S0 0x00000001 // PECI Module Sleep Mode Clock 2699 // Gating Control 2700 2701 //***************************************************************************** 2702 // 2703 // The following are defines for the bit fields in the SYSCTL_SCGCFAN register. 2704 // 2705 //***************************************************************************** 2706 #define SYSCTL_SCGCFAN_S0 0x00000001 // FAN Module Sleep Mode Clock 2707 // Gating Control 2708 2709 //***************************************************************************** 2710 // 2711 // The following are defines for the bit fields in the SYSCTL_SCGCEEPROM 2712 // register. 2713 // 2714 //***************************************************************************** 2715 #define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock 2716 // Gating Control 2717 2718 //***************************************************************************** 2719 // 2720 // The following are defines for the bit fields in the SYSCTL_SCGCWTIMER 2721 // register. 2722 // 2723 //***************************************************************************** 2724 #define SYSCTL_SCGCWTIMER_S5 0x00000020 // Wide Timer 5 Sleep Mode Clock 2725 // Gating Control 2726 #define SYSCTL_SCGCWTIMER_S4 0x00000010 // Wide Timer 4 Sleep Mode Clock 2727 // Gating Control 2728 #define SYSCTL_SCGCWTIMER_S3 0x00000008 // Wide Timer 3 Sleep Mode Clock 2729 // Gating Control 2730 #define SYSCTL_SCGCWTIMER_S2 0x00000004 // Wide Timer 2 Sleep Mode Clock 2731 // Gating Control 2732 #define SYSCTL_SCGCWTIMER_S1 0x00000002 // Wide Timer 1 Sleep Mode Clock 2733 // Gating Control 2734 #define SYSCTL_SCGCWTIMER_S0 0x00000001 // Wide Timer 0 Sleep Mode Clock 2735 // Gating Control 2736 2737 //***************************************************************************** 2738 // 2739 // The following are defines for the bit fields in the SYSCTL_DCGCWD register. 2740 // 2741 //***************************************************************************** 2742 #define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode 2743 // Clock Gating Control 2744 #define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode 2745 // Clock Gating Control 2746 2747 //***************************************************************************** 2748 // 2749 // The following are defines for the bit fields in the SYSCTL_DCGCTIMER 2750 // register. 2751 // 2752 //***************************************************************************** 2753 #define SYSCTL_DCGCTIMER_D5 0x00000020 // Timer 5 Deep-Sleep Mode Clock 2754 // Gating Control 2755 #define SYSCTL_DCGCTIMER_D4 0x00000010 // Timer 4 Deep-Sleep Mode Clock 2756 // Gating Control 2757 #define SYSCTL_DCGCTIMER_D3 0x00000008 // Timer 3 Deep-Sleep Mode Clock 2758 // Gating Control 2759 #define SYSCTL_DCGCTIMER_D2 0x00000004 // Timer 2 Deep-Sleep Mode Clock 2760 // Gating Control 2761 #define SYSCTL_DCGCTIMER_D1 0x00000002 // Timer 1 Deep-Sleep Mode Clock 2762 // Gating Control 2763 #define SYSCTL_DCGCTIMER_D0 0x00000001 // Timer 0 Deep-Sleep Mode Clock 2764 // Gating Control 2765 2766 //***************************************************************************** 2767 // 2768 // The following are defines for the bit fields in the SYSCTL_DCGCGPIO 2769 // register. 2770 // 2771 //***************************************************************************** 2772 #define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode 2773 // Clock Gating Control 2774 #define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode 2775 // Clock Gating Control 2776 #define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode 2777 // Clock Gating Control 2778 #define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode 2779 // Clock Gating Control 2780 #define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode 2781 // Clock Gating Control 2782 #define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode 2783 // Clock Gating Control 2784 #define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode 2785 // Clock Gating Control 2786 #define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode 2787 // Clock Gating Control 2788 #define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode 2789 // Clock Gating Control 2790 #define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode 2791 // Clock Gating Control 2792 #define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode 2793 // Clock Gating Control 2794 #define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode 2795 // Clock Gating Control 2796 #define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode 2797 // Clock Gating Control 2798 #define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode 2799 // Clock Gating Control 2800 #define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode 2801 // Clock Gating Control 2802 2803 //***************************************************************************** 2804 // 2805 // The following are defines for the bit fields in the SYSCTL_DCGCDMA register. 2806 // 2807 //***************************************************************************** 2808 #define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode 2809 // Clock Gating Control 2810 2811 //***************************************************************************** 2812 // 2813 // The following are defines for the bit fields in the SYSCTL_DCGCHIB register. 2814 // 2815 //***************************************************************************** 2816 #define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep 2817 // Mode Clock Gating Control 2818 2819 //***************************************************************************** 2820 // 2821 // The following are defines for the bit fields in the SYSCTL_DCGCUART 2822 // register. 2823 // 2824 //***************************************************************************** 2825 #define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode 2826 // Clock Gating Control 2827 #define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode 2828 // Clock Gating Control 2829 #define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode 2830 // Clock Gating Control 2831 #define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode 2832 // Clock Gating Control 2833 #define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode 2834 // Clock Gating Control 2835 #define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode 2836 // Clock Gating Control 2837 #define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode 2838 // Clock Gating Control 2839 #define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode 2840 // Clock Gating Control 2841 2842 //***************************************************************************** 2843 // 2844 // The following are defines for the bit fields in the SYSCTL_DCGCSSI register. 2845 // 2846 //***************************************************************************** 2847 #define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode 2848 // Clock Gating Control 2849 #define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode 2850 // Clock Gating Control 2851 #define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode 2852 // Clock Gating Control 2853 #define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode 2854 // Clock Gating Control 2855 2856 //***************************************************************************** 2857 // 2858 // The following are defines for the bit fields in the SYSCTL_DCGCI2C register. 2859 // 2860 //***************************************************************************** 2861 #define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode 2862 // Clock Gating Control 2863 #define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode 2864 // Clock Gating Control 2865 #define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode 2866 // Clock Gating Control 2867 #define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode 2868 // Clock Gating Control 2869 #define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode 2870 // Clock Gating Control 2871 #define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode 2872 // Clock Gating Control 2873 2874 //***************************************************************************** 2875 // 2876 // The following are defines for the bit fields in the SYSCTL_DCGCUSB register. 2877 // 2878 //***************************************************************************** 2879 #define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock 2880 // Gating Control 2881 2882 //***************************************************************************** 2883 // 2884 // The following are defines for the bit fields in the SYSCTL_DCGCCAN register. 2885 // 2886 //***************************************************************************** 2887 #define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode 2888 // Clock Gating Control 2889 #define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode 2890 // Clock Gating Control 2891 2892 //***************************************************************************** 2893 // 2894 // The following are defines for the bit fields in the SYSCTL_DCGCADC register. 2895 // 2896 //***************************************************************************** 2897 #define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode 2898 // Clock Gating Control 2899 #define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode 2900 // Clock Gating Control 2901 2902 //***************************************************************************** 2903 // 2904 // The following are defines for the bit fields in the SYSCTL_DCGCACMP 2905 // register. 2906 // 2907 //***************************************************************************** 2908 #define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0 2909 // Deep-Sleep Mode Clock Gating 2910 // Control 2911 2912 //***************************************************************************** 2913 // 2914 // The following are defines for the bit fields in the SYSCTL_DCGCPWM register. 2915 // 2916 //***************************************************************************** 2917 #define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode 2918 // Clock Gating Control 2919 #define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode 2920 // Clock Gating Control 2921 2922 //***************************************************************************** 2923 // 2924 // The following are defines for the bit fields in the SYSCTL_DCGCQEI register. 2925 // 2926 //***************************************************************************** 2927 #define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode 2928 // Clock Gating Control 2929 #define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode 2930 // Clock Gating Control 2931 2932 //***************************************************************************** 2933 // 2934 // The following are defines for the bit fields in the SYSCTL_DCGCLPC register. 2935 // 2936 //***************************************************************************** 2937 #define SYSCTL_DCGCLPC_D0 0x00000001 // LPC Module Deep-Sleep Mode Clock 2938 // Gating Control 2939 2940 //***************************************************************************** 2941 // 2942 // The following are defines for the bit fields in the SYSCTL_DCGCPECI 2943 // register. 2944 // 2945 //***************************************************************************** 2946 #define SYSCTL_DCGCPECI_D0 0x00000001 // PECI Module Deep-Sleep Mode 2947 // Clock Gating Control 2948 2949 //***************************************************************************** 2950 // 2951 // The following are defines for the bit fields in the SYSCTL_DCGCFAN register. 2952 // 2953 //***************************************************************************** 2954 #define SYSCTL_DCGCFAN_D0 0x00000001 // FAN Module Deep-Sleep Mode Clock 2955 // Gating Control 2956 2957 //***************************************************************************** 2958 // 2959 // The following are defines for the bit fields in the SYSCTL_DCGCEEPROM 2960 // register. 2961 // 2962 //***************************************************************************** 2963 #define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode 2964 // Clock Gating Control 2965 2966 //***************************************************************************** 2967 // 2968 // The following are defines for the bit fields in the SYSCTL_DCGCWTIMER 2969 // register. 2970 // 2971 //***************************************************************************** 2972 #define SYSCTL_DCGCWTIMER_D5 0x00000020 // Wide Timer 5 Deep-Sleep Mode 2973 // Clock Gating Control 2974 #define SYSCTL_DCGCWTIMER_D4 0x00000010 // Wide Timer 4 Deep-Sleep Mode 2975 // Clock Gating Control 2976 #define SYSCTL_DCGCWTIMER_D3 0x00000008 // Wide Timer 3 Deep-Sleep Mode 2977 // Clock Gating Control 2978 #define SYSCTL_DCGCWTIMER_D2 0x00000004 // Wide Timer 2 Deep-Sleep Mode 2979 // Clock Gating Control 2980 #define SYSCTL_DCGCWTIMER_D1 0x00000002 // Wide Timer 1 Deep-Sleep Mode 2981 // Clock Gating Control 2982 #define SYSCTL_DCGCWTIMER_D0 0x00000001 // Wide Timer 0 Deep-Sleep Mode 2983 // Clock Gating Control 2984 2985 //***************************************************************************** 2986 // 2987 // The following are defines for the bit fields in the SYSCTL_PCWD register. 2988 // 2989 //***************************************************************************** 2990 #define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control 2991 #define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control 2992 2993 //***************************************************************************** 2994 // 2995 // The following are defines for the bit fields in the SYSCTL_PCTIMER register. 2996 // 2997 //***************************************************************************** 2998 #define SYSCTL_PCTIMER_P5 0x00000020 // Timer 5 Power Control 2999 #define SYSCTL_PCTIMER_P4 0x00000010 // Timer 4 Power Control 3000 #define SYSCTL_PCTIMER_P3 0x00000008 // Timer 3 Power Control 3001 #define SYSCTL_PCTIMER_P2 0x00000004 // Timer 2 Power Control 3002 #define SYSCTL_PCTIMER_P1 0x00000002 // Timer 1 Power Control 3003 #define SYSCTL_PCTIMER_P0 0x00000001 // Timer 0 Power Control 3004 3005 //***************************************************************************** 3006 // 3007 // The following are defines for the bit fields in the SYSCTL_PCGPIO register. 3008 // 3009 //***************************************************************************** 3010 #define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control 3011 #define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control 3012 #define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control 3013 #define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control 3014 #define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control 3015 #define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control 3016 #define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control 3017 #define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control 3018 #define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control 3019 #define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control 3020 #define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control 3021 #define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control 3022 #define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control 3023 #define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control 3024 #define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control 3025 3026 //***************************************************************************** 3027 // 3028 // The following are defines for the bit fields in the SYSCTL_PCDMA register. 3029 // 3030 //***************************************************************************** 3031 #define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control 3032 3033 //***************************************************************************** 3034 // 3035 // The following are defines for the bit fields in the SYSCTL_PCHIB register. 3036 // 3037 //***************************************************************************** 3038 #define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control 3039 3040 //***************************************************************************** 3041 // 3042 // The following are defines for the bit fields in the SYSCTL_PCUART register. 3043 // 3044 //***************************************************************************** 3045 #define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control 3046 #define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control 3047 #define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control 3048 #define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control 3049 #define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control 3050 #define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control 3051 #define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control 3052 #define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control 3053 3054 //***************************************************************************** 3055 // 3056 // The following are defines for the bit fields in the SYSCTL_PCSSI register. 3057 // 3058 //***************************************************************************** 3059 #define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control 3060 #define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control 3061 #define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control 3062 #define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control 3063 3064 //***************************************************************************** 3065 // 3066 // The following are defines for the bit fields in the SYSCTL_PCI2C register. 3067 // 3068 //***************************************************************************** 3069 #define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control 3070 #define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control 3071 #define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control 3072 #define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control 3073 #define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control 3074 #define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control 3075 3076 //***************************************************************************** 3077 // 3078 // The following are defines for the bit fields in the SYSCTL_PCUSB register. 3079 // 3080 //***************************************************************************** 3081 #define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control 3082 3083 //***************************************************************************** 3084 // 3085 // The following are defines for the bit fields in the SYSCTL_PCCAN register. 3086 // 3087 //***************************************************************************** 3088 #define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control 3089 #define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control 3090 3091 //***************************************************************************** 3092 // 3093 // The following are defines for the bit fields in the SYSCTL_PCADC register. 3094 // 3095 //***************************************************************************** 3096 #define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control 3097 #define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control 3098 3099 //***************************************************************************** 3100 // 3101 // The following are defines for the bit fields in the SYSCTL_PCACMP register. 3102 // 3103 //***************************************************************************** 3104 #define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power 3105 // Control 3106 3107 //***************************************************************************** 3108 // 3109 // The following are defines for the bit fields in the SYSCTL_PCPWM register. 3110 // 3111 //***************************************************************************** 3112 #define SYSCTL_PCPWM_P1 0x00000002 // PWM Module 1 Power Control 3113 #define SYSCTL_PCPWM_P0 0x00000001 // PWM Module 0 Power Control 3114 3115 //***************************************************************************** 3116 // 3117 // The following are defines for the bit fields in the SYSCTL_PCQEI register. 3118 // 3119 //***************************************************************************** 3120 #define SYSCTL_PCQEI_P1 0x00000002 // QEI Module 1 Power Control 3121 #define SYSCTL_PCQEI_P0 0x00000001 // QEI Module 0 Power Control 3122 3123 //***************************************************************************** 3124 // 3125 // The following are defines for the bit fields in the SYSCTL_PCLPC register. 3126 // 3127 //***************************************************************************** 3128 #define SYSCTL_PCLPC_P0 0x00000001 // LPC Module Power Control 3129 3130 //***************************************************************************** 3131 // 3132 // The following are defines for the bit fields in the SYSCTL_PCPECI register. 3133 // 3134 //***************************************************************************** 3135 #define SYSCTL_PCPECI_P0 0x00000001 // PECI Module Power Control 3136 3137 //***************************************************************************** 3138 // 3139 // The following are defines for the bit fields in the SYSCTL_PCFAN register. 3140 // 3141 //***************************************************************************** 3142 #define SYSCTL_PCFAN_P0 0x00000001 // FAN Module Power Control 3143 3144 //***************************************************************************** 3145 // 3146 // The following are defines for the bit fields in the SYSCTL_PCEEPROM 3147 // register. 3148 // 3149 //***************************************************************************** 3150 #define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module Power Control 3151 3152 //***************************************************************************** 3153 // 3154 // The following are defines for the bit fields in the SYSCTL_PCWTIMER 3155 // register. 3156 // 3157 //***************************************************************************** 3158 #define SYSCTL_PCWTIMER_P5 0x00000020 // Wide Timer 5 Power Control 3159 #define SYSCTL_PCWTIMER_P4 0x00000010 // Wide Timer 4 Power Control 3160 #define SYSCTL_PCWTIMER_P3 0x00000008 // Wide Timer 3 Power Control 3161 #define SYSCTL_PCWTIMER_P2 0x00000004 // Wide Timer 2 Power Control 3162 #define SYSCTL_PCWTIMER_P1 0x00000002 // Wide Timer 1 Power Control 3163 #define SYSCTL_PCWTIMER_P0 0x00000001 // Wide Timer 0 Power Control 3164 3165 //***************************************************************************** 3166 // 3167 // The following are defines for the bit fields in the SYSCTL_PRWD register. 3168 // 3169 //***************************************************************************** 3170 #define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral 3171 // Ready 3172 #define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral 3173 // Ready 3174 3175 //***************************************************************************** 3176 // 3177 // The following are defines for the bit fields in the SYSCTL_PRTIMER register. 3178 // 3179 //***************************************************************************** 3180 #define SYSCTL_PRTIMER_R5 0x00000020 // Timer 5 Peripheral Ready 3181 #define SYSCTL_PRTIMER_R4 0x00000010 // Timer 4 Peripheral Ready 3182 #define SYSCTL_PRTIMER_R3 0x00000008 // Timer 3 Peripheral Ready 3183 #define SYSCTL_PRTIMER_R2 0x00000004 // Timer 2 Peripheral Ready 3184 #define SYSCTL_PRTIMER_R1 0x00000002 // Timer 1 Peripheral Ready 3185 #define SYSCTL_PRTIMER_R0 0x00000001 // Timer 0 Peripheral Ready 3186 3187 //***************************************************************************** 3188 // 3189 // The following are defines for the bit fields in the SYSCTL_PRGPIO register. 3190 // 3191 //***************************************************************************** 3192 #define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready 3193 #define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready 3194 #define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready 3195 #define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready 3196 #define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready 3197 #define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready 3198 #define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready 3199 #define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready 3200 #define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready 3201 #define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready 3202 #define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready 3203 #define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready 3204 #define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready 3205 #define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready 3206 #define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready 3207 3208 //***************************************************************************** 3209 // 3210 // The following are defines for the bit fields in the SYSCTL_PRDMA register. 3211 // 3212 //***************************************************************************** 3213 #define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready 3214 3215 //***************************************************************************** 3216 // 3217 // The following are defines for the bit fields in the SYSCTL_PRHIB register. 3218 // 3219 //***************************************************************************** 3220 #define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral 3221 // Ready 3222 3223 //***************************************************************************** 3224 // 3225 // The following are defines for the bit fields in the SYSCTL_PRUART register. 3226 // 3227 //***************************************************************************** 3228 #define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready 3229 #define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready 3230 #define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready 3231 #define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready 3232 #define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready 3233 #define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready 3234 #define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready 3235 #define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready 3236 3237 //***************************************************************************** 3238 // 3239 // The following are defines for the bit fields in the SYSCTL_PRSSI register. 3240 // 3241 //***************************************************************************** 3242 #define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready 3243 #define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready 3244 #define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready 3245 #define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready 3246 3247 //***************************************************************************** 3248 // 3249 // The following are defines for the bit fields in the SYSCTL_PRI2C register. 3250 // 3251 //***************************************************************************** 3252 #define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready 3253 #define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready 3254 #define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready 3255 #define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready 3256 #define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready 3257 #define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready 3258 3259 //***************************************************************************** 3260 // 3261 // The following are defines for the bit fields in the SYSCTL_PRUSB register. 3262 // 3263 //***************************************************************************** 3264 #define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready 3265 3266 //***************************************************************************** 3267 // 3268 // The following are defines for the bit fields in the SYSCTL_PRCAN register. 3269 // 3270 //***************************************************************************** 3271 #define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready 3272 #define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready 3273 3274 //***************************************************************************** 3275 // 3276 // The following are defines for the bit fields in the SYSCTL_PRADC register. 3277 // 3278 //***************************************************************************** 3279 #define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready 3280 #define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready 3281 3282 //***************************************************************************** 3283 // 3284 // The following are defines for the bit fields in the SYSCTL_PRACMP register. 3285 // 3286 //***************************************************************************** 3287 #define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0 3288 // Peripheral Ready 3289 3290 //***************************************************************************** 3291 // 3292 // The following are defines for the bit fields in the SYSCTL_PRPWM register. 3293 // 3294 //***************************************************************************** 3295 #define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready 3296 #define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready 3297 3298 //***************************************************************************** 3299 // 3300 // The following are defines for the bit fields in the SYSCTL_PRQEI register. 3301 // 3302 //***************************************************************************** 3303 #define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready 3304 #define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready 3305 3306 //***************************************************************************** 3307 // 3308 // The following are defines for the bit fields in the SYSCTL_PRLPC register. 3309 // 3310 //***************************************************************************** 3311 #define SYSCTL_PRLPC_R0 0x00000001 // LPC Module Peripheral Ready 3312 3313 //***************************************************************************** 3314 // 3315 // The following are defines for the bit fields in the SYSCTL_PRPECI register. 3316 // 3317 //***************************************************************************** 3318 #define SYSCTL_PRPECI_R0 0x00000001 // PECI Module Peripheral Ready 3319 3320 //***************************************************************************** 3321 // 3322 // The following are defines for the bit fields in the SYSCTL_PRFAN register. 3323 // 3324 //***************************************************************************** 3325 #define SYSCTL_PRFAN_R0 0x00000001 // FAN Module Peripheral Ready 3326 3327 //***************************************************************************** 3328 // 3329 // The following are defines for the bit fields in the SYSCTL_PREEPROM 3330 // register. 3331 // 3332 //***************************************************************************** 3333 #define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready 3334 3335 //***************************************************************************** 3336 // 3337 // The following are defines for the bit fields in the SYSCTL_PRWTIMER 3338 // register. 3339 // 3340 //***************************************************************************** 3341 #define SYSCTL_PRWTIMER_R5 0x00000020 // Wide Timer 5 Peripheral Ready 3342 #define SYSCTL_PRWTIMER_R4 0x00000010 // Wide Timer 4 Peripheral Ready 3343 #define SYSCTL_PRWTIMER_R3 0x00000008 // Wide Timer 3 Peripheral Ready 3344 #define SYSCTL_PRWTIMER_R2 0x00000004 // Wide Timer 2 Peripheral Ready 3345 #define SYSCTL_PRWTIMER_R1 0x00000002 // Wide Timer 1 Peripheral Ready 3346 #define SYSCTL_PRWTIMER_R0 0x00000001 // Wide Timer 0 Peripheral Ready 3347 3348 //***************************************************************************** 3349 // 3350 // The following definitions are deprecated. 3351 // 3352 //***************************************************************************** 3353 #ifndef DEPRECATED 3354 3355 //***************************************************************************** 3356 // 3357 // The following are deprecated defines for the System Control register 3358 // addresses. 3359 // 3360 //***************************************************************************** 3361 #define SYSCTL_GPIOHSCTL 0x400FE06C // GPIO High-Speed Control 3362 #define SYSCTL_USER0 0x400FE1E0 // NV User Register 0 3363 #define SYSCTL_USER1 0x400FE1E4 // NV User Register 1 3364 3365 //***************************************************************************** 3366 // 3367 // The following are deprecated defines for the bit fields in the SYSCTL_DID0 3368 // register. 3369 // 3370 //***************************************************************************** 3371 #define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask 3372 #define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class 3373 #define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask 3374 #define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A 3375 #define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B 3376 #define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C 3377 #define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask 3378 3379 //***************************************************************************** 3380 // 3381 // The following are deprecated defines for the bit fields in the SYSCTL_DID1 3382 // register. 3383 // 3384 //***************************************************************************** 3385 #define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask 3386 #define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask 3387 #define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family 3388 #define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask 3389 #define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count 3390 #define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask 3391 #define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask 3392 #define SYSCTL_DID1_PKG_48QFP 0x00000008 // QFP package 3393 #define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask 3394 #define SYSCTL_DID1_PKG_28SOIC 0x00000000 // SOIC package 3395 #define SYSCTL_DID1_PRTNO_SHIFT 16 3396 3397 //***************************************************************************** 3398 // 3399 // The following are deprecated defines for the bit fields in the SYSCTL_DC0 3400 // register. 3401 // 3402 //***************************************************************************** 3403 #define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask 3404 #define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask 3405 3406 //***************************************************************************** 3407 // 3408 // The following are deprecated defines for the bit fields in the SYSCTL_DC1 3409 // register. 3410 // 3411 //***************************************************************************** 3412 #define SYSCTL_DC1_PWM 0x00100000 // PWM Module Present 3413 #define SYSCTL_DC1_ADC 0x00010000 // ADC Module Present 3414 #define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask 3415 #define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask 3416 #define SYSCTL_DC1_ADCSPD_M 0x00000F00 // Max ADC Speed 3417 #define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC 3418 #define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250K samples/second 3419 #define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500K samples/second 3420 #define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1M samples/second 3421 #define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present 3422 #define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present 3423 3424 //***************************************************************************** 3425 // 3426 // The following are deprecated defines for the bit fields in the SYSCTL_DC2 3427 // register. 3428 // 3429 //***************************************************************************** 3430 #define SYSCTL_DC2_I2C 0x00001000 // I2C present 3431 #define SYSCTL_DC2_QEI 0x00000100 // QEI present 3432 #define SYSCTL_DC2_SSI 0x00000010 // SSI present 3433 3434 //***************************************************************************** 3435 // 3436 // The following are deprecated defines for the bit fields in the SYSCTL_DC3 3437 // register. 3438 // 3439 //***************************************************************************** 3440 #define SYSCTL_DC3_ADC7 0x00800000 // ADC7 Pin Present 3441 #define SYSCTL_DC3_ADC6 0x00400000 // ADC6 Pin Present 3442 #define SYSCTL_DC3_ADC5 0x00200000 // ADC5 Pin Present 3443 #define SYSCTL_DC3_ADC4 0x00100000 // ADC4 Pin Present 3444 #define SYSCTL_DC3_ADC3 0x00080000 // ADC3 Pin Present 3445 #define SYSCTL_DC3_ADC2 0x00040000 // ADC2 Pin Present 3446 #define SYSCTL_DC3_ADC1 0x00020000 // ADC1 Pin Present 3447 #define SYSCTL_DC3_ADC0 0x00010000 // ADC0 Pin Present 3448 #define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present 3449 3450 //***************************************************************************** 3451 // 3452 // The following are deprecated defines for the bit fields in the 3453 // SYSCTL_PBORCTL register. 3454 // 3455 //***************************************************************************** 3456 #define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer 3457 #define SYSCTL_PBORCTL_BOR_SH 2 3458 3459 //***************************************************************************** 3460 // 3461 // The following are deprecated defines for the bit fields in the 3462 // SYSCTL_LDOPCTL register. 3463 // 3464 //***************************************************************************** 3465 #define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask 3466 3467 //***************************************************************************** 3468 // 3469 // The following are deprecated defines for the bit fields in the SYSCTL_SRCR0 3470 // register. 3471 // 3472 //***************************************************************************** 3473 #define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control 3474 #define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control 3475 #define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control 3476 3477 //***************************************************************************** 3478 // 3479 // The following are deprecated defines for the bit fields in the SYSCTL_RESC 3480 // register. 3481 // 3482 //***************************************************************************** 3483 #define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset 3484 #define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset 3485 3486 //***************************************************************************** 3487 // 3488 // The following are deprecated defines for the bit fields in the SYSCTL_RCC 3489 // register. 3490 // 3491 //***************************************************************************** 3492 #define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider 3493 #define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider 3494 #define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider 3495 #define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider 3496 #define SYSCTL_RCC_OE 0x00001000 // PLL output enable 3497 #define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864 MHz crystal 3498 #define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4 MHz crystal 3499 #define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc 3500 #define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select 3501 #define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field 3502 #define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field 3503 #define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field 3504 #define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field 3505 3506 //***************************************************************************** 3507 // 3508 // The following are deprecated defines for the bit fields in the SYSCTL_PLLCFG 3509 // register. 3510 // 3511 //***************************************************************************** 3512 #define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider 3513 #define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier 3514 #define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider 3515 #define SYSCTL_PLLCFG_F_SHIFT 5 3516 #define SYSCTL_PLLCFG_R_SHIFT 0 3517 3518 //***************************************************************************** 3519 // 3520 // The following are deprecated defines for the bit fields in the 3521 // SYSCTL_GPIOHSCTL register. 3522 // 3523 //***************************************************************************** 3524 #define SYSCTL_GPIOHSCTL_PORTA 0x00000001 // Port A High-Speed 3525 #define SYSCTL_GPIOHSCTL_PORTB 0x00000002 // Port B High-Speed 3526 #define SYSCTL_GPIOHSCTL_PORTC 0x00000004 // Port C High-Speed 3527 #define SYSCTL_GPIOHSCTL_PORTD 0x00000008 // Port D High-Speed 3528 #define SYSCTL_GPIOHSCTL_PORTE 0x00000010 // Port E High-Speed 3529 #define SYSCTL_GPIOHSCTL_PORTF 0x00000020 // Port F High-Speed 3530 #define SYSCTL_GPIOHSCTL_PORTG 0x00000040 // Port G High-Speed 3531 #define SYSCTL_GPIOHSCTL_PORTH 0x00000080 // Port H High-Speed 3532 3533 //***************************************************************************** 3534 // 3535 // The following are deprecated defines for the bit fields in the SYSCTL_RCC2 3536 // register. 3537 // 3538 //***************************************************************************** 3539 #define SYSCTL_RCC2_USEFRACT 0x40000000 // Use fractional divider 3540 #define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider 3541 #define SYSCTL_RCC2_FRACT 0x00400000 // Fractional divide 3542 #define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select 3543 3544 //***************************************************************************** 3545 // 3546 // The following are deprecated defines for the bit fields in the SYSCTL_RCGC0 3547 // register. 3548 // 3549 //***************************************************************************** 3550 #define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control 3551 #define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control 3552 #define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control 3553 3554 //***************************************************************************** 3555 // 3556 // The following are deprecated defines for the bit fields in the SYSCTL_SCGC0 3557 // register. 3558 // 3559 //***************************************************************************** 3560 #define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control 3561 #define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control 3562 #define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control 3563 3564 //***************************************************************************** 3565 // 3566 // The following are deprecated defines for the bit fields in the SYSCTL_DCGC0 3567 // register. 3568 // 3569 //***************************************************************************** 3570 #define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control 3571 #define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control 3572 #define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control 3573 3574 //***************************************************************************** 3575 // 3576 // The following are deprecated defines for the bit fields in the 3577 // SYSCTL_DSLPCLKCFG register. 3578 // 3579 //***************************************************************************** 3580 #define SYSCTL_DSLPCLKCFG_D_MSK 0x1F800000 // Deep sleep system clock override 3581 #define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override 3582 3583 //***************************************************************************** 3584 // 3585 // The following are deprecated defines for the bit fields in the 3586 // SYSCTL_CLKVCLR register. 3587 // 3588 //***************************************************************************** 3589 #define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault 3590 3591 //***************************************************************************** 3592 // 3593 // The following are deprecated defines for the bit fields in the 3594 // SYSCTL_LDOARST register. 3595 // 3596 //***************************************************************************** 3597 #define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device 3598 3599 //***************************************************************************** 3600 // 3601 // The following are deprecated defines for the bit fields in the SYSCTL_SRCR0, 3602 // SYSCTL_RCGC0, SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. 3603 // 3604 //***************************************************************************** 3605 #define SYSCTL_SET0_CAN2 0x04000000 // CAN 2 module 3606 #define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module 3607 #define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module 3608 #define SYSCTL_SET0_PWM 0x00100000 // PWM module 3609 #define SYSCTL_SET0_ADC 0x00010000 // ADC module 3610 #define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask 3611 #define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC 3612 #define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC 3613 #define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC 3614 #define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC 3615 #define SYSCTL_SET0_HIB 0x00000040 // Hibernation module 3616 #define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module 3617 3618 //***************************************************************************** 3619 // 3620 // The following are deprecated defines for the bit fields in the SYSCTL_SRCR1, 3621 // SYSCTL_RCGC1, SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. 3622 // 3623 //***************************************************************************** 3624 #define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 3625 #define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 3626 #define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 3627 #define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3 3628 #define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 3629 #define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 3630 #define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 3631 #define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1 3632 #define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0 3633 #define SYSCTL_SET1_I2C 0x00001000 // I2C module 3634 #define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1 3635 #define SYSCTL_SET1_QEI 0x00000100 // QEI module 3636 #define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0 3637 #define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1 3638 #define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0 3639 #define SYSCTL_SET1_SSI 0x00000010 // SSI module 3640 #define SYSCTL_SET1_UART2 0x00000004 // UART module 2 3641 #define SYSCTL_SET1_UART1 0x00000002 // UART module 1 3642 #define SYSCTL_SET1_UART0 0x00000001 // UART module 0 3643 3644 //***************************************************************************** 3645 // 3646 // The following are deprecated defines for the bit fields in the SYSCTL_SRCR2, 3647 // SYSCTL_RCGC2, SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. 3648 // 3649 //***************************************************************************** 3650 #define SYSCTL_SET2_ETH 0x50000000 // ETH module 3651 #define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module 3652 #define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module 3653 #define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module 3654 #define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module 3655 #define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module 3656 #define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module 3657 #define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module 3658 #define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module 3659 3660 //***************************************************************************** 3661 // 3662 // The following are deprecated defines for the bit fields in the SYSCTL_RIS, 3663 // SYSCTL_IMC, and SYSCTL_IMS registers. 3664 // 3665 //***************************************************************************** 3666 #define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt 3667 #define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt 3668 #define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int 3669 #define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int 3670 #define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt 3671 #define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt 3672 #define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt 3673 3674 #endif 3675 3676 #endif // __HW_SYSCTL_H__ 3677