1 /*
2 * @brief LPC15XX System Control registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2014
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __SYSCTL_15XX_H_
33 #define __SYSCTL_15XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /** @defgroup SYSCTL_15XX CHIP: LPC15xx System Control block driver
40 * @ingroup CHIP_15XX_Drivers
41 * @{
42 */
43
44 /**
45 * @brief LPC15XX System Control block structure
46 */
47 typedef struct { /*!< SYSCTL Structure */
48 __IO uint32_t SYSMEMREMAP; /*!< System Memory remap register */
49 __I uint32_t RESERVED0[2];
50 __IO uint32_t AHBBUFEN0;
51 __IO uint32_t AHBBUFEN1;
52 __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration register */
53 __I uint32_t RESERVED1[1];
54 __IO uint32_t NMISRC; /*!< NMI source control register */
55 __I uint32_t RESERVED2[8];
56 __IO uint32_t SYSRSTSTAT; /*!< System Reset Status register */
57 __IO uint32_t PRESETCTRL[2]; /*!< Peripheral reset Control registers */
58 __I uint32_t PIOPORCAP[3]; /*!< POR captured PIO status registers */
59 __I uint32_t RESERVED3[10];
60 __IO uint32_t MAINCLKSELA; /*!< Main clock source A select register */
61 __IO uint32_t MAINCLKSELB; /*!< Main clock source B select register */
62 __IO uint32_t USBCLKSEL; /*!< USB clock source select register */
63 __IO uint32_t ADCASYNCCLKSEL; /*!< ADC asynchronous clock source select register */
64 __I uint32_t RESERVED4[1];
65 __IO uint32_t CLKOUTSEL[2]; /*!< Clock out source select registers */
66 __I uint32_t RESERVED5[1];
67 __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select register */
68 __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select register */
69 __IO uint32_t SCTPLLCLKSEL; /*!< SCT PLL clock source select register */
70 __I uint32_t RESERVED6[5];
71 __IO uint32_t SYSAHBCLKDIV; /*!< System Clock divider register */
72 __IO uint32_t SYSAHBCLKCTRL[2];/*!< System clock control registers */
73 __IO uint32_t SYSTICKCLKDIV; /*!< SYSTICK clock divider */
74 __IO uint32_t UARTCLKDIV; /*!< UART clock divider register */
75 __IO uint32_t IOCONCLKDIV; /*!< programmable glitch filter divider registers for IOCON */
76 __IO uint32_t TRACECLKDIV; /*!< ARM trace clock divider register */
77 __I uint32_t RESERVED7[4];
78 __IO uint32_t USBCLKDIV; /*!< USB clock source divider register */
79 __IO uint32_t ADCASYNCCLKDIV; /*!< Asynchronous ADC clock divider */
80 __I uint32_t RESERVED8[1];
81 __IO uint32_t CLKOUTDIV; /*!< Clock out divider register */
82 __I uint32_t RESERVED9[9];
83 __IO uint32_t FREQMECTRL; /*!< Frequency measure register */
84 __IO uint32_t FLASHCFG; /*!< Flash configuration register */
85 __IO uint32_t FRGCTRL; /*!< USART fractional baud rate generator control register */
86 __IO uint32_t USBCLKCTRL; /*!< USB clock control register */
87 __I uint32_t USBCLKST; /*!< USB clock status register */
88 __I uint32_t RESERVED10[19];
89 __IO uint32_t BODCTRL; /*!< Brown Out Detect register */
90 __I uint32_t IRCCTRL;
91 __IO uint32_t SYSOSCCTRL; /*!< System Oscillator control register */
92 __I uint32_t RESERVED11[1];
93 __IO uint32_t RTCOSCCTRL; /*!< RTC Oscillator control register */
94 __I uint32_t RESERVED12[1];
95 __IO uint32_t SYSPLLCTRL; /*!< System PLL control register */
96 __I uint32_t SYSPLLSTAT; /*!< System PLL status register */
97 __IO uint32_t USBPLLCTRL; /*!< USB PLL control register */
98 __I uint32_t USBPLLSTAT; /*!< USB PLL status register */
99 __IO uint32_t SCTPLLCTRL; /*!< SCT PLL control register */
100 __I uint32_t SCTPLLSTAT; /*!< SCT PLL status register */
101 __I uint32_t RESERVED13[21];
102 __IO uint32_t PDWAKECFG; /*!< Power down states in wake up from deep sleep register */
103 __IO uint32_t PDRUNCFG; /*!< Power configuration register*/
104 __I uint32_t RESERVED14[3];
105 __IO uint32_t STARTERP[2]; /*!< Start logic interrupt wake-up enable registers */
106 __I uint32_t RESERVED15[117];
107 __I uint32_t JTAG_IDCODE; /*!< JTAG ID code register */
108 __I uint32_t DEVICEID[2]; /*!< Device ID registers */
109 } LPC_SYSCTL_T;
110
111 /**
112 * System memory remap modes used to remap interrupt vectors
113 */
114 typedef enum CHIP_SYSCTL_BOOT_MODE_REMAP {
115 REMAP_BOOT_LOADER_MODE = 0, /*!< Interrupt vectors are re-mapped to Boot ROM */
116 REMAP_USER_RAM_MODE, /*!< Interrupt vectors are re-mapped to Static RAM */
117 REMAP_USER_FLASH_MODE /*!< Interrupt vectors are not re-mapped and reside in Flash */
118 } CHIP_SYSCTL_BOOT_MODE_REMAP_T;
119
120 /**
121 * @brief Re-map interrupt vectors
122 * @param remap : system memory map value
123 * @return Nothing
124 */
Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap)125 STATIC INLINE void Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap)
126 {
127 LPC_SYSCTL->SYSMEMREMAP = (uint32_t) remap;
128 }
129
130 /**
131 * Peripheral reset identifiers, not available on all devices
132 */
133 typedef enum {
134 /* PRESETCTRL0 resets */
135 RESET_FLASH = 7, /*!< FLASH controller reset control */
136 RESET_EEPROM = 9, /*!< EEPROM controller reset control */
137 RESET_MUX = 11, /*!< Input mux reset control */
138 RESET_IOCON = 13, /*!< IOCON reset control */
139 RESET_PININT = 18, /*!< Pin interrupt (PINT) reset reset control */
140 RESET_GINT, /*!< Grouped interrupt (GINT) reset control */
141 RESET_DMA, /*!< DMA reset control */
142 RESET_CRC, /*!< CRC reset control */
143 RESET_ADC0 = 27, /*!< ADC0 reset control */
144 RESET_ADC1, /*!< ADC1 reset control */
145 RESET_ACMP = 30, /*!< Analog Comparator (all 4 ACMP) reset control */
146 RESET_MRT = 32 + 0, /*!< Multi-rate timer (MRT) reset control */
147 RESET_RIT, /*!< Repetitive interrupt timer (RIT) reset control */
148 RESET_SCT0, /*!< State configurable timer 0 (SCT0) reset control */
149 RESET_SCT1, /*!< State configurable timer 1 (SCT1) reset control */
150 RESET_SCT2, /*!< State configurable timer 2 (SCT2) reset control */
151 RESET_SCT3, /*!< State configurable timer 3 (SCT3) reset control */
152 RESET_SCTIPU, /*!< State configurable timer IPU (SCTIPU) reset control */
153 RESET_CAN, /*!< CAN reset control */
154 RESET_SPI0 = 32 + 9, /*!< SPI0 reset control */
155 RESET_SPI1, /*!< SPI1 reset control */
156 RESET_I2C0 = 32 + 13, /*!< I2C0 reset control */
157 RESET_UART0 = 32 + 17, /*!< UART0 reset control */
158 RESET_UART1, /*!< UART1 reset control */
159 RESET_UART2, /*!< UART2 reset control */
160 RESET_QEI0 = 32 + 21, /*!< QEI0 reset control */
161 RESET_USB = 32 + 23 /*!< USB reset control */
162 } CHIP_SYSCTL_PERIPH_RESET_T;
163
164 /**
165 * @brief Assert reset for a peripheral
166 * @param periph : Peripheral to assert reset for
167 * @return Nothing
168 * @note The peripheral will stay in reset until reset is de-asserted. Call
169 * Chip_SYSCTL_DeassertPeriphReset() to de-assert the reset.
170 */
171 void Chip_SYSCTL_AssertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph);
172
173 /**
174 * @brief De-assert reset for a peripheral
175 * @param periph : Peripheral to de-assert reset for
176 * @return Nothing
177 */
178 void Chip_SYSCTL_DeassertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph);
179
180 /**
181 * @brief Resets a peripheral
182 * @param periph : Peripheral to reset
183 * @return Nothing
184 */
Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)185 STATIC INLINE void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
186 {
187 Chip_SYSCTL_AssertPeriphReset(periph);
188 Chip_SYSCTL_DeassertPeriphReset(periph);
189 }
190
191 /**
192 * System reset status
193 */
194 #define SYSCTL_RST_POR (1 << 0) /*!< POR reset status */
195 #define SYSCTL_RST_EXTRST (1 << 1) /*!< External reset status */
196 #define SYSCTL_RST_WDT (1 << 2) /*!< Watchdog reset status */
197 #define SYSCTL_RST_BOD (1 << 3) /*!< Brown-out detect reset status */
198 #define SYSCTL_RST_SYSRST (1 << 4) /*!< software system reset status */
199
200 /**
201 * @brief Get system reset status
202 * @return An Or'ed value of SYSCTL_RST_*
203 * @note This function returns the detected reset source(s). Mask with an
204 * SYSCTL_RST_* value to determine if a reset has occurred.
205 */
Chip_SYSCTL_GetSystemRSTStatus(void)206 STATIC INLINE uint32_t Chip_SYSCTL_GetSystemRSTStatus(void)
207 {
208 return LPC_SYSCTL->SYSRSTSTAT;
209 }
210
211 /**
212 * @brief Clear system reset status
213 * @param reset : An Or'ed value of SYSCTL_RST_* statuses to clear
214 * @return Nothing
215 */
Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset)216 STATIC INLINE void Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset)
217 {
218 LPC_SYSCTL->SYSRSTSTAT = reset;
219 }
220
221 /**
222 * @brief Read POR captured PIO status at reset
223 * @param index : POR register index 0, 1, or 2
224 * @return captured POR PIO status for ports 0, 1, or 2
225 */
Chip_SYSCTL_GetPORPIOStatus(int index)226 STATIC INLINE uint32_t Chip_SYSCTL_GetPORPIOStatus(int index)
227 {
228 return LPC_SYSCTL->PIOPORCAP[index];
229 }
230
231 /**
232 * Brown-out detector reset level
233 */
234 typedef enum CHIP_SYSCTL_BODRSTLVL {
235 SYSCTL_BODRSTLVL_RESERVED0,
236 SYSCTL_BODRSTLVL_RESERVED1,
237 SYSCTL_BODRSTLVL_2_34V, /*!< Brown-out reset at 2.34v */
238 SYSCTL_BODRSTLVL_2_64V, /*!< Brown-out reset at 2.64v */
239 } CHIP_SYSCTL_BODRSTLVL_T;
240
241 /**
242 * Brown-out detector interrupt level
243 */
244 typedef enum CHIP_SYSCTL_BODRINTVAL {
245 SYSCTL_BODINTVAL_RESERVED0,
246 SYSCTL_BODINTVAL_RESERVED1,
247 SYSCTL_BODINTVAL_2_55V, /*!< Brown-out interrupt at 2.55v */
248 SYSCTL_BODINTVAL_2_83V, /*!< Brown-out interrupt at 2.83v */
249 } CHIP_SYSCTL_BODRINTVAL_T;
250
251 /**
252 * @brief Set brown-out detection interrupt and reset levels
253 * @param rstlvl : Brown-out detector reset level
254 * @param intlvl : Brown-out interrupt level
255 * @return Nothing
256 * @note Brown-out detection reset will be disabled upon exiting this function.
257 * Use Chip_SYSCTL_EnableBODReset() to re-enable.
258 */
Chip_SYSCTL_SetBODLevels(CHIP_SYSCTL_BODRSTLVL_T rstlvl,CHIP_SYSCTL_BODRINTVAL_T intlvl)259 STATIC INLINE void Chip_SYSCTL_SetBODLevels(CHIP_SYSCTL_BODRSTLVL_T rstlvl,
260 CHIP_SYSCTL_BODRINTVAL_T intlvl)
261 {
262 LPC_SYSCTL->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2);
263 }
264
265 /**
266 * @brief Enable brown-out detection reset
267 * @return Nothing
268 */
Chip_SYSCTL_EnableBODReset(void)269 STATIC INLINE void Chip_SYSCTL_EnableBODReset(void)
270 {
271 LPC_SYSCTL->BODCTRL |= (1 << 4);
272 }
273
274 /**
275 * @brief Disable brown-out detection reset
276 * @return Nothing
277 */
Chip_SYSCTL_DisableBODReset(void)278 STATIC INLINE void Chip_SYSCTL_DisableBODReset(void)
279 {
280 LPC_SYSCTL->BODCTRL &= ~(1 << 4);
281 }
282
283 /**
284 * @brief Set System tick timer calibration value
285 * @param sysCalVal : System tick timer calibration value
286 * @return Nothing
287 */
Chip_SYSCTL_SetSYSTCKCAL(uint32_t sysCalVal)288 STATIC INLINE void Chip_SYSCTL_SetSYSTCKCAL(uint32_t sysCalVal)
289 {
290 LPC_SYSCTL->SYSTCKCAL = sysCalVal;
291 }
292
293 /**
294 * Non-Maskable Interrupt Enable/Disable value
295 */
296 #define SYSCTL_NMISRC_ENABLE (1UL << 31) /*!< Enable the Non-Maskable Interrupt (NMI) source */
297
298 /**
299 * @brief Set source for non-maskable interrupt (NMI)
300 * @param intsrc : IRQ number to assign to the NMI
301 * @return Nothing
302 * @note The NMI source will be disabled upon exiting this function. Use the
303 * Chip_SYSCTL_EnableNMISource() function to enable the NMI source.
304 */
Chip_SYSCTL_SetNMISource(uint32_t intsrc)305 STATIC INLINE void Chip_SYSCTL_SetNMISource(uint32_t intsrc)
306 {
307 LPC_SYSCTL->NMISRC = 0; /* Disable first */
308 LPC_SYSCTL->NMISRC = intsrc;
309 }
310
311 /**
312 * @brief Enable interrupt used for NMI source
313 * @return Nothing
314 */
Chip_SYSCTL_EnableNMISource(void)315 STATIC INLINE void Chip_SYSCTL_EnableNMISource(void)
316 {
317 LPC_SYSCTL->NMISRC |= SYSCTL_NMISRC_ENABLE;
318 }
319
320 /**
321 * @brief Disable interrupt used for NMI source
322 * @return Nothing
323 */
Chip_SYSCTL_DisableNMISource(void)324 STATIC INLINE void Chip_SYSCTL_DisableNMISource(void)
325 {
326 LPC_SYSCTL->NMISRC &= ~(SYSCTL_NMISRC_ENABLE);
327 }
328
329 /**
330 * @brief Starts a frequency measurement cycle
331 * @return Nothing
332 * @note This function is meant to be used with the Chip_INMUX_SetFreqMeasRefClock()
333 * and Chip_INMUX_SetFreqMeasTargClock() functions.
334 */
Chip_SYSCTL_StartFreqMeas(void)335 STATIC INLINE void Chip_SYSCTL_StartFreqMeas(void)
336 {
337 LPC_SYSCTL->FREQMECTRL = 0;
338 LPC_SYSCTL->FREQMECTRL = (1UL << 31);
339 }
340
341 /**
342 * @brief Indicates when a frequency measurement cycle is complete
343 * @return true if a measurement cycle is active, otherwise false
344 */
Chip_SYSCTL_IsFreqMeasComplete(void)345 STATIC INLINE bool Chip_SYSCTL_IsFreqMeasComplete(void)
346 {
347 return (bool) ((LPC_SYSCTL->FREQMECTRL & (1UL << 31)) == 0);
348 }
349
350 /**
351 * @brief Returns the raw capture value for a frequency measurement cycle
352 * @return raw cpature value (this is not a frequency)
353 */
Chip_SYSCTL_GetRawFreqMeasCapval(void)354 STATIC INLINE uint32_t Chip_SYSCTL_GetRawFreqMeasCapval(void)
355 {
356 return LPC_SYSCTL->FREQMECTRL & 0x3FFF;
357 }
358
359 /**
360 * @brief Returns the computed value for a frequency measurement cycle
361 * @param refClockRate : Reference clock rate used during the frequency measurement cycle
362 * @return Computed cpature value
363 */
364 uint32_t Chip_SYSCTL_GetCompFreqMeas(uint32_t refClockRate);
365
366 /**
367 * @brief FLASH Access time definitions
368 */
369 typedef enum {
370 SYSCTL_FLASHTIM_25MHZ_CPU = 0, /*!< Flash accesses use 1 CPU clocks. Use for up to 25 MHz CPU clock*/
371 SYSCTL_FLASHTIM_55MHZ_CPU = 1, /*!< Flash accesses use 2 CPU clocks. Use for up to 55 MHz CPU clock*/
372 SYSCTL_FLASHTIM_72MHZ_CPU = 2, /*!< Flash accesses use 3 CPU clocks. Use for up to 72 MHz CPU clock*/
373 } SYSCTL_FLASHTIM_T;
374
375 /**
376 * @brief Set FLASH access time in clocks
377 * @param clks : Clock cycles for FLASH access (minus 1)
378 * @return Nothing
379 */
Chip_FMC_SetFLASHAccess(SYSCTL_FLASHTIM_T clks)380 STATIC INLINE void Chip_FMC_SetFLASHAccess(SYSCTL_FLASHTIM_T clks)
381 {
382 uint32_t tmp = LPC_SYSCTL->FLASHCFG & (~(0x3 << 12));
383
384 /* Don't alter other bits */
385 LPC_SYSCTL->FLASHCFG = tmp | ((clks & 0x03) << 12);
386 }
387
388 /**
389 * @brief Setup USB clock control
390 * @param ap_clk : USB need_clock signal control (0 or 1)
391 * @param pol_clk : USB need_clock polarity for triggering the USB wake-up interrupt (0 or 1)
392 * @return Nothing
393 * @note See the USBCLKCTRL register in the user manual for these settings.
394 */
Chip_SYSCTL_SetUSBCLKCTRL(uint32_t ap_clk,uint32_t pol_clk)395 STATIC INLINE void Chip_SYSCTL_SetUSBCLKCTRL(uint32_t ap_clk, uint32_t pol_clk)
396 {
397 LPC_SYSCTL->USBCLKCTRL = ap_clk | (pol_clk << 1);
398 }
399
400 /**
401 * @brief Returns the status of the USB need_clock signal
402 * @return true if USB need_clock status is high, otherwise false
403 */
Chip_SYSCTL_GetUSBCLKStatus(void)404 STATIC INLINE bool Chip_SYSCTL_GetUSBCLKStatus(void)
405 {
406 return (bool) ((LPC_SYSCTL->USBCLKST & 0x1) != 0);
407 }
408
409 /**
410 * Peripheral interrupt wakeup events on STARTERP0 only
411 */
412 #define SYSCTL_ERP0_WAKEUP_WDTINT (1 << 0) /*!< WWDT interrupt wake-up */
413 #define SYSCTL_ERP0_WAKEUP_BODINT (1 << 1) /*!< Brown out detector interrupt wake-up */
414 #define SYSCTL_ERP0_WAKEUP_GINT0INT (1 << 5) /*!< Group interrupt 0 wake-up */
415 #define SYSCTL_ERP0_WAKEUP_GINT1INT (1 << 6) /*!< Group interrupt 1 wake-up */
416 #define SYSCTL_ERP0_WAKEUP_PINT0INT (1 << 7) /*!< GPIO pin interrupt 0 wake-up */
417 #define SYSCTL_ERP0_WAKEUP_PINT1INT (1 << 8) /*!< GPIO pin interrupt 1 wake-up */
418 #define SYSCTL_ERP0_WAKEUP_PINT2INT (1 << 9) /*!< GPIO pin interrupt 2 wake-up */
419 #define SYSCTL_ERP0_WAKEUP_PINT3INT (1 << 10) /*!< GPIO pin interrupt 3 wake-up */
420 #define SYSCTL_ERP0_WAKEUP_PINT4INT (1 << 11) /*!< GPIO pin interrupt 4 wake-up */
421 #define SYSCTL_ERP0_WAKEUP_PINT5INT (1 << 12) /*!< GPIO pin interrupt 5 wake-up */
422 #define SYSCTL_ERP0_WAKEUP_PINT6INT (1 << 13) /*!< GPIO pin interrupt 6 wake-up */
423 #define SYSCTL_ERP0_WAKEUP_PINT7INT (1 << 14) /*!< GPIO pin interrupt 7 wake-up */
424 #define SYSCTL_ERP0_WAKEUP_USART0INT (1 << 21) /*!< USART0 interrupt wake-up */
425 #define SYSCTL_ERP0_WAKEUP_USART1INT (1 << 22) /*!< USART1 interrupt wake-up */
426 #define SYSCTL_ERP0_WAKEUP_USART2INT (1 << 23) /*!< USART2 interrupt wake-up */
427 #define SYSCTL_ERP0_WAKEUP_I2CINT (1 << 24) /*!< I2C interrupt wake-up */
428 #define SYSCTL_ERP0_WAKEUP_SPI0INT (1 << 25) /*!< SPI0 interrupt wake-up */
429 #define SYSCTL_ERP0_WAKEUP_SPI1INT (1 << 26) /*!< SPI1 interrupt wake-up */
430 #define SYSCTL_ERP0_WAKEUP_USB_WAKEUP (1 << 30) /*!< USB need_clock signal wake-up */
431
432 /**
433 * @brief Enables a peripheral's wakeup logic (STARTERP0 only)
434 * @param periphmask : OR'ed values of SYSCTL_ERP0_* for wakeup
435 * @return Nothing
436 * @note Use this function only with definitions of type SYSCTL_ERP0_*. Do
437 * not use or mix with SYSCTL_ERP1_* definitions.
438 */
Chip_SYSCTL_EnableERP0PeriphWakeup(uint32_t periphmask)439 STATIC INLINE void Chip_SYSCTL_EnableERP0PeriphWakeup(uint32_t periphmask)
440 {
441 LPC_SYSCTL->STARTERP[0] |= periphmask;
442 }
443
444 /**
445 * @brief Disables a peripheral's wakeup logic (STARTERP0 only)
446 * @param periphmask : OR'ed values of SYSCTL_ERP0_* for wakeup
447 * @return Nothing
448 * @note Use this function only with definitions of type SYSCTL_ERP0_*. Do
449 * not use or mix with SYSCTL_ERP1_* definitions.
450 */
Chip_SYSCTL_DisableERP0PeriphWakeup(uint32_t periphmask)451 STATIC INLINE void Chip_SYSCTL_DisableERP0PeriphWakeup(uint32_t periphmask)
452 {
453 LPC_SYSCTL->STARTERP[0] &= ~periphmask;
454 }
455
456 /**
457 * Peripheral interrupt wakeup events on STARTERP1 only
458 */
459 #define SYSCTL_ERP1_WAKEUP_ACMP0INT (1 << 8) /*!< Analog comparator 0 interrupt wake-up */
460 #define SYSCTL_ERP1_WAKEUP_ACMP1INT (1 << 9) /*!< Analog comparator 1 interrupt wake-up */
461 #define SYSCTL_ERP1_WAKEUP_ACMP2INT (1 << 10) /*!< Analog comparator 2 interrupt wake-up */
462 #define SYSCTL_ERP1_WAKEUP_ACMP3INT (1 << 11) /*!< Analog comparator 3 interrupt wake-up */
463 #define SYSCTL_ERP1_WAKEUP_RTCALARMINT (1 << 13) /*!< RTC alarm interrupt wake-up */
464 #define SYSCTL_ERP1_WAKEUP_RTCWAKEINT (1 << 14) /*!< RTC wake (1KHz wake) interrupt wake-up */
465
466 /**
467 * @brief Enables a peripheral's wakeup logic (STARTERP0 only)
468 * @param periphmask : OR'ed values of SYSCTL_ERP1_* for wakeup
469 * @return Nothing
470 * @note Use this function only with definitions of type SYSCTL_ERP1_*. Do
471 * not use or mix with SYSCTL_ERP1_* definitions.
472 */
Chip_SYSCTL_EnableERP1PeriphWakeup(uint32_t periphmask)473 STATIC INLINE void Chip_SYSCTL_EnableERP1PeriphWakeup(uint32_t periphmask)
474 {
475 LPC_SYSCTL->STARTERP[1] |= periphmask;
476 }
477
478 /**
479 * @brief Disables a peripheral's wakeup logic (STARTERP1 only)
480 * @param periphmask : OR'ed values of SYSCTL_ERP1_* for wakeup
481 * @return Nothing
482 * @note Use this function only with definitions of type SYSCTL_ERP1_*. Do
483 * not use or mix with SYSCTL_ERP1_* definitions.
484 */
Chip_SYSCTL_DisableERP1PeriphWakeup(uint32_t periphmask)485 STATIC INLINE void Chip_SYSCTL_DisableERP1PeriphWakeup(uint32_t periphmask)
486 {
487 LPC_SYSCTL->STARTERP[1] &= ~periphmask;
488 }
489
490 /**
491 * Deep sleep to wakeup setup values
492 */
493 #define SYSCTL_SLPWAKE_TBD0_PD (1 << 0) /*!< TBD0 wake-up configuration */
494 #define SYSCTL_SLPWAKE_TBD1_PD (1 << 1) /*!< TBD1 wake-up configuration */
495 #define SYSCTL_SLPWAKE_TBD2_PD (1 << 2) /*!< TBD2 wake-up configuration */
496 #define SYSCTL_SLPWAKE_IRCOUT_PD (1 << 3) /*!< IRC oscillator output wake-up configuration */
497 #define SYSCTL_SLPWAKE_IRC_PD (1 << 4) /*!< IRC oscillator power-down wake-up configuration */
498 #define SYSCTL_SLPWAKE_FLASH_PD (1 << 5) /*!< Flash wake-up configuration */
499 #define SYSCTL_SLPWAKE_EEPROM_PD (1 << 6) /*!< EEPROM wake-up configuration */
500 #define SYSCTL_SLPWAKE_BOD_PD (1 << 8) /*!< BOD wake-up configuration */
501 #define SYSCTL_SLPWAKE_USBPHY_PD (1 << 9) /*!< USB PHY wake-up configuration */
502 #define SYSCTL_SLPWAKE_ADC0_PD (1 << 10) /*!< ADC0 wake-up configuration */
503 #define SYSCTL_SLPWAKE_ADC1_PD (1 << 11) /*!< ADC1 wake-up configuration */
504 #define SYSCTL_SLPWAKE_DAC_PD (1 << 12) /*!< DAC wake-up configuration */
505 #define SYSCTL_SLPWAKE_ACMP0_PD (1 << 13) /*!< ACMP0 wake-up configuration */
506 #define SYSCTL_SLPWAKE_ACMP1_PD (1 << 14) /*!< ACMP0 wake-up configuration */
507 #define SYSCTL_SLPWAKE_ACMP2_PD (1 << 15) /*!< ACMP0 wake-up configuration */
508 #define SYSCTL_SLPWAKE_ACMP3_PD (1 << 16) /*!< ACMP0 wake-up configuration */
509 #define SYSCTL_SLPWAKE_IREF_PD (1 << 17) /*!< Internal voltage reference wake-up configuration */
510 #define SYSCTL_SLPWAKE_TS_PD (1 << 18) /*!< Temperature sensor wake-up configuration */
511 #define SYSCTL_SLPWAKE_VDDADIV_PD (1 << 19) /*!< VDDA divider wake-up configuration */
512 #define SYSCTL_SLPWAKE_WDTOSC_PD (1 << 20) /*!< Watchdog oscillator wake-up configuration */
513 #define SYSCTL_SLPWAKE_SYSOSC_PD (1 << 21) /*!< System oscillator wake-up configuration */
514 #define SYSCTL_SLPWAKE_SYSPLL_PD (1 << 22) /*!< System PLL wake-up configuration */
515 #define SYSCTL_SLPWAKE_USBPLL_PD (1 << 23) /*!< USB PLL wake-up configuration */
516 #define SYSCTL_SLPWAKE_SCTPLL_PD (1 << 24) /*!< SCT PLL wake-up configuration */
517
518 /**
519 * @brief Setup wakeup behaviour from deep sleep
520 * @param wakeupmask : OR'ed values of SYSCTL_SLPWAKE_* values (high is powered down)
521 * @return Nothing
522 * @note This must be setup prior to using deep sleep. See the user manual
523 * (PDWAKECFG register) for more info on setting this up. This function selects
524 * which peripherals are powered up on exit from deep sleep.
525 * This function should only be called once with all options for wakeup
526 * in that call.
527 */
528 void Chip_SYSCTL_SetWakeup(uint32_t wakeupmask);
529
530 /**
531 * @brief Return current wakeup mask
532 * @return OR'ed values of SYSCTL_SLPWAKE_* values
533 * @note A high state indicates the peripehral will powerup on wakeup.
534 */
Chip_SYSCTL_GetWakeup(void)535 STATIC INLINE uint32_t Chip_SYSCTL_GetWakeup(void)
536 {
537 return LPC_SYSCTL->PDWAKECFG;
538 }
539
540 /**
541 * Power down configuration values
542 */
543 #define SYSCTL_POWERDOWN_TBD0_PD (1 << 0) /*!< TBD0 wake-up power down */
544 #define SYSCTL_POWERDOWN_TBD1_PD (1 << 1) /*!< TBD1 wake-up power down */
545 #define SYSCTL_POWERDOWN_TBD2_PD (1 << 2) /*!< TBD2 wake-up power down */
546 #define SYSCTL_POWERDOWN_IRCOUT_PD (1 << 3) /*!< IRC oscillator output wake-up power down */
547 #define SYSCTL_POWERDOWN_IRC_PD (1 << 4) /*!< IRC oscillator power-down wake-up power down */
548 #define SYSCTL_POWERDOWN_FLASH_PD (1 << 5) /*!< Flash wake-up power down */
549 #define SYSCTL_POWERDOWN_EEPROM_PD (1 << 6) /*!< EEPROM wake-up power down */
550 #define SYSCTL_POWERDOWN_BOD_PD (1 << 8) /*!< BOD wake-up power down */
551 #define SYSCTL_POWERDOWN_USBPHY_PD (1 << 9) /*!< USB PHY wake-up power down */
552 #define SYSCTL_POWERDOWN_ADC0_PD (1 << 10) /*!< ADC0 wake-up power down */
553 #define SYSCTL_POWERDOWN_ADC1_PD (1 << 11) /*!< ADC1 wake-up power down */
554 #define SYSCTL_POWERDOWN_DAC_PD (1 << 12) /*!< DAC wake-up power down */
555 #define SYSCTL_POWERDOWN_ACMP0_PD (1 << 13) /*!< ACMP0 wake-up power down */
556 #define SYSCTL_POWERDOWN_ACMP1_PD (1 << 14) /*!< ACMP0 wake-up power down */
557 #define SYSCTL_POWERDOWN_ACMP2_PD (1 << 15) /*!< ACMP0 wake-up power down */
558 #define SYSCTL_POWERDOWN_ACMP3_PD (1 << 16) /*!< ACMP0 wake-up power down */
559 #define SYSCTL_POWERDOWN_IREF_PD (1 << 17) /*!< Internal voltage reference wake-up power down */
560 #define SYSCTL_POWERDOWN_TS_PD (1 << 18) /*!< Temperature sensor wake-up power down */
561 #define SYSCTL_POWERDOWN_VDDADIV_PD (1 << 19) /*!< VDDA divider wake-up power down */
562 #define SYSCTL_POWERDOWN_WDTOSC_PD (1 << 20) /*!< Watchdog oscillator wake-up power down */
563 #define SYSCTL_POWERDOWN_SYSOSC_PD (1 << 21) /*!< System oscillator wake-up power down */
564 #define SYSCTL_POWERDOWN_SYSPLL_PD (1 << 22) /*!< System PLL wake-up power down */
565 #define SYSCTL_POWERDOWN_USBPLL_PD (1 << 23) /*!< USB PLL wake-up power down */
566 #define SYSCTL_POWERDOWN_SCTPLL_PD (1 << 24) /*!< SCT PLL wake-up power down */
567
568 /**
569 * @brief Power down one or more blocks or peripherals
570 * @param powerdownmask : OR'ed values of SYSCTL_POWERDOWN_* values
571 * @return Nothing
572 */
573 void Chip_SYSCTL_PowerDown(uint32_t powerdownmask);
574
575 /**
576 * @brief Power up one or more blocks or peripherals
577 * @param powerupmask : OR'ed values of SYSCTL_POWERDOWN_* values
578 * @return Nothing
579 */
580 void Chip_SYSCTL_PowerUp(uint32_t powerupmask);
581
582 /**
583 * @brief Get power status
584 * @return OR'ed values of SYSCTL_POWERDOWN_* values
585 * @note A high state indicates the peripheral is powered down.
586 */
Chip_SYSCTL_GetPowerStates(void)587 STATIC INLINE uint32_t Chip_SYSCTL_GetPowerStates(void)
588 {
589 return LPC_SYSCTL->PDRUNCFG;
590 }
591
592 /**
593 * @brief Return the JTAG ID code
594 * @return the JTAG ID code
595 */
Chip_SYSCTL_GetJTAGIDCode(void)596 STATIC INLINE uint32_t Chip_SYSCTL_GetJTAGIDCode(void)
597 {
598 return LPC_SYSCTL->JTAG_IDCODE;
599 }
600
601 /**
602 * @brief Return the device ID
603 * @param index : Index of device ID to get, 0 or 1
604 * @return the device ID
605 */
Chip_SYSCTL_GetDeviceID(int index)606 STATIC INLINE uint32_t Chip_SYSCTL_GetDeviceID(int index)
607 {
608 return LPC_SYSCTL->DEVICEID[index];
609 }
610
611 /**
612 * @}
613 */
614
615 #ifdef __cplusplus
616 }
617 #endif
618
619 #endif /*!< __SYSCTL_15XX_H_ */
620