1 /*
2 * @brief LPC15XX Clock control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2013
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __CLOCK_15XX_H_
33 #define __CLOCK_15XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /** @defgroup CLOCK_15XX CHIP: LPC15xx Clock Control block driver
40 * @ingroup CHIP_15XX_Drivers
41 * @{
42 */
43
44 /** Internal oscillator frequency */
45 #define SYSCTL_IRC_FREQ (12000000)
46
47 /** Internal watchdog oscillator frequency */
48 #define SYSCTL_WDTOSC_FREQ (503000)
49
50 /** @defgroup CLOCK_15XXcCHIP_SEL: Clock source selection functions
51 * These functions provide selection of clocks for system functions such as
52 * the USB clock, main system clock, or the clock output pin.
53 * @{
54 */
55
56 /**
57 * Clock source selections for only the main A system clock. The main A system
58 * clock is used as an input into the main B system clock selector. Main clock A
59 * only needs to be setup if the main clock A input is used in the main clock
60 * system selector.
61 */
62 typedef enum CHIP_SYSCTL_MAIN_A_CLKSRC {
63 SYSCTL_MAIN_A_CLKSRC_IRC = 0, /*!< Internal oscillator */
64 SYSCTL_MAIN_A_CLKSRCA_MAINOSC, /*!< Crystal (main) oscillator in */
65 SYSCTL_MAIN_A_CLKSRCA_SYSOSC = SYSCTL_MAIN_A_CLKSRCA_MAINOSC,
66 SYSCTL_MAIN_A_CLKSRCA_WDTOSC, /*!< Watchdog oscillator rate */
67 SYSCTL_MAIN_A_CLKSRCA_RESERVED,
68 } CHIP_SYSCTL_MAIN_A_CLKSRC_T;
69
70 /**
71 * @brief Set main A system clock source
72 * @param src : Clock source for main A
73 * @return Nothing
74 * @note This function only neesd to be setup if main clock A will be
75 * selected in the Chip_Clock_GetMain_B_ClockRate() function.
76 */
Chip_Clock_SetMain_A_ClockSource(CHIP_SYSCTL_MAIN_A_CLKSRC_T src)77 STATIC INLINE void Chip_Clock_SetMain_A_ClockSource(CHIP_SYSCTL_MAIN_A_CLKSRC_T src)
78 {
79 LPC_SYSCTL->MAINCLKSELA = (uint32_t) src;
80 }
81
82 /**
83 * @brief Returns the main A clock source
84 * @return Returns which clock is used for the main A
85 */
Chip_Clock_GetMain_A_ClockSource(void)86 STATIC INLINE CHIP_SYSCTL_MAIN_A_CLKSRC_T Chip_Clock_GetMain_A_ClockSource(void)
87 {
88 return (CHIP_SYSCTL_MAIN_A_CLKSRC_T) (LPC_SYSCTL->MAINCLKSELA);
89 }
90
91 /**
92 * @brief Return main A clock rate
93 * @return main A clock rate in Hz
94 */
95 uint32_t Chip_Clock_GetMain_A_ClockRate(void);
96
97 /**
98 * Clock sources for only main B system clock
99 */
100 typedef enum CHIP_SYSCTL_MAIN_B_CLKSRC {
101 SYSCTL_MAIN_B_CLKSRC_MAINCLKSELA = 0, /*!< main clock A */
102 SYSCTL_MAIN_B_CLKSRC_SYSPLLIN, /*!< System PLL input */
103 SYSCTL_MAIN_B_CLKSRC_SYSPLLOUT, /*!< System PLL output */
104 SYSCTL_MAIN_B_CLKSRC_RTC, /*!< RTC oscillator 32KHz output */
105 } CHIP_SYSCTL_MAIN_B_CLKSRC_T;
106
107 /**
108 * @brief Set main B system clock source
109 * @param src : Clock source for main B
110 * @return Nothing
111 */
Chip_Clock_SetMain_B_ClockSource(CHIP_SYSCTL_MAIN_B_CLKSRC_T src)112 STATIC INLINE void Chip_Clock_SetMain_B_ClockSource(CHIP_SYSCTL_MAIN_B_CLKSRC_T src)
113 {
114 LPC_SYSCTL->MAINCLKSELB = (uint32_t) src;
115 }
116
117 /**
118 * @brief Returns the main B clock source
119 * @return Returns which clock is used for the main B
120 */
Chip_Clock_GetMain_B_ClockSource(void)121 STATIC INLINE CHIP_SYSCTL_MAIN_B_CLKSRC_T Chip_Clock_GetMain_B_ClockSource(void)
122 {
123 return (CHIP_SYSCTL_MAIN_B_CLKSRC_T) (LPC_SYSCTL->MAINCLKSELB);
124 }
125
126 /**
127 * @brief Return main B clock rate
128 * @return main B clock rate
129 */
130 uint32_t Chip_Clock_GetMain_B_ClockRate(void);
131
132 /**
133 * Clock sources for main system clock. This is a mix of both main clock A
134 * and B seelctions.
135 */
136 typedef enum CHIP_SYSCTL_MAINCLKSRC {
137 SYSCTL_MAINCLKSRC_IRC = 0, /*!< Internal oscillator */
138 SYSCTL_MAINCLKSRCA_MAINOSC, /*!< Crystal (main) oscillator in */
139 SYSCTL_MAINCLKSRCA_SYSOSC = SYSCTL_MAINCLKSRCA_MAINOSC,
140 SYSCTL_MAINCLKSRCA_WDTOSC, /*!< Watchdog oscillator rate */
141 SYSCTL_MAINCLKSRC_SYSPLLIN = 5, /*!< System PLL input */
142 SYSCTL_MAINCLKSRC_SYSPLLOUT, /*!< System PLL output */
143 SYSCTL_MAINCLKSRC_RTC, /*!< RTC oscillator 32KHz output */
144 } CHIP_SYSCTL_MAINCLKSRC_T;
145
146 /**
147 * @brief Set main system clock source
148 * @param src : Main clock source
149 * @return Nothing
150 * @note This functions handles setup of both A and B main clock sources.
151 */
152 void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src);
153
154 /**
155 * @brief Returns the main clock source
156 * @return Returns which clock is used for the main clock source
157 * @note This functions handles both A and B main clock sources.
158 */
159 CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void);
160
161 /**
162 * @brief Return main clock rate
163 * @return main clock rate
164 */
165 uint32_t Chip_Clock_GetMainClockRate(void);
166
167 /**
168 * @brief Return system clock rate
169 * @return system clock rate
170 */
171 uint32_t Chip_Clock_GetSystemClockRate(void);
172
173 /**
174 * Clock sources for USB (usb_clk)
175 */
176 typedef enum CHIP_SYSCTL_USBCLKSRC {
177 SYSCTL_USBCLKSRC_IRC = 0, /*!< Internal oscillator */
178 SYSCTL_USBCLKSRC_MAINOSC, /*!< Crystal (main) oscillator in */
179 SYSCTL_USBCLKSRC_SYSOSC = SYSCTL_USBCLKSRC_MAINOSC,
180 SYSCTL_USBCLKSRC_PLLOUT, /*!< USB PLL out */
181 SYSCTL_USBCLKSRC_MAINSYSCLK, /*!< Main system clock (B) */
182 } CHIP_SYSCTL_USBCLKSRC_T;
183
184 /**
185 * @brief Set USB clock source and divider
186 * @param src : Clock source for USB
187 * @param div : divider for USB clock
188 * @return Nothing
189 * @note Use 0 to disable, or a divider value of 1 to 255. The USB clock
190 * rate is either the main system clock or USB PLL output clock divided
191 * by this value. This function will also toggle the clock source
192 * update register to update the clock source.
193 */
Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src,uint32_t div)194 STATIC INLINE void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div)
195 {
196 LPC_SYSCTL->USBCLKSEL = (uint32_t) src;
197 LPC_SYSCTL->USBCLKDIV = div;
198 }
199
200 /**
201 * Clock sources for ADC asynchronous clock source select
202 */
203 typedef enum CHIP_SYSCTL_ADCASYNCCLKSRC {
204 SYSCTL_ADCASYNCCLKSRC_IRC = 0, /*!< Internal oscillator */
205 SYSCTL_ADCASYNCCLKSRC_SYSPLLOUT, /*!< System PLL out */
206 SYSCTL_ADCASYNCCLKSRC_USBPLLOUT, /*!< USB PLL out */
207 SYSCTL_ADCASYNCCLKSRC_SCTPLLOUT /*!< SCT PLL out */
208 } CHIP_SYSCTL_ADCASYNCCLKSRC_T;
209
210 /**
211 * @brief Set the ADC asynchronous clock source
212 * @param src : ADC asynchronous clock source
213 * @return Nothing
214 */
Chip_Clock_SetADCASYNCSource(CHIP_SYSCTL_ADCASYNCCLKSRC_T src)215 STATIC INLINE void Chip_Clock_SetADCASYNCSource(CHIP_SYSCTL_ADCASYNCCLKSRC_T src)
216 {
217 LPC_SYSCTL->ADCASYNCCLKSEL = (uint32_t) src;
218 }
219
220 /**
221 * @brief Returns the ADC asynchronous clock source
222 * @return Returns which clock is used for the ADC asynchronous clock source
223 */
Chip_Clock_GetADCASYNCSource(void)224 STATIC INLINE CHIP_SYSCTL_ADCASYNCCLKSRC_T Chip_Clock_GetADCASYNCSource(void)
225 {
226 return (CHIP_SYSCTL_ADCASYNCCLKSRC_T) (LPC_SYSCTL->ADCASYNCCLKSEL);
227 }
228
229 /**
230 * @brief Return ADC asynchronous clock rate
231 * @return ADC asynchronous clock rate (not including divider)
232 */
233 uint32_t Chip_Clock_GetADCASYNCRate(void);
234
235 /**
236 * Clock sources for CLKOUT
237 */
238 typedef enum CHIP_SYSCTL_CLKOUTSRC {
239 SYSCTL_CLKOUTSRC_IRC = 0, /*!< Internal oscillator for CLKOUT */
240 SYSCTL_CLKOUTSRC_MAINOSC, /*!< Main oscillator for CLKOUT */
241 SYSCTL_CLKOUTSRC_SYSOSC = SYSCTL_CLKOUTSRC_MAINOSC,
242 SYSCTL_CLKOUTSRC_WDTOSC, /*!< Watchdog oscillator for CLKOUT */
243 SYSCTL_CLKOUTSRC_MAINSYSCLK, /*!< Main (B) system clock for CLKOUT */
244 SYSCTL_CLKOUTSRC_USBPLLOUT = 5, /*!< USB PLL out */
245 SYSCTL_CLKOUTSRC_SCTPLLOUT, /*!< SCT PLL out */
246 SYSCTL_CLKOUTSRC_RTC32K /*!< RTC 32 kHz output */
247 } CHIP_SYSCTL_CLKOUTSRC_T;
248
249 /**
250 * @brief Set CLKOUT clock source and divider
251 * @param src : Clock source for CLKOUT
252 * @param div : divider for CLKOUT clock
253 * @return Nothing
254 * @note Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock
255 * rate is the clock source divided by the divider. This function will
256 * also toggle the clock source update register to update the clock
257 * source.
258 */
259 void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);
260
261 /**
262 * @}
263 */
264
265 /** @defgroup CLOCK_15XX_CHIP_PLL: PLL setup functions
266 * @{
267 */
268
269 /**
270 * Clock sources for system, USB, and SCT PLLs
271 */
272 typedef enum CHIP_SYSCTL_PLLCLKSRC {
273 SYSCTL_PLLCLKSRC_IRC = 0, /*!< Internal oscillator in (may not work for USB) */
274 SYSCTL_PLLCLKSRC_MAINOSC, /*!< Crystal (main) oscillator in */
275 SYSCTL_PLLCLKSRC_SYSOSC = SYSCTL_PLLCLKSRC_MAINOSC,
276 SYSCTL_PLLCLKSRC_RESERVED1, /*!< Reserved */
277 SYSCTL_PLLCLKSRC_RESERVED2, /*!< Reserved */
278 } CHIP_SYSCTL_PLLCLKSRC_T;
279
280 /**
281 * @brief Set System PLL clock source
282 * @param src : Clock source for system PLL
283 * @return Nothing
284 */
Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)285 STATIC INLINE void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
286 {
287 LPC_SYSCTL->SYSPLLCLKSEL = (uint32_t) src;
288 }
289
290 /**
291 * @brief Set System PLL divider values
292 * @param msel : PLL feedback divider value. M = msel + 1.
293 * @param psel : PLL post divider value. P = (1<<psel).
294 * @return Nothing
295 * @note See the user manual for how to setup the PLL.
296 */
Chip_Clock_SetupSystemPLL(uint8_t msel,uint8_t psel)297 STATIC INLINE void Chip_Clock_SetupSystemPLL(uint8_t msel, uint8_t psel)
298 {
299 LPC_SYSCTL->SYSPLLCTRL = (msel & 0x3F) | ((psel & 0x3) << 6);
300 }
301
302 /**
303 * @brief Read System PLL lock status
304 * @return true of the PLL is locked. false if not locked
305 */
Chip_Clock_IsSystemPLLLocked(void)306 STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void)
307 {
308 return (bool) ((LPC_SYSCTL->SYSPLLSTAT & 1) != 0);
309 }
310
311 /**
312 * @brief Return System PLL input clock rate
313 * @return System PLL input clock rate
314 */
315 uint32_t Chip_Clock_GetSystemPLLInClockRate(void);
316
317 /**
318 * @brief Return System PLL output clock rate
319 * @return System PLL output clock rate
320 */
321 uint32_t Chip_Clock_GetSystemPLLOutClockRate(void);
322
323 /**
324 * @brief Set USB PLL clock source
325 * @param src : Clock source for USB PLL
326 * @return Nothing
327 */
Chip_Clock_SetUSBPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)328 STATIC INLINE void Chip_Clock_SetUSBPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
329 {
330 LPC_SYSCTL->USBPLLCLKSEL = (uint32_t) src;
331 }
332
333 /**
334 * @brief Set USB PLL divider values
335 * @param msel : PLL feedback divider value. M = msel + 1.
336 * @param psel : PLL post divider value. P = (1<<psel).
337 * @return Nothing
338 * @note See the user manual for how to setup the PLL.
339 */
Chip_Clock_SetupUSBPLL(uint8_t msel,uint8_t psel)340 STATIC INLINE void Chip_Clock_SetupUSBPLL(uint8_t msel, uint8_t psel)
341 {
342 LPC_SYSCTL->USBPLLCTRL = (msel & 0x3F) | ((psel & 0x3) << 6);
343 }
344
345 /**
346 * @brief Read USB PLL lock status
347 * @return true of the PLL is locked. false if not locked
348 */
Chip_Clock_IsUSBPLLLocked(void)349 STATIC INLINE bool Chip_Clock_IsUSBPLLLocked(void)
350 {
351 return (bool) ((LPC_SYSCTL->USBPLLSTAT & 1) != 0);
352 }
353
354 /**
355 * @brief Return USB PLL input clock rate
356 * @return USB PLL input clock rate
357 */
358 uint32_t Chip_Clock_GetUSBPLLInClockRate(void);
359
360 /**
361 * @brief Return USB PLL output clock rate
362 * @return USB PLL output clock rate
363 */
364 uint32_t Chip_Clock_GetUSBPLLOutClockRate(void);
365
366 /**
367 * @brief Set SCT PLL clock source
368 * @param src : Clock source for SCT PLL
369 * @return Nothing
370 */
Chip_Clock_SetSCTPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)371 STATIC INLINE void Chip_Clock_SetSCTPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
372 {
373 LPC_SYSCTL->SCTPLLCLKSEL = (uint32_t) src;
374 }
375
376 /**
377 * @brief Set SCT PLL divider values
378 * @param msel : PLL feedback divider value. M = msel + 1.
379 * @param psel : PLL post divider value. P = (1<<psel).
380 * @return Nothing
381 * @note See the user manual for how to setup the PLL.
382 */
Chip_Clock_SetupSCTPLL(uint8_t msel,uint8_t psel)383 STATIC INLINE void Chip_Clock_SetupSCTPLL(uint8_t msel, uint8_t psel)
384 {
385 LPC_SYSCTL->SCTPLLCTRL = (msel & 0x3F) | ((psel & 0x3) << 6);
386 }
387
388 /**
389 * @brief Read SCT PLL lock status
390 * @return true of the PLL is locked. false if not locked
391 */
Chip_Clock_IsSCTPLLLocked(void)392 STATIC INLINE bool Chip_Clock_IsSCTPLLLocked(void)
393 {
394 return (bool) ((LPC_SYSCTL->SCTPLLSTAT & 1) != 0);
395 }
396
397 /**
398 * @brief Return SCT PLL input clock rate
399 * @return SCT PLL input clock rate
400 */
401 uint32_t Chip_Clock_GetSCTPLLInClockRate(void);
402
403 /**
404 * @brief Return SCT PLL output clock rate
405 * @return SCT PLL output clock rate
406 */
407 uint32_t Chip_Clock_GetSCTPLLOutClockRate(void);
408
409 /**
410 * @}
411 */
412
413 /** @defgroup CLOCK_15XX_CHIP_SUP: Clock support functions
414 * Functions in this group include oscillator control and rates, peripheral
415 * clock control, and peripheral dividers.
416 * @{
417 */
418
419 /**
420 * @brief Set system clock divider
421 * @param div : divider for system clock
422 * @return Nothing
423 * @note Use 0 to disable, or a divider value of 1 to 255. The system clock
424 * rate is the main system clock divided by this value.
425 */
Chip_Clock_SetSysClockDiv(uint32_t div)426 STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div)
427 {
428 LPC_SYSCTL->SYSAHBCLKDIV = div;
429 }
430
431 /**
432 * System and peripheral clocks
433 */
434 typedef enum CHIP_SYSCTL_CLOCK {
435 /* Peripheral clock enables for SYSAHBCLKCTRL0 */
436 SYSCTL_CLOCK_SYS = 0, /*!< System clock */
437 SYSCTL_CLOCK_ROM, /*!< ROM clock */
438 SYSCTL_CLOCK_SRAM1 = 3, /*!< SRAM1 clock */
439 SYSCTL_CLOCK_SRAM2, /*!< SRAM2 clock */
440 SYSCTL_CLOCK_FLASH = 7, /*!< FLASH controller clock */
441 SYSCTL_CLOCK_EEPROM = 9, /*!< EEPROM controller clock */
442 SYSCTL_CLOCK_MUX = 11, /*!< Input mux clock */
443 SYSCTL_CLOCK_SWM, /*!< Switch matrix clock */
444 SYSCTL_CLOCK_IOCON, /*!< IOCON clock */
445 SYSCTL_CLOCK_GPIO0, /*!< GPIO0 clock */
446 SYSCTL_CLOCK_GPIO1, /*!< GPIO1 clock */
447 SYSCTL_CLOCK_GPIO2, /*!< GPIO2 clock */
448 SYSCTL_CLOCK_PININT = 18, /*!< PININT clock */
449 SYSCTL_CLOCK_GINT, /*!< grouped pin interrupt block clock */
450 SYSCTL_CLOCK_DMA, /*!< DMA clock */
451 SYSCTL_CLOCK_CRC, /*!< CRC clock */
452 SYSCTL_CLOCK_WDT, /*!< WDT clock */
453 SYSCTL_CLOCK_RTC, /*!< RTC clock */
454 SYSCTL_CLOCK_ADC0 = 27, /*!< ADC0 clock */
455 SYSCTL_CLOCK_ADC1, /*!< ADC1 clock */
456 SYSCTL_CLOCK_DAC, /*!< DAC clock */
457 SYSCTL_CLOCK_ACMP, /*!< ACMP clock */
458 /* Peripheral clock enables for SYSAHBCLKCTRL1 */
459 SYSCTL_CLOCK_MRT = 32, /*!< multi-rate timer clock */
460 SYSCTL_CLOCK_RIT, /*!< repetitive interrupt timer clock */
461 SYSCTL_CLOCK_SCT0, /*!< SCT0 clock */
462 SYSCTL_CLOCK_SCT1, /*!< SCT1 clock */
463 SYSCTL_CLOCK_SCT2, /*!< SCT2 clock */
464 SYSCTL_CLOCK_SCT3, /*!< SCT3 clock */
465 SYSCTL_CLOCK_SCTIPU, /*!< SCTIPU clock */
466 SYSCTL_CLOCK_CAN, /*!< CAN clock */
467 SYSCTL_CLOCK_SPI0 = 32 + 9, /*!< SPI0 clock */
468 SYSCTL_CLOCK_SPI1, /*!< SPI1 clock */
469 SYSCTL_CLOCK_I2C0 = 32 + 13, /*!< I2C0 clock */
470 SYSCTL_CLOCK_UART0 = 32 + 17, /*!< UART0 clock */
471 SYSCTL_CLOCK_UART1, /*!< UART1 clock */
472 SYSCTL_CLOCK_UART2, /*!< UART2 clock */
473 SYSCTL_CLOCK_QEI = 32 + 21, /*!< QEI clock */
474 SYSCTL_CLOCK_USB = 32 + 23, /*!< USB clock */
475 } CHIP_SYSCTL_CLOCK_T;
476
477 /**
478 * @brief Enable a system or peripheral clock
479 * @param clk : Clock to enable
480 * @return Nothing
481 */
482 void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk);
483
484 /**
485 * @brief Disable a system or peripheral clock
486 * @param clk : Clock to disable
487 * @return Nothing
488 */
489 void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk);
490
491 /**
492 * @brief Set system tick clock divider
493 * @param div : divider for system clock
494 * @return Nothing
495 * @note Use 0 to disable, or a divider value of 1 to 255. The system tick
496 * rate is the main system clock divided by this value. Use caution when using
497 * the CMSIS SysTick_Config() functions as they typically use SystemCoreClock
498 * for setup.
499 */
Chip_Clock_SetSysTickClockDiv(uint32_t div)500 STATIC INLINE void Chip_Clock_SetSysTickClockDiv(uint32_t div)
501 {
502 LPC_SYSCTL->SYSTICKCLKDIV = div;
503 }
504
505 /**
506 * @brief Returns system tick clock divider
507 * @return system tick clock divider
508 */
Chip_Clock_GetSysTickClockDiv(void)509 STATIC INLINE uint32_t Chip_Clock_GetSysTickClockDiv(void)
510 {
511 return LPC_SYSCTL->SYSTICKCLKDIV;
512 }
513
514 /**
515 * @brief Returns the system tick rate as used with the system tick divider
516 * @return the system tick rate
517 */
518 uint32_t Chip_Clock_GetSysTickClockRate(void);
519
520 /**
521 * @brief Set IOCON glitch filter clock divider value
522 * @param div : value for IOCON filter divider
523 * @return Nothing
524 * @note Use 0 to disable, or a divider value of 1 to 255.
525 */
Chip_Clock_SetIOCONFiltClockDiv(uint32_t div)526 STATIC INLINE void Chip_Clock_SetIOCONFiltClockDiv(uint32_t div)
527 {
528 LPC_SYSCTL->IOCONCLKDIV = div;
529 }
530
531 /**
532 * @brief Return IOCON glitch filter clock divider value
533 * @return IOCON glitch filter clock divider value
534 */
Chip_Clock_GetIOCONFiltClockDiv(void)535 STATIC INLINE uint32_t Chip_Clock_GetIOCONFiltClockDiv(void)
536 {
537 return LPC_SYSCTL->IOCONCLKDIV;
538 }
539
540 /**
541 * @brief Set Asynchronous ADC clock divider value
542 * @param div : value for UART fractional generator multiplier value
543 * @return Nothing
544 * @note Use 0 to disable, or a divider value of 1 to 255.
545 */
Chip_Clock_SetADCASYNCClockDiv(uint32_t div)546 STATIC INLINE void Chip_Clock_SetADCASYNCClockDiv(uint32_t div)
547 {
548 LPC_SYSCTL->ADCASYNCCLKDIV = div;
549 }
550
551 /**
552 * @brief Return Asynchronous ADC clock divider value
553 * @return Asynchronous ADC clock divider value
554 */
Chip_Clock_GetADCASYNCClockDiv(void)555 STATIC INLINE uint32_t Chip_Clock_GetADCASYNCClockDiv(void)
556 {
557 return LPC_SYSCTL->ADCASYNCCLKDIV;
558 }
559
560 /**
561 * @brief Set UART base rate base rate (up to main clock rate) (all UARTs)
562 * @param rate : Desired rate for fractional divider/multipler output
563 * @param fEnable : true to use fractional clocking, false for integer clocking
564 * @return Actual rate generated
565 * @note All UARTs use the same base clock for their baud rate
566 * basis. This function is used to generate that clock, while the
567 * UART driver's SetBaud functions will attempt to get the closest
568 * baud rate from this base clock without altering it. This needs
569 * to be setup prior to individual UART setup.<br>
570 * UARTs need a base clock 16x faster than the baud rate, so if you
571 * need a 115.2Kbps baud rate, you will need a clock rate of at
572 * least (115.2K * 16). The UART base clock is generated from the
573 * main system clock, so fractional clocking may be the only
574 * possible choice when using a low main system clock frequency.
575 * Do not alter the FRGCTRL or UARTCLKDIV registers after this call.
576 */
577 uint32_t Chip_Clock_SetUARTBaseClockRate(uint32_t rate, bool fEnable);
578
579 /**
580 * @brief Get UART base rate (all UARTs)
581 * @return UART base rate in Hz
582 */
583 uint32_t Chip_Clock_GetUARTBaseClockRate(void);
584
585 /**
586 * @brief Set The UART Fractional Generator Divider (all UARTs)
587 * @param div : Fractional Generator Divider value, should be 0xFF
588 * @return Nothing
589 */
Chip_Clock_SetUARTFRGDivider(uint8_t div)590 STATIC INLINE void Chip_Clock_SetUARTFRGDivider(uint8_t div)
591 {
592 LPC_SYSCTL->UARTCLKDIV = (uint32_t) div;
593 }
594
595 /**
596 * @brief Get The UART Fractional Generator Divider (all UARTs)
597 * @return Value of UART Fractional Generator Divider
598 */
Chip_Clock_GetUARTFRGDivider(void)599 STATIC INLINE uint32_t Chip_Clock_GetUARTFRGDivider(void)
600 {
601 return LPC_SYSCTL->UARTCLKDIV;
602 }
603
604 /**
605 * @brief Enable the RTC 32KHz output
606 * @return Nothing
607 * @note This clock can be used for the main clock directly, but
608 * do not use this clock with the system PLL.
609 */
Chip_Clock_EnableRTCOsc(void)610 STATIC INLINE void Chip_Clock_EnableRTCOsc(void)
611 {
612 LPC_SYSCTL->RTCOSCCTRL = 1;
613 }
614
615 /**
616 * @brief Disable the RTC 32KHz output
617 * @return Nothing
618 */
Chip_Clock_DisableRTCOsc(void)619 STATIC INLINE void Chip_Clock_DisableRTCOsc(void)
620 {
621 LPC_SYSCTL->RTCOSCCTRL = 0;
622 }
623
624 /**
625 * @brief Returns the main oscillator clock rate
626 * @return main oscillator clock rate in Hz
627 */
Chip_Clock_GetMainOscRate(void)628 STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
629 {
630 return OscRateIn;
631 }
632
633 /**
634 * @brief Returns the internal oscillator (IRC) clock rate
635 * @return internal oscillator (IRC) clock rate in Hz
636 */
Chip_Clock_GetIntOscRate(void)637 STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
638 {
639 return SYSCTL_IRC_FREQ;
640 }
641
642 /**
643 * @brief Returns the RTC clock rate
644 * @return RTC oscillator clock rate in Hz
645 */
Chip_Clock_GetRTCOscRate(void)646 STATIC INLINE uint32_t Chip_Clock_GetRTCOscRate(void)
647 {
648 return RTCOscRateIn;
649 }
650
651 /**
652 * @brief Return estimated watchdog oscillator rate
653 * @return Estimated watchdog oscillator rate
654 * @note This rate is accurate to plus or minus 40%.
655 */
Chip_Clock_GetWDTOSCRate(void)656 STATIC INLINE uint32_t Chip_Clock_GetWDTOSCRate(void)
657 {
658 return SYSCTL_WDTOSC_FREQ;
659 }
660
661 /**
662 * @}
663 */
664
665 /** @defgroup CLOCK_15XX_CHIP_MISC: Misc clock functions
666 * @{
667 */
668
669 /**
670 * @brief Bypass System Oscillator and set oscillator frequency range
671 * @param bypass : Flag to bypass oscillator
672 * @param highfr : Flag to set oscillator range from 15-25 MHz
673 * @return Nothing
674 * @note Sets the PLL input to bypass the oscillator. This would be
675 * used if an external clock that is not an oscillator is attached
676 * to the XTALIN pin.
677 */
678 void Chip_Clock_SetPLLBypass(bool bypass, bool highfr);
679
680 /**
681 * @}
682 */
683
684 /**
685 * @}
686 */
687
688 #ifdef __cplusplus
689 }
690 #endif
691
692 #endif /* __CLOCK_15XX_H_ */
693