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Searched refs:TRNG_BASE (Results 1 – 5 of 5) sorted by relevance

/lk-master/external/platform/cc13xx/cc13xxware/driverlib/
A Dtrng.h154 HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 1; in TRNGEnable()
168 HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 0; in TRNGDisable()
211 return (HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT)); in TRNGStatusGet()
230 HWREG(TRNG_BASE + TRNG_O_SWRESET) = 1; in TRNGReset()
261 HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK) |= ui32IntFlags; in TRNGIntEnable()
292 HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK) &= ~ui32IntFlags; in TRNGIntDisable()
323 ui32Mask = HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK); in TRNGIntStatus()
324 return(ui32Mask & HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT)); in TRNGIntStatus()
328 return(HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT) & 0x00000003); in TRNGIntStatus()
375 HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = ui32IntFlags; in TRNGIntClear()
A Dtrng.c69 ui32Val = HWREG(TRNG_BASE + TRNG_O_CTL) & ~TRNG_CTL_TRNG_EN; in TRNGConfigure()
70 HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; in TRNGConfigure()
77 HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; in TRNGConfigure()
83 HWREG(TRNG_BASE + TRNG_O_CFG0) = ( in TRNGConfigure()
110 ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT1); in TRNGNumberGet()
114 ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT0); in TRNGNumberGet()
120 HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = 0x1; in TRNGNumberGet()
/lk-master/external/platform/cc13xx/cc13xxware/inc/
A Dhw_memmap.h63 #define TRNG_BASE 0x40028000 // TRNG macro
/lk-master/platform/mediatek/mt6735/include/platform/
A Dmt_reg_base.h138 #define TRNG_BASE (0x1020F000) macro
/lk-master/platform/mediatek/mt6797/include/platform/
A Dmt_reg_base.h132 #define TRNG_BASE (0x1020F000) macro

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