1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : UART 8 // Version : 1 9 // Bus type : apb 10 // Description : None 11 // ============================================================================= 12 #ifndef HARDWARE_REGS_UART_DEFINED 13 #define HARDWARE_REGS_UART_DEFINED 14 // ============================================================================= 15 // Register : UART_UARTDR 16 // Description : Data Register, UARTDR 17 #define UART_UARTDR_OFFSET 0x00000000 18 #define UART_UARTDR_BITS 0x00000fff 19 #define UART_UARTDR_RESET 0x00000000 20 // ----------------------------------------------------------------------------- 21 // Field : UART_UARTDR_OE 22 // Description : Overrun error. This bit is set to 1 if data is received and the 23 // receive FIFO is already full. This is cleared to 0 once there 24 // is an empty space in the FIFO and a new character can be 25 // written to it. 26 #define UART_UARTDR_OE_RESET "-" 27 #define UART_UARTDR_OE_BITS 0x00000800 28 #define UART_UARTDR_OE_MSB 11 29 #define UART_UARTDR_OE_LSB 11 30 #define UART_UARTDR_OE_ACCESS "RO" 31 // ----------------------------------------------------------------------------- 32 // Field : UART_UARTDR_BE 33 // Description : Break error. This bit is set to 1 if a break condition was 34 // detected, indicating that the received data input was held LOW 35 // for longer than a full-word transmission time (defined as 36 // start, data, parity and stop bits). In FIFO mode, this error is 37 // associated with the character at the top of the FIFO. When a 38 // break occurs, only one 0 character is loaded into the FIFO. The 39 // next character is only enabled after the receive data input 40 // goes to a 1 (marking state), and the next valid start bit is 41 // received. 42 #define UART_UARTDR_BE_RESET "-" 43 #define UART_UARTDR_BE_BITS 0x00000400 44 #define UART_UARTDR_BE_MSB 10 45 #define UART_UARTDR_BE_LSB 10 46 #define UART_UARTDR_BE_ACCESS "RO" 47 // ----------------------------------------------------------------------------- 48 // Field : UART_UARTDR_PE 49 // Description : Parity error. When set to 1, it indicates that the parity of 50 // the received data character does not match the parity that the 51 // EPS and SPS bits in the Line Control Register, UARTLCR_H. In 52 // FIFO mode, this error is associated with the character at the 53 // top of the FIFO. 54 #define UART_UARTDR_PE_RESET "-" 55 #define UART_UARTDR_PE_BITS 0x00000200 56 #define UART_UARTDR_PE_MSB 9 57 #define UART_UARTDR_PE_LSB 9 58 #define UART_UARTDR_PE_ACCESS "RO" 59 // ----------------------------------------------------------------------------- 60 // Field : UART_UARTDR_FE 61 // Description : Framing error. When set to 1, it indicates that the received 62 // character did not have a valid stop bit (a valid stop bit is 63 // 1). In FIFO mode, this error is associated with the character 64 // at the top of the FIFO. 65 #define UART_UARTDR_FE_RESET "-" 66 #define UART_UARTDR_FE_BITS 0x00000100 67 #define UART_UARTDR_FE_MSB 8 68 #define UART_UARTDR_FE_LSB 8 69 #define UART_UARTDR_FE_ACCESS "RO" 70 // ----------------------------------------------------------------------------- 71 // Field : UART_UARTDR_DATA 72 // Description : Receive (read) data character. Transmit (write) data character. 73 #define UART_UARTDR_DATA_RESET "-" 74 #define UART_UARTDR_DATA_BITS 0x000000ff 75 #define UART_UARTDR_DATA_MSB 7 76 #define UART_UARTDR_DATA_LSB 0 77 #define UART_UARTDR_DATA_ACCESS "RWF" 78 // ============================================================================= 79 // Register : UART_UARTRSR 80 // Description : Receive Status Register/Error Clear Register, UARTRSR/UARTECR 81 #define UART_UARTRSR_OFFSET 0x00000004 82 #define UART_UARTRSR_BITS 0x0000000f 83 #define UART_UARTRSR_RESET 0x00000000 84 // ----------------------------------------------------------------------------- 85 // Field : UART_UARTRSR_OE 86 // Description : Overrun error. This bit is set to 1 if data is received and the 87 // FIFO is already full. This bit is cleared to 0 by a write to 88 // UARTECR. The FIFO contents remain valid because no more data is 89 // written when the FIFO is full, only the contents of the shift 90 // register are overwritten. The CPU must now read the data, to 91 // empty the FIFO. 92 #define UART_UARTRSR_OE_RESET 0x0 93 #define UART_UARTRSR_OE_BITS 0x00000008 94 #define UART_UARTRSR_OE_MSB 3 95 #define UART_UARTRSR_OE_LSB 3 96 #define UART_UARTRSR_OE_ACCESS "WC" 97 // ----------------------------------------------------------------------------- 98 // Field : UART_UARTRSR_BE 99 // Description : Break error. This bit is set to 1 if a break condition was 100 // detected, indicating that the received data input was held LOW 101 // for longer than a full-word transmission time (defined as 102 // start, data, parity, and stop bits). This bit is cleared to 0 103 // after a write to UARTECR. In FIFO mode, this error is 104 // associated with the character at the top of the FIFO. When a 105 // break occurs, only one 0 character is loaded into the FIFO. The 106 // next character is only enabled after the receive data input 107 // goes to a 1 (marking state) and the next valid start bit is 108 // received. 109 #define UART_UARTRSR_BE_RESET 0x0 110 #define UART_UARTRSR_BE_BITS 0x00000004 111 #define UART_UARTRSR_BE_MSB 2 112 #define UART_UARTRSR_BE_LSB 2 113 #define UART_UARTRSR_BE_ACCESS "WC" 114 // ----------------------------------------------------------------------------- 115 // Field : UART_UARTRSR_PE 116 // Description : Parity error. When set to 1, it indicates that the parity of 117 // the received data character does not match the parity that the 118 // EPS and SPS bits in the Line Control Register, UARTLCR_H. This 119 // bit is cleared to 0 by a write to UARTECR. In FIFO mode, this 120 // error is associated with the character at the top of the FIFO. 121 #define UART_UARTRSR_PE_RESET 0x0 122 #define UART_UARTRSR_PE_BITS 0x00000002 123 #define UART_UARTRSR_PE_MSB 1 124 #define UART_UARTRSR_PE_LSB 1 125 #define UART_UARTRSR_PE_ACCESS "WC" 126 // ----------------------------------------------------------------------------- 127 // Field : UART_UARTRSR_FE 128 // Description : Framing error. When set to 1, it indicates that the received 129 // character did not have a valid stop bit (a valid stop bit is 130 // 1). This bit is cleared to 0 by a write to UARTECR. In FIFO 131 // mode, this error is associated with the character at the top of 132 // the FIFO. 133 #define UART_UARTRSR_FE_RESET 0x0 134 #define UART_UARTRSR_FE_BITS 0x00000001 135 #define UART_UARTRSR_FE_MSB 0 136 #define UART_UARTRSR_FE_LSB 0 137 #define UART_UARTRSR_FE_ACCESS "WC" 138 // ============================================================================= 139 // Register : UART_UARTFR 140 // Description : Flag Register, UARTFR 141 #define UART_UARTFR_OFFSET 0x00000018 142 #define UART_UARTFR_BITS 0x000001ff 143 #define UART_UARTFR_RESET 0x00000090 144 // ----------------------------------------------------------------------------- 145 // Field : UART_UARTFR_RI 146 // Description : Ring indicator. This bit is the complement of the UART ring 147 // indicator, nUARTRI, modem status input. That is, the bit is 1 148 // when nUARTRI is LOW. 149 #define UART_UARTFR_RI_RESET "-" 150 #define UART_UARTFR_RI_BITS 0x00000100 151 #define UART_UARTFR_RI_MSB 8 152 #define UART_UARTFR_RI_LSB 8 153 #define UART_UARTFR_RI_ACCESS "RO" 154 // ----------------------------------------------------------------------------- 155 // Field : UART_UARTFR_TXFE 156 // Description : Transmit FIFO empty. The meaning of this bit depends on the 157 // state of the FEN bit in the Line Control Register, UARTLCR_H. 158 // If the FIFO is disabled, this bit is set when the transmit 159 // holding register is empty. If the FIFO is enabled, the TXFE bit 160 // is set when the transmit FIFO is empty. This bit does not 161 // indicate if there is data in the transmit shift register. 162 #define UART_UARTFR_TXFE_RESET 0x1 163 #define UART_UARTFR_TXFE_BITS 0x00000080 164 #define UART_UARTFR_TXFE_MSB 7 165 #define UART_UARTFR_TXFE_LSB 7 166 #define UART_UARTFR_TXFE_ACCESS "RO" 167 // ----------------------------------------------------------------------------- 168 // Field : UART_UARTFR_RXFF 169 // Description : Receive FIFO full. The meaning of this bit depends on the state 170 // of the FEN bit in the UARTLCR_H Register. If the FIFO is 171 // disabled, this bit is set when the receive holding register is 172 // full. If the FIFO is enabled, the RXFF bit is set when the 173 // receive FIFO is full. 174 #define UART_UARTFR_RXFF_RESET 0x0 175 #define UART_UARTFR_RXFF_BITS 0x00000040 176 #define UART_UARTFR_RXFF_MSB 6 177 #define UART_UARTFR_RXFF_LSB 6 178 #define UART_UARTFR_RXFF_ACCESS "RO" 179 // ----------------------------------------------------------------------------- 180 // Field : UART_UARTFR_TXFF 181 // Description : Transmit FIFO full. The meaning of this bit depends on the 182 // state of the FEN bit in the UARTLCR_H Register. If the FIFO is 183 // disabled, this bit is set when the transmit holding register is 184 // full. If the FIFO is enabled, the TXFF bit is set when the 185 // transmit FIFO is full. 186 #define UART_UARTFR_TXFF_RESET 0x0 187 #define UART_UARTFR_TXFF_BITS 0x00000020 188 #define UART_UARTFR_TXFF_MSB 5 189 #define UART_UARTFR_TXFF_LSB 5 190 #define UART_UARTFR_TXFF_ACCESS "RO" 191 // ----------------------------------------------------------------------------- 192 // Field : UART_UARTFR_RXFE 193 // Description : Receive FIFO empty. The meaning of this bit depends on the 194 // state of the FEN bit in the UARTLCR_H Register. If the FIFO is 195 // disabled, this bit is set when the receive holding register is 196 // empty. If the FIFO is enabled, the RXFE bit is set when the 197 // receive FIFO is empty. 198 #define UART_UARTFR_RXFE_RESET 0x1 199 #define UART_UARTFR_RXFE_BITS 0x00000010 200 #define UART_UARTFR_RXFE_MSB 4 201 #define UART_UARTFR_RXFE_LSB 4 202 #define UART_UARTFR_RXFE_ACCESS "RO" 203 // ----------------------------------------------------------------------------- 204 // Field : UART_UARTFR_BUSY 205 // Description : UART busy. If this bit is set to 1, the UART is busy 206 // transmitting data. This bit remains set until the complete 207 // byte, including all the stop bits, has been sent from the shift 208 // register. This bit is set as soon as the transmit FIFO becomes 209 // non-empty, regardless of whether the UART is enabled or not. 210 #define UART_UARTFR_BUSY_RESET 0x0 211 #define UART_UARTFR_BUSY_BITS 0x00000008 212 #define UART_UARTFR_BUSY_MSB 3 213 #define UART_UARTFR_BUSY_LSB 3 214 #define UART_UARTFR_BUSY_ACCESS "RO" 215 // ----------------------------------------------------------------------------- 216 // Field : UART_UARTFR_DCD 217 // Description : Data carrier detect. This bit is the complement of the UART 218 // data carrier detect, nUARTDCD, modem status input. That is, the 219 // bit is 1 when nUARTDCD is LOW. 220 #define UART_UARTFR_DCD_RESET "-" 221 #define UART_UARTFR_DCD_BITS 0x00000004 222 #define UART_UARTFR_DCD_MSB 2 223 #define UART_UARTFR_DCD_LSB 2 224 #define UART_UARTFR_DCD_ACCESS "RO" 225 // ----------------------------------------------------------------------------- 226 // Field : UART_UARTFR_DSR 227 // Description : Data set ready. This bit is the complement of the UART data set 228 // ready, nUARTDSR, modem status input. That is, the bit is 1 when 229 // nUARTDSR is LOW. 230 #define UART_UARTFR_DSR_RESET "-" 231 #define UART_UARTFR_DSR_BITS 0x00000002 232 #define UART_UARTFR_DSR_MSB 1 233 #define UART_UARTFR_DSR_LSB 1 234 #define UART_UARTFR_DSR_ACCESS "RO" 235 // ----------------------------------------------------------------------------- 236 // Field : UART_UARTFR_CTS 237 // Description : Clear to send. This bit is the complement of the UART clear to 238 // send, nUARTCTS, modem status input. That is, the bit is 1 when 239 // nUARTCTS is LOW. 240 #define UART_UARTFR_CTS_RESET "-" 241 #define UART_UARTFR_CTS_BITS 0x00000001 242 #define UART_UARTFR_CTS_MSB 0 243 #define UART_UARTFR_CTS_LSB 0 244 #define UART_UARTFR_CTS_ACCESS "RO" 245 // ============================================================================= 246 // Register : UART_UARTILPR 247 // Description : IrDA Low-Power Counter Register, UARTILPR 248 #define UART_UARTILPR_OFFSET 0x00000020 249 #define UART_UARTILPR_BITS 0x000000ff 250 #define UART_UARTILPR_RESET 0x00000000 251 // ----------------------------------------------------------------------------- 252 // Field : UART_UARTILPR_ILPDVSR 253 // Description : 8-bit low-power divisor value. These bits are cleared to 0 at 254 // reset. 255 #define UART_UARTILPR_ILPDVSR_RESET 0x00 256 #define UART_UARTILPR_ILPDVSR_BITS 0x000000ff 257 #define UART_UARTILPR_ILPDVSR_MSB 7 258 #define UART_UARTILPR_ILPDVSR_LSB 0 259 #define UART_UARTILPR_ILPDVSR_ACCESS "RW" 260 // ============================================================================= 261 // Register : UART_UARTIBRD 262 // Description : Integer Baud Rate Register, UARTIBRD 263 #define UART_UARTIBRD_OFFSET 0x00000024 264 #define UART_UARTIBRD_BITS 0x0000ffff 265 #define UART_UARTIBRD_RESET 0x00000000 266 // ----------------------------------------------------------------------------- 267 // Field : UART_UARTIBRD_BAUD_DIVINT 268 // Description : The integer baud rate divisor. These bits are cleared to 0 on 269 // reset. 270 #define UART_UARTIBRD_BAUD_DIVINT_RESET 0x0000 271 #define UART_UARTIBRD_BAUD_DIVINT_BITS 0x0000ffff 272 #define UART_UARTIBRD_BAUD_DIVINT_MSB 15 273 #define UART_UARTIBRD_BAUD_DIVINT_LSB 0 274 #define UART_UARTIBRD_BAUD_DIVINT_ACCESS "RW" 275 // ============================================================================= 276 // Register : UART_UARTFBRD 277 // Description : Fractional Baud Rate Register, UARTFBRD 278 #define UART_UARTFBRD_OFFSET 0x00000028 279 #define UART_UARTFBRD_BITS 0x0000003f 280 #define UART_UARTFBRD_RESET 0x00000000 281 // ----------------------------------------------------------------------------- 282 // Field : UART_UARTFBRD_BAUD_DIVFRAC 283 // Description : The fractional baud rate divisor. These bits are cleared to 0 284 // on reset. 285 #define UART_UARTFBRD_BAUD_DIVFRAC_RESET 0x00 286 #define UART_UARTFBRD_BAUD_DIVFRAC_BITS 0x0000003f 287 #define UART_UARTFBRD_BAUD_DIVFRAC_MSB 5 288 #define UART_UARTFBRD_BAUD_DIVFRAC_LSB 0 289 #define UART_UARTFBRD_BAUD_DIVFRAC_ACCESS "RW" 290 // ============================================================================= 291 // Register : UART_UARTLCR_H 292 // Description : Line Control Register, UARTLCR_H 293 #define UART_UARTLCR_H_OFFSET 0x0000002c 294 #define UART_UARTLCR_H_BITS 0x000000ff 295 #define UART_UARTLCR_H_RESET 0x00000000 296 // ----------------------------------------------------------------------------- 297 // Field : UART_UARTLCR_H_SPS 298 // Description : Stick parity select. 0 = stick parity is disabled 1 = either: * 299 // if the EPS bit is 0 then the parity bit is transmitted and 300 // checked as a 1 * if the EPS bit is 1 then the parity bit is 301 // transmitted and checked as a 0. This bit has no effect when the 302 // PEN bit disables parity checking and generation. 303 #define UART_UARTLCR_H_SPS_RESET 0x0 304 #define UART_UARTLCR_H_SPS_BITS 0x00000080 305 #define UART_UARTLCR_H_SPS_MSB 7 306 #define UART_UARTLCR_H_SPS_LSB 7 307 #define UART_UARTLCR_H_SPS_ACCESS "RW" 308 // ----------------------------------------------------------------------------- 309 // Field : UART_UARTLCR_H_WLEN 310 // Description : Word length. These bits indicate the number of data bits 311 // transmitted or received in a frame as follows: b11 = 8 bits b10 312 // = 7 bits b01 = 6 bits b00 = 5 bits. 313 #define UART_UARTLCR_H_WLEN_RESET 0x0 314 #define UART_UARTLCR_H_WLEN_BITS 0x00000060 315 #define UART_UARTLCR_H_WLEN_MSB 6 316 #define UART_UARTLCR_H_WLEN_LSB 5 317 #define UART_UARTLCR_H_WLEN_ACCESS "RW" 318 // ----------------------------------------------------------------------------- 319 // Field : UART_UARTLCR_H_FEN 320 // Description : Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, 321 // the FIFOs become 1-byte-deep holding registers 1 = transmit and 322 // receive FIFO buffers are enabled (FIFO mode). 323 #define UART_UARTLCR_H_FEN_RESET 0x0 324 #define UART_UARTLCR_H_FEN_BITS 0x00000010 325 #define UART_UARTLCR_H_FEN_MSB 4 326 #define UART_UARTLCR_H_FEN_LSB 4 327 #define UART_UARTLCR_H_FEN_ACCESS "RW" 328 // ----------------------------------------------------------------------------- 329 // Field : UART_UARTLCR_H_STP2 330 // Description : Two stop bits select. If this bit is set to 1, two stop bits 331 // are transmitted at the end of the frame. The receive logic does 332 // not check for two stop bits being received. 333 #define UART_UARTLCR_H_STP2_RESET 0x0 334 #define UART_UARTLCR_H_STP2_BITS 0x00000008 335 #define UART_UARTLCR_H_STP2_MSB 3 336 #define UART_UARTLCR_H_STP2_LSB 3 337 #define UART_UARTLCR_H_STP2_ACCESS "RW" 338 // ----------------------------------------------------------------------------- 339 // Field : UART_UARTLCR_H_EPS 340 // Description : Even parity select. Controls the type of parity the UART uses 341 // during transmission and reception: 0 = odd parity. The UART 342 // generates or checks for an odd number of 1s in the data and 343 // parity bits. 1 = even parity. The UART generates or checks for 344 // an even number of 1s in the data and parity bits. This bit has 345 // no effect when the PEN bit disables parity checking and 346 // generation. 347 #define UART_UARTLCR_H_EPS_RESET 0x0 348 #define UART_UARTLCR_H_EPS_BITS 0x00000004 349 #define UART_UARTLCR_H_EPS_MSB 2 350 #define UART_UARTLCR_H_EPS_LSB 2 351 #define UART_UARTLCR_H_EPS_ACCESS "RW" 352 // ----------------------------------------------------------------------------- 353 // Field : UART_UARTLCR_H_PEN 354 // Description : Parity enable: 0 = parity is disabled and no parity bit added 355 // to the data frame 1 = parity checking and generation is 356 // enabled. 357 #define UART_UARTLCR_H_PEN_RESET 0x0 358 #define UART_UARTLCR_H_PEN_BITS 0x00000002 359 #define UART_UARTLCR_H_PEN_MSB 1 360 #define UART_UARTLCR_H_PEN_LSB 1 361 #define UART_UARTLCR_H_PEN_ACCESS "RW" 362 // ----------------------------------------------------------------------------- 363 // Field : UART_UARTLCR_H_BRK 364 // Description : Send break. If this bit is set to 1, a low-level is continually 365 // output on the UARTTXD output, after completing transmission of 366 // the current character. For the proper execution of the break 367 // command, the software must set this bit for at least two 368 // complete frames. For normal use, this bit must be cleared to 0. 369 #define UART_UARTLCR_H_BRK_RESET 0x0 370 #define UART_UARTLCR_H_BRK_BITS 0x00000001 371 #define UART_UARTLCR_H_BRK_MSB 0 372 #define UART_UARTLCR_H_BRK_LSB 0 373 #define UART_UARTLCR_H_BRK_ACCESS "RW" 374 // ============================================================================= 375 // Register : UART_UARTCR 376 // Description : Control Register, UARTCR 377 #define UART_UARTCR_OFFSET 0x00000030 378 #define UART_UARTCR_BITS 0x0000ff87 379 #define UART_UARTCR_RESET 0x00000300 380 // ----------------------------------------------------------------------------- 381 // Field : UART_UARTCR_CTSEN 382 // Description : CTS hardware flow control enable. If this bit is set to 1, CTS 383 // hardware flow control is enabled. Data is only transmitted when 384 // the nUARTCTS signal is asserted. 385 #define UART_UARTCR_CTSEN_RESET 0x0 386 #define UART_UARTCR_CTSEN_BITS 0x00008000 387 #define UART_UARTCR_CTSEN_MSB 15 388 #define UART_UARTCR_CTSEN_LSB 15 389 #define UART_UARTCR_CTSEN_ACCESS "RW" 390 // ----------------------------------------------------------------------------- 391 // Field : UART_UARTCR_RTSEN 392 // Description : RTS hardware flow control enable. If this bit is set to 1, RTS 393 // hardware flow control is enabled. Data is only requested when 394 // there is space in the receive FIFO for it to be received. 395 #define UART_UARTCR_RTSEN_RESET 0x0 396 #define UART_UARTCR_RTSEN_BITS 0x00004000 397 #define UART_UARTCR_RTSEN_MSB 14 398 #define UART_UARTCR_RTSEN_LSB 14 399 #define UART_UARTCR_RTSEN_ACCESS "RW" 400 // ----------------------------------------------------------------------------- 401 // Field : UART_UARTCR_OUT2 402 // Description : This bit is the complement of the UART Out2 (nUARTOut2) modem 403 // status output. That is, when the bit is programmed to a 1, the 404 // output is 0. For DTE this can be used as Ring Indicator (RI). 405 #define UART_UARTCR_OUT2_RESET 0x0 406 #define UART_UARTCR_OUT2_BITS 0x00002000 407 #define UART_UARTCR_OUT2_MSB 13 408 #define UART_UARTCR_OUT2_LSB 13 409 #define UART_UARTCR_OUT2_ACCESS "RW" 410 // ----------------------------------------------------------------------------- 411 // Field : UART_UARTCR_OUT1 412 // Description : This bit is the complement of the UART Out1 (nUARTOut1) modem 413 // status output. That is, when the bit is programmed to a 1 the 414 // output is 0. For DTE this can be used as Data Carrier Detect 415 // (DCD). 416 #define UART_UARTCR_OUT1_RESET 0x0 417 #define UART_UARTCR_OUT1_BITS 0x00001000 418 #define UART_UARTCR_OUT1_MSB 12 419 #define UART_UARTCR_OUT1_LSB 12 420 #define UART_UARTCR_OUT1_ACCESS "RW" 421 // ----------------------------------------------------------------------------- 422 // Field : UART_UARTCR_RTS 423 // Description : Request to send. This bit is the complement of the UART request 424 // to send, nUARTRTS, modem status output. That is, when the bit 425 // is programmed to a 1 then nUARTRTS is LOW. 426 #define UART_UARTCR_RTS_RESET 0x0 427 #define UART_UARTCR_RTS_BITS 0x00000800 428 #define UART_UARTCR_RTS_MSB 11 429 #define UART_UARTCR_RTS_LSB 11 430 #define UART_UARTCR_RTS_ACCESS "RW" 431 // ----------------------------------------------------------------------------- 432 // Field : UART_UARTCR_DTR 433 // Description : Data transmit ready. This bit is the complement of the UART 434 // data transmit ready, nUARTDTR, modem status output. That is, 435 // when the bit is programmed to a 1 then nUARTDTR is LOW. 436 #define UART_UARTCR_DTR_RESET 0x0 437 #define UART_UARTCR_DTR_BITS 0x00000400 438 #define UART_UARTCR_DTR_MSB 10 439 #define UART_UARTCR_DTR_LSB 10 440 #define UART_UARTCR_DTR_ACCESS "RW" 441 // ----------------------------------------------------------------------------- 442 // Field : UART_UARTCR_RXE 443 // Description : Receive enable. If this bit is set to 1, the receive section of 444 // the UART is enabled. Data reception occurs for either UART 445 // signals or SIR signals depending on the setting of the SIREN 446 // bit. When the UART is disabled in the middle of reception, it 447 // completes the current character before stopping. 448 #define UART_UARTCR_RXE_RESET 0x1 449 #define UART_UARTCR_RXE_BITS 0x00000200 450 #define UART_UARTCR_RXE_MSB 9 451 #define UART_UARTCR_RXE_LSB 9 452 #define UART_UARTCR_RXE_ACCESS "RW" 453 // ----------------------------------------------------------------------------- 454 // Field : UART_UARTCR_TXE 455 // Description : Transmit enable. If this bit is set to 1, the transmit section 456 // of the UART is enabled. Data transmission occurs for either 457 // UART signals, or SIR signals depending on the setting of the 458 // SIREN bit. When the UART is disabled in the middle of 459 // transmission, it completes the current character before 460 // stopping. 461 #define UART_UARTCR_TXE_RESET 0x1 462 #define UART_UARTCR_TXE_BITS 0x00000100 463 #define UART_UARTCR_TXE_MSB 8 464 #define UART_UARTCR_TXE_LSB 8 465 #define UART_UARTCR_TXE_ACCESS "RW" 466 // ----------------------------------------------------------------------------- 467 // Field : UART_UARTCR_LBE 468 // Description : Loopback enable. If this bit is set to 1 and the SIREN bit is 469 // set to 1 and the SIRTEST bit in the Test Control Register, 470 // UARTTCR is set to 1, then the nSIROUT path is inverted, and fed 471 // through to the SIRIN path. The SIRTEST bit in the test register 472 // must be set to 1 to override the normal half-duplex SIR 473 // operation. This must be the requirement for accessing the test 474 // registers during normal operation, and SIRTEST must be cleared 475 // to 0 when loopback testing is finished. This feature reduces 476 // the amount of external coupling required during system test. If 477 // this bit is set to 1, and the SIRTEST bit is set to 0, the 478 // UARTTXD path is fed through to the UARTRXD path. In either SIR 479 // mode or UART mode, when this bit is set, the modem outputs are 480 // also fed through to the modem inputs. This bit is cleared to 0 481 // on reset, to disable loopback. 482 #define UART_UARTCR_LBE_RESET 0x0 483 #define UART_UARTCR_LBE_BITS 0x00000080 484 #define UART_UARTCR_LBE_MSB 7 485 #define UART_UARTCR_LBE_LSB 7 486 #define UART_UARTCR_LBE_ACCESS "RW" 487 // ----------------------------------------------------------------------------- 488 // Field : UART_UARTCR_SIRLP 489 // Description : SIR low-power IrDA mode. This bit selects the IrDA encoding 490 // mode. If this bit is cleared to 0, low-level bits are 491 // transmitted as an active high pulse with a width of 3 / 16th of 492 // the bit period. If this bit is set to 1, low-level bits are 493 // transmitted with a pulse width that is 3 times the period of 494 // the IrLPBaud16 input signal, regardless of the selected bit 495 // rate. Setting this bit uses less power, but might reduce 496 // transmission distances. 497 #define UART_UARTCR_SIRLP_RESET 0x0 498 #define UART_UARTCR_SIRLP_BITS 0x00000004 499 #define UART_UARTCR_SIRLP_MSB 2 500 #define UART_UARTCR_SIRLP_LSB 2 501 #define UART_UARTCR_SIRLP_ACCESS "RW" 502 // ----------------------------------------------------------------------------- 503 // Field : UART_UARTCR_SIREN 504 // Description : SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW 505 // (no light pulse generated), and signal transitions on SIRIN 506 // have no effect. 1 = IrDA SIR ENDEC is enabled. Data is 507 // transmitted and received on nSIROUT and SIRIN. UARTTXD remains 508 // HIGH, in the marking state. Signal transitions on UARTRXD or 509 // modem status inputs have no effect. This bit has no effect if 510 // the UARTEN bit disables the UART. 511 #define UART_UARTCR_SIREN_RESET 0x0 512 #define UART_UARTCR_SIREN_BITS 0x00000002 513 #define UART_UARTCR_SIREN_MSB 1 514 #define UART_UARTCR_SIREN_LSB 1 515 #define UART_UARTCR_SIREN_ACCESS "RW" 516 // ----------------------------------------------------------------------------- 517 // Field : UART_UARTCR_UARTEN 518 // Description : UART enable: 0 = UART is disabled. If the UART is disabled in 519 // the middle of transmission or reception, it completes the 520 // current character before stopping. 1 = the UART is enabled. 521 // Data transmission and reception occurs for either UART signals 522 // or SIR signals depending on the setting of the SIREN bit. 523 #define UART_UARTCR_UARTEN_RESET 0x0 524 #define UART_UARTCR_UARTEN_BITS 0x00000001 525 #define UART_UARTCR_UARTEN_MSB 0 526 #define UART_UARTCR_UARTEN_LSB 0 527 #define UART_UARTCR_UARTEN_ACCESS "RW" 528 // ============================================================================= 529 // Register : UART_UARTIFLS 530 // Description : Interrupt FIFO Level Select Register, UARTIFLS 531 #define UART_UARTIFLS_OFFSET 0x00000034 532 #define UART_UARTIFLS_BITS 0x0000003f 533 #define UART_UARTIFLS_RESET 0x00000012 534 // ----------------------------------------------------------------------------- 535 // Field : UART_UARTIFLS_RXIFLSEL 536 // Description : Receive interrupt FIFO level select. The trigger points for the 537 // receive interrupt are as follows: b000 = Receive FIFO becomes 538 // >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = 539 // Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes 540 // >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full 541 // b101-b111 = reserved. 542 #define UART_UARTIFLS_RXIFLSEL_RESET 0x2 543 #define UART_UARTIFLS_RXIFLSEL_BITS 0x00000038 544 #define UART_UARTIFLS_RXIFLSEL_MSB 5 545 #define UART_UARTIFLS_RXIFLSEL_LSB 3 546 #define UART_UARTIFLS_RXIFLSEL_ACCESS "RW" 547 // ----------------------------------------------------------------------------- 548 // Field : UART_UARTIFLS_TXIFLSEL 549 // Description : Transmit interrupt FIFO level select. The trigger points for 550 // the transmit interrupt are as follows: b000 = Transmit FIFO 551 // becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 552 // full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit 553 // FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 554 // 8 full b101-b111 = reserved. 555 #define UART_UARTIFLS_TXIFLSEL_RESET 0x2 556 #define UART_UARTIFLS_TXIFLSEL_BITS 0x00000007 557 #define UART_UARTIFLS_TXIFLSEL_MSB 2 558 #define UART_UARTIFLS_TXIFLSEL_LSB 0 559 #define UART_UARTIFLS_TXIFLSEL_ACCESS "RW" 560 // ============================================================================= 561 // Register : UART_UARTIMSC 562 // Description : Interrupt Mask Set/Clear Register, UARTIMSC 563 #define UART_UARTIMSC_OFFSET 0x00000038 564 #define UART_UARTIMSC_BITS 0x000007ff 565 #define UART_UARTIMSC_RESET 0x00000000 566 // ----------------------------------------------------------------------------- 567 // Field : UART_UARTIMSC_OEIM 568 // Description : Overrun error interrupt mask. A read returns the current mask 569 // for the UARTOEINTR interrupt. On a write of 1, the mask of the 570 // UARTOEINTR interrupt is set. A write of 0 clears the mask. 571 #define UART_UARTIMSC_OEIM_RESET 0x0 572 #define UART_UARTIMSC_OEIM_BITS 0x00000400 573 #define UART_UARTIMSC_OEIM_MSB 10 574 #define UART_UARTIMSC_OEIM_LSB 10 575 #define UART_UARTIMSC_OEIM_ACCESS "RW" 576 // ----------------------------------------------------------------------------- 577 // Field : UART_UARTIMSC_BEIM 578 // Description : Break error interrupt mask. A read returns the current mask for 579 // the UARTBEINTR interrupt. On a write of 1, the mask of the 580 // UARTBEINTR interrupt is set. A write of 0 clears the mask. 581 #define UART_UARTIMSC_BEIM_RESET 0x0 582 #define UART_UARTIMSC_BEIM_BITS 0x00000200 583 #define UART_UARTIMSC_BEIM_MSB 9 584 #define UART_UARTIMSC_BEIM_LSB 9 585 #define UART_UARTIMSC_BEIM_ACCESS "RW" 586 // ----------------------------------------------------------------------------- 587 // Field : UART_UARTIMSC_PEIM 588 // Description : Parity error interrupt mask. A read returns the current mask 589 // for the UARTPEINTR interrupt. On a write of 1, the mask of the 590 // UARTPEINTR interrupt is set. A write of 0 clears the mask. 591 #define UART_UARTIMSC_PEIM_RESET 0x0 592 #define UART_UARTIMSC_PEIM_BITS 0x00000100 593 #define UART_UARTIMSC_PEIM_MSB 8 594 #define UART_UARTIMSC_PEIM_LSB 8 595 #define UART_UARTIMSC_PEIM_ACCESS "RW" 596 // ----------------------------------------------------------------------------- 597 // Field : UART_UARTIMSC_FEIM 598 // Description : Framing error interrupt mask. A read returns the current mask 599 // for the UARTFEINTR interrupt. On a write of 1, the mask of the 600 // UARTFEINTR interrupt is set. A write of 0 clears the mask. 601 #define UART_UARTIMSC_FEIM_RESET 0x0 602 #define UART_UARTIMSC_FEIM_BITS 0x00000080 603 #define UART_UARTIMSC_FEIM_MSB 7 604 #define UART_UARTIMSC_FEIM_LSB 7 605 #define UART_UARTIMSC_FEIM_ACCESS "RW" 606 // ----------------------------------------------------------------------------- 607 // Field : UART_UARTIMSC_RTIM 608 // Description : Receive timeout interrupt mask. A read returns the current mask 609 // for the UARTRTINTR interrupt. On a write of 1, the mask of the 610 // UARTRTINTR interrupt is set. A write of 0 clears the mask. 611 #define UART_UARTIMSC_RTIM_RESET 0x0 612 #define UART_UARTIMSC_RTIM_BITS 0x00000040 613 #define UART_UARTIMSC_RTIM_MSB 6 614 #define UART_UARTIMSC_RTIM_LSB 6 615 #define UART_UARTIMSC_RTIM_ACCESS "RW" 616 // ----------------------------------------------------------------------------- 617 // Field : UART_UARTIMSC_TXIM 618 // Description : Transmit interrupt mask. A read returns the current mask for 619 // the UARTTXINTR interrupt. On a write of 1, the mask of the 620 // UARTTXINTR interrupt is set. A write of 0 clears the mask. 621 #define UART_UARTIMSC_TXIM_RESET 0x0 622 #define UART_UARTIMSC_TXIM_BITS 0x00000020 623 #define UART_UARTIMSC_TXIM_MSB 5 624 #define UART_UARTIMSC_TXIM_LSB 5 625 #define UART_UARTIMSC_TXIM_ACCESS "RW" 626 // ----------------------------------------------------------------------------- 627 // Field : UART_UARTIMSC_RXIM 628 // Description : Receive interrupt mask. A read returns the current mask for the 629 // UARTRXINTR interrupt. On a write of 1, the mask of the 630 // UARTRXINTR interrupt is set. A write of 0 clears the mask. 631 #define UART_UARTIMSC_RXIM_RESET 0x0 632 #define UART_UARTIMSC_RXIM_BITS 0x00000010 633 #define UART_UARTIMSC_RXIM_MSB 4 634 #define UART_UARTIMSC_RXIM_LSB 4 635 #define UART_UARTIMSC_RXIM_ACCESS "RW" 636 // ----------------------------------------------------------------------------- 637 // Field : UART_UARTIMSC_DSRMIM 638 // Description : nUARTDSR modem interrupt mask. A read returns the current mask 639 // for the UARTDSRINTR interrupt. On a write of 1, the mask of the 640 // UARTDSRINTR interrupt is set. A write of 0 clears the mask. 641 #define UART_UARTIMSC_DSRMIM_RESET 0x0 642 #define UART_UARTIMSC_DSRMIM_BITS 0x00000008 643 #define UART_UARTIMSC_DSRMIM_MSB 3 644 #define UART_UARTIMSC_DSRMIM_LSB 3 645 #define UART_UARTIMSC_DSRMIM_ACCESS "RW" 646 // ----------------------------------------------------------------------------- 647 // Field : UART_UARTIMSC_DCDMIM 648 // Description : nUARTDCD modem interrupt mask. A read returns the current mask 649 // for the UARTDCDINTR interrupt. On a write of 1, the mask of the 650 // UARTDCDINTR interrupt is set. A write of 0 clears the mask. 651 #define UART_UARTIMSC_DCDMIM_RESET 0x0 652 #define UART_UARTIMSC_DCDMIM_BITS 0x00000004 653 #define UART_UARTIMSC_DCDMIM_MSB 2 654 #define UART_UARTIMSC_DCDMIM_LSB 2 655 #define UART_UARTIMSC_DCDMIM_ACCESS "RW" 656 // ----------------------------------------------------------------------------- 657 // Field : UART_UARTIMSC_CTSMIM 658 // Description : nUARTCTS modem interrupt mask. A read returns the current mask 659 // for the UARTCTSINTR interrupt. On a write of 1, the mask of the 660 // UARTCTSINTR interrupt is set. A write of 0 clears the mask. 661 #define UART_UARTIMSC_CTSMIM_RESET 0x0 662 #define UART_UARTIMSC_CTSMIM_BITS 0x00000002 663 #define UART_UARTIMSC_CTSMIM_MSB 1 664 #define UART_UARTIMSC_CTSMIM_LSB 1 665 #define UART_UARTIMSC_CTSMIM_ACCESS "RW" 666 // ----------------------------------------------------------------------------- 667 // Field : UART_UARTIMSC_RIMIM 668 // Description : nUARTRI modem interrupt mask. A read returns the current mask 669 // for the UARTRIINTR interrupt. On a write of 1, the mask of the 670 // UARTRIINTR interrupt is set. A write of 0 clears the mask. 671 #define UART_UARTIMSC_RIMIM_RESET 0x0 672 #define UART_UARTIMSC_RIMIM_BITS 0x00000001 673 #define UART_UARTIMSC_RIMIM_MSB 0 674 #define UART_UARTIMSC_RIMIM_LSB 0 675 #define UART_UARTIMSC_RIMIM_ACCESS "RW" 676 // ============================================================================= 677 // Register : UART_UARTRIS 678 // Description : Raw Interrupt Status Register, UARTRIS 679 #define UART_UARTRIS_OFFSET 0x0000003c 680 #define UART_UARTRIS_BITS 0x000007ff 681 #define UART_UARTRIS_RESET 0x00000000 682 // ----------------------------------------------------------------------------- 683 // Field : UART_UARTRIS_OERIS 684 // Description : Overrun error interrupt status. Returns the raw interrupt state 685 // of the UARTOEINTR interrupt. 686 #define UART_UARTRIS_OERIS_RESET 0x0 687 #define UART_UARTRIS_OERIS_BITS 0x00000400 688 #define UART_UARTRIS_OERIS_MSB 10 689 #define UART_UARTRIS_OERIS_LSB 10 690 #define UART_UARTRIS_OERIS_ACCESS "RO" 691 // ----------------------------------------------------------------------------- 692 // Field : UART_UARTRIS_BERIS 693 // Description : Break error interrupt status. Returns the raw interrupt state 694 // of the UARTBEINTR interrupt. 695 #define UART_UARTRIS_BERIS_RESET 0x0 696 #define UART_UARTRIS_BERIS_BITS 0x00000200 697 #define UART_UARTRIS_BERIS_MSB 9 698 #define UART_UARTRIS_BERIS_LSB 9 699 #define UART_UARTRIS_BERIS_ACCESS "RO" 700 // ----------------------------------------------------------------------------- 701 // Field : UART_UARTRIS_PERIS 702 // Description : Parity error interrupt status. Returns the raw interrupt state 703 // of the UARTPEINTR interrupt. 704 #define UART_UARTRIS_PERIS_RESET 0x0 705 #define UART_UARTRIS_PERIS_BITS 0x00000100 706 #define UART_UARTRIS_PERIS_MSB 8 707 #define UART_UARTRIS_PERIS_LSB 8 708 #define UART_UARTRIS_PERIS_ACCESS "RO" 709 // ----------------------------------------------------------------------------- 710 // Field : UART_UARTRIS_FERIS 711 // Description : Framing error interrupt status. Returns the raw interrupt state 712 // of the UARTFEINTR interrupt. 713 #define UART_UARTRIS_FERIS_RESET 0x0 714 #define UART_UARTRIS_FERIS_BITS 0x00000080 715 #define UART_UARTRIS_FERIS_MSB 7 716 #define UART_UARTRIS_FERIS_LSB 7 717 #define UART_UARTRIS_FERIS_ACCESS "RO" 718 // ----------------------------------------------------------------------------- 719 // Field : UART_UARTRIS_RTRIS 720 // Description : Receive timeout interrupt status. Returns the raw interrupt 721 // state of the UARTRTINTR interrupt. a 722 #define UART_UARTRIS_RTRIS_RESET 0x0 723 #define UART_UARTRIS_RTRIS_BITS 0x00000040 724 #define UART_UARTRIS_RTRIS_MSB 6 725 #define UART_UARTRIS_RTRIS_LSB 6 726 #define UART_UARTRIS_RTRIS_ACCESS "RO" 727 // ----------------------------------------------------------------------------- 728 // Field : UART_UARTRIS_TXRIS 729 // Description : Transmit interrupt status. Returns the raw interrupt state of 730 // the UARTTXINTR interrupt. 731 #define UART_UARTRIS_TXRIS_RESET 0x0 732 #define UART_UARTRIS_TXRIS_BITS 0x00000020 733 #define UART_UARTRIS_TXRIS_MSB 5 734 #define UART_UARTRIS_TXRIS_LSB 5 735 #define UART_UARTRIS_TXRIS_ACCESS "RO" 736 // ----------------------------------------------------------------------------- 737 // Field : UART_UARTRIS_RXRIS 738 // Description : Receive interrupt status. Returns the raw interrupt state of 739 // the UARTRXINTR interrupt. 740 #define UART_UARTRIS_RXRIS_RESET 0x0 741 #define UART_UARTRIS_RXRIS_BITS 0x00000010 742 #define UART_UARTRIS_RXRIS_MSB 4 743 #define UART_UARTRIS_RXRIS_LSB 4 744 #define UART_UARTRIS_RXRIS_ACCESS "RO" 745 // ----------------------------------------------------------------------------- 746 // Field : UART_UARTRIS_DSRRMIS 747 // Description : nUARTDSR modem interrupt status. Returns the raw interrupt 748 // state of the UARTDSRINTR interrupt. 749 #define UART_UARTRIS_DSRRMIS_RESET "-" 750 #define UART_UARTRIS_DSRRMIS_BITS 0x00000008 751 #define UART_UARTRIS_DSRRMIS_MSB 3 752 #define UART_UARTRIS_DSRRMIS_LSB 3 753 #define UART_UARTRIS_DSRRMIS_ACCESS "RO" 754 // ----------------------------------------------------------------------------- 755 // Field : UART_UARTRIS_DCDRMIS 756 // Description : nUARTDCD modem interrupt status. Returns the raw interrupt 757 // state of the UARTDCDINTR interrupt. 758 #define UART_UARTRIS_DCDRMIS_RESET "-" 759 #define UART_UARTRIS_DCDRMIS_BITS 0x00000004 760 #define UART_UARTRIS_DCDRMIS_MSB 2 761 #define UART_UARTRIS_DCDRMIS_LSB 2 762 #define UART_UARTRIS_DCDRMIS_ACCESS "RO" 763 // ----------------------------------------------------------------------------- 764 // Field : UART_UARTRIS_CTSRMIS 765 // Description : nUARTCTS modem interrupt status. Returns the raw interrupt 766 // state of the UARTCTSINTR interrupt. 767 #define UART_UARTRIS_CTSRMIS_RESET "-" 768 #define UART_UARTRIS_CTSRMIS_BITS 0x00000002 769 #define UART_UARTRIS_CTSRMIS_MSB 1 770 #define UART_UARTRIS_CTSRMIS_LSB 1 771 #define UART_UARTRIS_CTSRMIS_ACCESS "RO" 772 // ----------------------------------------------------------------------------- 773 // Field : UART_UARTRIS_RIRMIS 774 // Description : nUARTRI modem interrupt status. Returns the raw interrupt state 775 // of the UARTRIINTR interrupt. 776 #define UART_UARTRIS_RIRMIS_RESET "-" 777 #define UART_UARTRIS_RIRMIS_BITS 0x00000001 778 #define UART_UARTRIS_RIRMIS_MSB 0 779 #define UART_UARTRIS_RIRMIS_LSB 0 780 #define UART_UARTRIS_RIRMIS_ACCESS "RO" 781 // ============================================================================= 782 // Register : UART_UARTMIS 783 // Description : Masked Interrupt Status Register, UARTMIS 784 #define UART_UARTMIS_OFFSET 0x00000040 785 #define UART_UARTMIS_BITS 0x000007ff 786 #define UART_UARTMIS_RESET 0x00000000 787 // ----------------------------------------------------------------------------- 788 // Field : UART_UARTMIS_OEMIS 789 // Description : Overrun error masked interrupt status. Returns the masked 790 // interrupt state of the UARTOEINTR interrupt. 791 #define UART_UARTMIS_OEMIS_RESET 0x0 792 #define UART_UARTMIS_OEMIS_BITS 0x00000400 793 #define UART_UARTMIS_OEMIS_MSB 10 794 #define UART_UARTMIS_OEMIS_LSB 10 795 #define UART_UARTMIS_OEMIS_ACCESS "RO" 796 // ----------------------------------------------------------------------------- 797 // Field : UART_UARTMIS_BEMIS 798 // Description : Break error masked interrupt status. Returns the masked 799 // interrupt state of the UARTBEINTR interrupt. 800 #define UART_UARTMIS_BEMIS_RESET 0x0 801 #define UART_UARTMIS_BEMIS_BITS 0x00000200 802 #define UART_UARTMIS_BEMIS_MSB 9 803 #define UART_UARTMIS_BEMIS_LSB 9 804 #define UART_UARTMIS_BEMIS_ACCESS "RO" 805 // ----------------------------------------------------------------------------- 806 // Field : UART_UARTMIS_PEMIS 807 // Description : Parity error masked interrupt status. Returns the masked 808 // interrupt state of the UARTPEINTR interrupt. 809 #define UART_UARTMIS_PEMIS_RESET 0x0 810 #define UART_UARTMIS_PEMIS_BITS 0x00000100 811 #define UART_UARTMIS_PEMIS_MSB 8 812 #define UART_UARTMIS_PEMIS_LSB 8 813 #define UART_UARTMIS_PEMIS_ACCESS "RO" 814 // ----------------------------------------------------------------------------- 815 // Field : UART_UARTMIS_FEMIS 816 // Description : Framing error masked interrupt status. Returns the masked 817 // interrupt state of the UARTFEINTR interrupt. 818 #define UART_UARTMIS_FEMIS_RESET 0x0 819 #define UART_UARTMIS_FEMIS_BITS 0x00000080 820 #define UART_UARTMIS_FEMIS_MSB 7 821 #define UART_UARTMIS_FEMIS_LSB 7 822 #define UART_UARTMIS_FEMIS_ACCESS "RO" 823 // ----------------------------------------------------------------------------- 824 // Field : UART_UARTMIS_RTMIS 825 // Description : Receive timeout masked interrupt status. Returns the masked 826 // interrupt state of the UARTRTINTR interrupt. 827 #define UART_UARTMIS_RTMIS_RESET 0x0 828 #define UART_UARTMIS_RTMIS_BITS 0x00000040 829 #define UART_UARTMIS_RTMIS_MSB 6 830 #define UART_UARTMIS_RTMIS_LSB 6 831 #define UART_UARTMIS_RTMIS_ACCESS "RO" 832 // ----------------------------------------------------------------------------- 833 // Field : UART_UARTMIS_TXMIS 834 // Description : Transmit masked interrupt status. Returns the masked interrupt 835 // state of the UARTTXINTR interrupt. 836 #define UART_UARTMIS_TXMIS_RESET 0x0 837 #define UART_UARTMIS_TXMIS_BITS 0x00000020 838 #define UART_UARTMIS_TXMIS_MSB 5 839 #define UART_UARTMIS_TXMIS_LSB 5 840 #define UART_UARTMIS_TXMIS_ACCESS "RO" 841 // ----------------------------------------------------------------------------- 842 // Field : UART_UARTMIS_RXMIS 843 // Description : Receive masked interrupt status. Returns the masked interrupt 844 // state of the UARTRXINTR interrupt. 845 #define UART_UARTMIS_RXMIS_RESET 0x0 846 #define UART_UARTMIS_RXMIS_BITS 0x00000010 847 #define UART_UARTMIS_RXMIS_MSB 4 848 #define UART_UARTMIS_RXMIS_LSB 4 849 #define UART_UARTMIS_RXMIS_ACCESS "RO" 850 // ----------------------------------------------------------------------------- 851 // Field : UART_UARTMIS_DSRMMIS 852 // Description : nUARTDSR modem masked interrupt status. Returns the masked 853 // interrupt state of the UARTDSRINTR interrupt. 854 #define UART_UARTMIS_DSRMMIS_RESET "-" 855 #define UART_UARTMIS_DSRMMIS_BITS 0x00000008 856 #define UART_UARTMIS_DSRMMIS_MSB 3 857 #define UART_UARTMIS_DSRMMIS_LSB 3 858 #define UART_UARTMIS_DSRMMIS_ACCESS "RO" 859 // ----------------------------------------------------------------------------- 860 // Field : UART_UARTMIS_DCDMMIS 861 // Description : nUARTDCD modem masked interrupt status. Returns the masked 862 // interrupt state of the UARTDCDINTR interrupt. 863 #define UART_UARTMIS_DCDMMIS_RESET "-" 864 #define UART_UARTMIS_DCDMMIS_BITS 0x00000004 865 #define UART_UARTMIS_DCDMMIS_MSB 2 866 #define UART_UARTMIS_DCDMMIS_LSB 2 867 #define UART_UARTMIS_DCDMMIS_ACCESS "RO" 868 // ----------------------------------------------------------------------------- 869 // Field : UART_UARTMIS_CTSMMIS 870 // Description : nUARTCTS modem masked interrupt status. Returns the masked 871 // interrupt state of the UARTCTSINTR interrupt. 872 #define UART_UARTMIS_CTSMMIS_RESET "-" 873 #define UART_UARTMIS_CTSMMIS_BITS 0x00000002 874 #define UART_UARTMIS_CTSMMIS_MSB 1 875 #define UART_UARTMIS_CTSMMIS_LSB 1 876 #define UART_UARTMIS_CTSMMIS_ACCESS "RO" 877 // ----------------------------------------------------------------------------- 878 // Field : UART_UARTMIS_RIMMIS 879 // Description : nUARTRI modem masked interrupt status. Returns the masked 880 // interrupt state of the UARTRIINTR interrupt. 881 #define UART_UARTMIS_RIMMIS_RESET "-" 882 #define UART_UARTMIS_RIMMIS_BITS 0x00000001 883 #define UART_UARTMIS_RIMMIS_MSB 0 884 #define UART_UARTMIS_RIMMIS_LSB 0 885 #define UART_UARTMIS_RIMMIS_ACCESS "RO" 886 // ============================================================================= 887 // Register : UART_UARTICR 888 // Description : Interrupt Clear Register, UARTICR 889 #define UART_UARTICR_OFFSET 0x00000044 890 #define UART_UARTICR_BITS 0x000007ff 891 #define UART_UARTICR_RESET 0x00000000 892 // ----------------------------------------------------------------------------- 893 // Field : UART_UARTICR_OEIC 894 // Description : Overrun error interrupt clear. Clears the UARTOEINTR interrupt. 895 #define UART_UARTICR_OEIC_RESET "-" 896 #define UART_UARTICR_OEIC_BITS 0x00000400 897 #define UART_UARTICR_OEIC_MSB 10 898 #define UART_UARTICR_OEIC_LSB 10 899 #define UART_UARTICR_OEIC_ACCESS "WC" 900 // ----------------------------------------------------------------------------- 901 // Field : UART_UARTICR_BEIC 902 // Description : Break error interrupt clear. Clears the UARTBEINTR interrupt. 903 #define UART_UARTICR_BEIC_RESET "-" 904 #define UART_UARTICR_BEIC_BITS 0x00000200 905 #define UART_UARTICR_BEIC_MSB 9 906 #define UART_UARTICR_BEIC_LSB 9 907 #define UART_UARTICR_BEIC_ACCESS "WC" 908 // ----------------------------------------------------------------------------- 909 // Field : UART_UARTICR_PEIC 910 // Description : Parity error interrupt clear. Clears the UARTPEINTR interrupt. 911 #define UART_UARTICR_PEIC_RESET "-" 912 #define UART_UARTICR_PEIC_BITS 0x00000100 913 #define UART_UARTICR_PEIC_MSB 8 914 #define UART_UARTICR_PEIC_LSB 8 915 #define UART_UARTICR_PEIC_ACCESS "WC" 916 // ----------------------------------------------------------------------------- 917 // Field : UART_UARTICR_FEIC 918 // Description : Framing error interrupt clear. Clears the UARTFEINTR interrupt. 919 #define UART_UARTICR_FEIC_RESET "-" 920 #define UART_UARTICR_FEIC_BITS 0x00000080 921 #define UART_UARTICR_FEIC_MSB 7 922 #define UART_UARTICR_FEIC_LSB 7 923 #define UART_UARTICR_FEIC_ACCESS "WC" 924 // ----------------------------------------------------------------------------- 925 // Field : UART_UARTICR_RTIC 926 // Description : Receive timeout interrupt clear. Clears the UARTRTINTR 927 // interrupt. 928 #define UART_UARTICR_RTIC_RESET "-" 929 #define UART_UARTICR_RTIC_BITS 0x00000040 930 #define UART_UARTICR_RTIC_MSB 6 931 #define UART_UARTICR_RTIC_LSB 6 932 #define UART_UARTICR_RTIC_ACCESS "WC" 933 // ----------------------------------------------------------------------------- 934 // Field : UART_UARTICR_TXIC 935 // Description : Transmit interrupt clear. Clears the UARTTXINTR interrupt. 936 #define UART_UARTICR_TXIC_RESET "-" 937 #define UART_UARTICR_TXIC_BITS 0x00000020 938 #define UART_UARTICR_TXIC_MSB 5 939 #define UART_UARTICR_TXIC_LSB 5 940 #define UART_UARTICR_TXIC_ACCESS "WC" 941 // ----------------------------------------------------------------------------- 942 // Field : UART_UARTICR_RXIC 943 // Description : Receive interrupt clear. Clears the UARTRXINTR interrupt. 944 #define UART_UARTICR_RXIC_RESET "-" 945 #define UART_UARTICR_RXIC_BITS 0x00000010 946 #define UART_UARTICR_RXIC_MSB 4 947 #define UART_UARTICR_RXIC_LSB 4 948 #define UART_UARTICR_RXIC_ACCESS "WC" 949 // ----------------------------------------------------------------------------- 950 // Field : UART_UARTICR_DSRMIC 951 // Description : nUARTDSR modem interrupt clear. Clears the UARTDSRINTR 952 // interrupt. 953 #define UART_UARTICR_DSRMIC_RESET "-" 954 #define UART_UARTICR_DSRMIC_BITS 0x00000008 955 #define UART_UARTICR_DSRMIC_MSB 3 956 #define UART_UARTICR_DSRMIC_LSB 3 957 #define UART_UARTICR_DSRMIC_ACCESS "WC" 958 // ----------------------------------------------------------------------------- 959 // Field : UART_UARTICR_DCDMIC 960 // Description : nUARTDCD modem interrupt clear. Clears the UARTDCDINTR 961 // interrupt. 962 #define UART_UARTICR_DCDMIC_RESET "-" 963 #define UART_UARTICR_DCDMIC_BITS 0x00000004 964 #define UART_UARTICR_DCDMIC_MSB 2 965 #define UART_UARTICR_DCDMIC_LSB 2 966 #define UART_UARTICR_DCDMIC_ACCESS "WC" 967 // ----------------------------------------------------------------------------- 968 // Field : UART_UARTICR_CTSMIC 969 // Description : nUARTCTS modem interrupt clear. Clears the UARTCTSINTR 970 // interrupt. 971 #define UART_UARTICR_CTSMIC_RESET "-" 972 #define UART_UARTICR_CTSMIC_BITS 0x00000002 973 #define UART_UARTICR_CTSMIC_MSB 1 974 #define UART_UARTICR_CTSMIC_LSB 1 975 #define UART_UARTICR_CTSMIC_ACCESS "WC" 976 // ----------------------------------------------------------------------------- 977 // Field : UART_UARTICR_RIMIC 978 // Description : nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. 979 #define UART_UARTICR_RIMIC_RESET "-" 980 #define UART_UARTICR_RIMIC_BITS 0x00000001 981 #define UART_UARTICR_RIMIC_MSB 0 982 #define UART_UARTICR_RIMIC_LSB 0 983 #define UART_UARTICR_RIMIC_ACCESS "WC" 984 // ============================================================================= 985 // Register : UART_UARTDMACR 986 // Description : DMA Control Register, UARTDMACR 987 #define UART_UARTDMACR_OFFSET 0x00000048 988 #define UART_UARTDMACR_BITS 0x00000007 989 #define UART_UARTDMACR_RESET 0x00000000 990 // ----------------------------------------------------------------------------- 991 // Field : UART_UARTDMACR_DMAONERR 992 // Description : DMA on error. If this bit is set to 1, the DMA receive request 993 // outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the 994 // UART error interrupt is asserted. 995 #define UART_UARTDMACR_DMAONERR_RESET 0x0 996 #define UART_UARTDMACR_DMAONERR_BITS 0x00000004 997 #define UART_UARTDMACR_DMAONERR_MSB 2 998 #define UART_UARTDMACR_DMAONERR_LSB 2 999 #define UART_UARTDMACR_DMAONERR_ACCESS "RW" 1000 // ----------------------------------------------------------------------------- 1001 // Field : UART_UARTDMACR_TXDMAE 1002 // Description : Transmit DMA enable. If this bit is set to 1, DMA for the 1003 // transmit FIFO is enabled. 1004 #define UART_UARTDMACR_TXDMAE_RESET 0x0 1005 #define UART_UARTDMACR_TXDMAE_BITS 0x00000002 1006 #define UART_UARTDMACR_TXDMAE_MSB 1 1007 #define UART_UARTDMACR_TXDMAE_LSB 1 1008 #define UART_UARTDMACR_TXDMAE_ACCESS "RW" 1009 // ----------------------------------------------------------------------------- 1010 // Field : UART_UARTDMACR_RXDMAE 1011 // Description : Receive DMA enable. If this bit is set to 1, DMA for the 1012 // receive FIFO is enabled. 1013 #define UART_UARTDMACR_RXDMAE_RESET 0x0 1014 #define UART_UARTDMACR_RXDMAE_BITS 0x00000001 1015 #define UART_UARTDMACR_RXDMAE_MSB 0 1016 #define UART_UARTDMACR_RXDMAE_LSB 0 1017 #define UART_UARTDMACR_RXDMAE_ACCESS "RW" 1018 // ============================================================================= 1019 // Register : UART_UARTPERIPHID0 1020 // Description : UARTPeriphID0 Register 1021 #define UART_UARTPERIPHID0_OFFSET 0x00000fe0 1022 #define UART_UARTPERIPHID0_BITS 0x000000ff 1023 #define UART_UARTPERIPHID0_RESET 0x00000011 1024 // ----------------------------------------------------------------------------- 1025 // Field : UART_UARTPERIPHID0_PARTNUMBER0 1026 // Description : These bits read back as 0x11 1027 #define UART_UARTPERIPHID0_PARTNUMBER0_RESET 0x11 1028 #define UART_UARTPERIPHID0_PARTNUMBER0_BITS 0x000000ff 1029 #define UART_UARTPERIPHID0_PARTNUMBER0_MSB 7 1030 #define UART_UARTPERIPHID0_PARTNUMBER0_LSB 0 1031 #define UART_UARTPERIPHID0_PARTNUMBER0_ACCESS "RO" 1032 // ============================================================================= 1033 // Register : UART_UARTPERIPHID1 1034 // Description : UARTPeriphID1 Register 1035 #define UART_UARTPERIPHID1_OFFSET 0x00000fe4 1036 #define UART_UARTPERIPHID1_BITS 0x000000ff 1037 #define UART_UARTPERIPHID1_RESET 0x00000010 1038 // ----------------------------------------------------------------------------- 1039 // Field : UART_UARTPERIPHID1_DESIGNER0 1040 // Description : These bits read back as 0x1 1041 #define UART_UARTPERIPHID1_DESIGNER0_RESET 0x1 1042 #define UART_UARTPERIPHID1_DESIGNER0_BITS 0x000000f0 1043 #define UART_UARTPERIPHID1_DESIGNER0_MSB 7 1044 #define UART_UARTPERIPHID1_DESIGNER0_LSB 4 1045 #define UART_UARTPERIPHID1_DESIGNER0_ACCESS "RO" 1046 // ----------------------------------------------------------------------------- 1047 // Field : UART_UARTPERIPHID1_PARTNUMBER1 1048 // Description : These bits read back as 0x0 1049 #define UART_UARTPERIPHID1_PARTNUMBER1_RESET 0x0 1050 #define UART_UARTPERIPHID1_PARTNUMBER1_BITS 0x0000000f 1051 #define UART_UARTPERIPHID1_PARTNUMBER1_MSB 3 1052 #define UART_UARTPERIPHID1_PARTNUMBER1_LSB 0 1053 #define UART_UARTPERIPHID1_PARTNUMBER1_ACCESS "RO" 1054 // ============================================================================= 1055 // Register : UART_UARTPERIPHID2 1056 // Description : UARTPeriphID2 Register 1057 #define UART_UARTPERIPHID2_OFFSET 0x00000fe8 1058 #define UART_UARTPERIPHID2_BITS 0x000000ff 1059 #define UART_UARTPERIPHID2_RESET 0x00000034 1060 // ----------------------------------------------------------------------------- 1061 // Field : UART_UARTPERIPHID2_REVISION 1062 // Description : This field depends on the revision of the UART: r1p0 0x0 r1p1 1063 // 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 1064 #define UART_UARTPERIPHID2_REVISION_RESET 0x3 1065 #define UART_UARTPERIPHID2_REVISION_BITS 0x000000f0 1066 #define UART_UARTPERIPHID2_REVISION_MSB 7 1067 #define UART_UARTPERIPHID2_REVISION_LSB 4 1068 #define UART_UARTPERIPHID2_REVISION_ACCESS "RO" 1069 // ----------------------------------------------------------------------------- 1070 // Field : UART_UARTPERIPHID2_DESIGNER1 1071 // Description : These bits read back as 0x4 1072 #define UART_UARTPERIPHID2_DESIGNER1_RESET 0x4 1073 #define UART_UARTPERIPHID2_DESIGNER1_BITS 0x0000000f 1074 #define UART_UARTPERIPHID2_DESIGNER1_MSB 3 1075 #define UART_UARTPERIPHID2_DESIGNER1_LSB 0 1076 #define UART_UARTPERIPHID2_DESIGNER1_ACCESS "RO" 1077 // ============================================================================= 1078 // Register : UART_UARTPERIPHID3 1079 // Description : UARTPeriphID3 Register 1080 #define UART_UARTPERIPHID3_OFFSET 0x00000fec 1081 #define UART_UARTPERIPHID3_BITS 0x000000ff 1082 #define UART_UARTPERIPHID3_RESET 0x00000000 1083 // ----------------------------------------------------------------------------- 1084 // Field : UART_UARTPERIPHID3_CONFIGURATION 1085 // Description : These bits read back as 0x00 1086 #define UART_UARTPERIPHID3_CONFIGURATION_RESET 0x00 1087 #define UART_UARTPERIPHID3_CONFIGURATION_BITS 0x000000ff 1088 #define UART_UARTPERIPHID3_CONFIGURATION_MSB 7 1089 #define UART_UARTPERIPHID3_CONFIGURATION_LSB 0 1090 #define UART_UARTPERIPHID3_CONFIGURATION_ACCESS "RO" 1091 // ============================================================================= 1092 // Register : UART_UARTPCELLID0 1093 // Description : UARTPCellID0 Register 1094 #define UART_UARTPCELLID0_OFFSET 0x00000ff0 1095 #define UART_UARTPCELLID0_BITS 0x000000ff 1096 #define UART_UARTPCELLID0_RESET 0x0000000d 1097 // ----------------------------------------------------------------------------- 1098 // Field : UART_UARTPCELLID0_UARTPCELLID0 1099 // Description : These bits read back as 0x0D 1100 #define UART_UARTPCELLID0_UARTPCELLID0_RESET 0x0d 1101 #define UART_UARTPCELLID0_UARTPCELLID0_BITS 0x000000ff 1102 #define UART_UARTPCELLID0_UARTPCELLID0_MSB 7 1103 #define UART_UARTPCELLID0_UARTPCELLID0_LSB 0 1104 #define UART_UARTPCELLID0_UARTPCELLID0_ACCESS "RO" 1105 // ============================================================================= 1106 // Register : UART_UARTPCELLID1 1107 // Description : UARTPCellID1 Register 1108 #define UART_UARTPCELLID1_OFFSET 0x00000ff4 1109 #define UART_UARTPCELLID1_BITS 0x000000ff 1110 #define UART_UARTPCELLID1_RESET 0x000000f0 1111 // ----------------------------------------------------------------------------- 1112 // Field : UART_UARTPCELLID1_UARTPCELLID1 1113 // Description : These bits read back as 0xF0 1114 #define UART_UARTPCELLID1_UARTPCELLID1_RESET 0xf0 1115 #define UART_UARTPCELLID1_UARTPCELLID1_BITS 0x000000ff 1116 #define UART_UARTPCELLID1_UARTPCELLID1_MSB 7 1117 #define UART_UARTPCELLID1_UARTPCELLID1_LSB 0 1118 #define UART_UARTPCELLID1_UARTPCELLID1_ACCESS "RO" 1119 // ============================================================================= 1120 // Register : UART_UARTPCELLID2 1121 // Description : UARTPCellID2 Register 1122 #define UART_UARTPCELLID2_OFFSET 0x00000ff8 1123 #define UART_UARTPCELLID2_BITS 0x000000ff 1124 #define UART_UARTPCELLID2_RESET 0x00000005 1125 // ----------------------------------------------------------------------------- 1126 // Field : UART_UARTPCELLID2_UARTPCELLID2 1127 // Description : These bits read back as 0x05 1128 #define UART_UARTPCELLID2_UARTPCELLID2_RESET 0x05 1129 #define UART_UARTPCELLID2_UARTPCELLID2_BITS 0x000000ff 1130 #define UART_UARTPCELLID2_UARTPCELLID2_MSB 7 1131 #define UART_UARTPCELLID2_UARTPCELLID2_LSB 0 1132 #define UART_UARTPCELLID2_UARTPCELLID2_ACCESS "RO" 1133 // ============================================================================= 1134 // Register : UART_UARTPCELLID3 1135 // Description : UARTPCellID3 Register 1136 #define UART_UARTPCELLID3_OFFSET 0x00000ffc 1137 #define UART_UARTPCELLID3_BITS 0x000000ff 1138 #define UART_UARTPCELLID3_RESET 0x000000b1 1139 // ----------------------------------------------------------------------------- 1140 // Field : UART_UARTPCELLID3_UARTPCELLID3 1141 // Description : These bits read back as 0xB1 1142 #define UART_UARTPCELLID3_UARTPCELLID3_RESET 0xb1 1143 #define UART_UARTPCELLID3_UARTPCELLID3_BITS 0x000000ff 1144 #define UART_UARTPCELLID3_UARTPCELLID3_MSB 7 1145 #define UART_UARTPCELLID3_UARTPCELLID3_LSB 0 1146 #define UART_UARTPCELLID3_UARTPCELLID3_ACCESS "RO" 1147 // ============================================================================= 1148 #endif // HARDWARE_REGS_UART_DEFINED 1149