1 /* 2 * Copyright (c) 2015 Travis Geiselbrecht 3 * 4 * Use of this source code is governed by a MIT-style 5 * license that can be found in the LICENSE file or at 6 * https://opensource.org/licenses/MIT 7 */ 8 #pragma once 9 10 /* up to 30 GB of ram */ 11 #define MEMORY_BASE_PHYS (0x40000000) 12 #if ARCH_ARM64 13 #define MEMORY_APERTURE_SIZE (30ULL * 1024 * 1024 * 1024) 14 #else 15 #define MEMORY_APERTURE_SIZE (1UL * 1024 * 1024 * 1024) 16 #endif 17 18 /* memory map of peripherals, from qemu hw/arm/virt.c */ 19 #if 0 20 static const MemMapEntry base_memmap[] = { 21 /* Space up to 0x8000000 is reserved for a boot ROM */ 22 [VIRT_FLASH] = { 0, 0x08000000 }, 23 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 24 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 25 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 26 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 27 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 28 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 29 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 30 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 31 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 32 /* This redistributor space allows up to 2*64kB*123 CPUs */ 33 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 34 [VIRT_UART] = { 0x09000000, 0x00001000 }, 35 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 36 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 37 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 38 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 39 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 40 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 41 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 42 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 43 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 44 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 45 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 46 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 47 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 48 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 49 /* Actual RAM size depends on initial RAM and device memory settings */ 50 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 51 }; 52 53 static const int a15irqmap[] = { 54 [VIRT_UART] = 1, 55 [VIRT_RTC] = 2, 56 [VIRT_PCIE] = 3, /* ... to 6 */ 57 [VIRT_GPIO] = 7, 58 [VIRT_SECURE_UART] = 8, 59 [VIRT_ACPI_GED] = 9, 60 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 61 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 62 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 63 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 64 }; 65 #endif 66 67 /* map all of 0-1GB into kernel space in one shot */ 68 #define PERIPHERAL_BASE_PHYS (0) 69 #define PERIPHERAL_BASE_SIZE (0x40000000UL) // 1GB 70 71 #if ARCH_ARM64 72 #define PERIPHERAL_BASE_VIRT (0xffffffffc0000000ULL) // -1GB 73 #else 74 #define PERIPHERAL_BASE_VIRT (0xc0000000UL) // -1GB 75 #endif 76 77 /* individual peripherals in this mapping */ 78 #define FLASH_BASE_VIRT (PERIPHERAL_BASE_VIRT + 0) 79 #define FLASH_SIZE (0x08000000) 80 #define CPUPRIV_BASE_VIRT (PERIPHERAL_BASE_VIRT + 0x08000000) 81 #define CPUPRIV_BASE_PHYS (PERIPHERAL_BASE_PHYS + 0x08000000) 82 #define CPUPRIV_SIZE (0x00020000) 83 #define UART_BASE (PERIPHERAL_BASE_VIRT + 0x09000000) 84 #define UART_SIZE (0x00001000) 85 #define RTC_BASE (PERIPHERAL_BASE_VIRT + 0x09010000) 86 #define RTC_SIZE (0x00001000) 87 #define FW_CFG_BASE (PERIPHERAL_BASE_VIRT + 0x09020000) 88 #define FW_CFG_SIZE (0x00001000) 89 #define NUM_VIRTIO_TRANSPORTS 32 90 #define VIRTIO_BASE (PERIPHERAL_BASE_VIRT + 0x0a000000) 91 #define VIRTIO_SIZE (NUM_VIRTIO_TRANSPORTS * 0x200) 92 93 /* interrupts */ 94 #define ARM_GENERIC_TIMER_VIRTUAL_INT 27 95 #define ARM_GENERIC_TIMER_PHYSICAL_INT 30 96 #define UART0_INT (32 + 1) 97 #define VIRTIO0_INT (32 + 16) 98 99 #define MAX_INT 128 100 101