1 /* 2 * Copyright (c) 2021 Travis Geiselbrecht 3 * 4 * Use of this source code is governed by a MIT-style 5 * license that can be found in the LICENSE file or at 6 * https://opensource.org/licenses/MIT 7 */ 8 #pragma once 9 10 // Top level #defines for the 68k-virt machine in qemu 6.0 11 // 12 // From qemu/hw/m68k/virt.c 13 14 /* 15 * 6 goldfish-pic for CPU IRQ #1 to IRQ #6 16 * CPU IRQ #1 -> PIC #1 17 * IRQ #1 to IRQ #31 -> unused 18 * IRQ #32 -> goldfish-tty 19 * CPU IRQ #2 -> PIC #2 20 * IRQ #1 to IRQ #32 -> virtio-mmio from 1 to 32 21 * CPU IRQ #3 -> PIC #3 22 * IRQ #1 to IRQ #32 -> virtio-mmio from 33 to 64 23 * CPU IRQ #4 -> PIC #4 24 * IRQ #1 to IRQ #32 -> virtio-mmio from 65 to 96 25 * CPU IRQ #5 -> PIC #5 26 * IRQ #1 to IRQ #32 -> virtio-mmio from 97 to 128 27 * CPU IRQ #6 -> PIC #6 28 * IRQ #1 -> goldfish-rtc 29 * IRQ #2 to IRQ #32 -> unused 30 * CPU IRQ #7 -> NMI 31 */ 32 #define NUM_PICS 6 33 #define NUM_IRQS (NUM_PICS * 32) // PIC 1 - 6 34 35 #define PIC_IRQ_TO_LINEAR(pic, irq) (((pic) - 1) * 32 + ((irq) - 1)) 36 #define GOLDFISH_TTY_IRQ PIC_IRQ_TO_LINEAR(1, 32) // PIC 1, irq 32 37 #define GOLDFISH_RTC_IRQ PIC_IRQ_TO_LINEAR(6, 1) // PIC 6, irq 1 38 39 //#define PIC_IRQ_BASE(num) (8 + (num - 1) * 32) 40 //#define PIC_IRQ(num, irq) (PIC_IRQ_BASE(num) + irq - 1) 41 //#define PIC_GPIO(pic_irq) (qdev_get_gpio_in(pic_dev[(pic_irq - 8) / 32], (pic_irq - 8) % 32)) 42 43 #define VIRT_GF_PIC_MMIO_BASE 0xff000000 /* MMIO: 0xff000000 - 0xff005fff */ 44 #define VIRT_GF_PIC_IRQ_BASE 1 /* IRQ: #1 -> #6 */ 45 #define VIRT_GF_PIC_NB 6 46 47 /* 2 goldfish-rtc (and timer) */ 48 #define VIRT_GF_RTC_MMIO_BASE 0xff006000 /* MMIO: 0xff006000 - 0xff007fff */ 49 #define VIRT_GF_RTC_IRQ_BASE PIC_IRQ(6, 1) /* PIC: #6, IRQ: #1 */ 50 #define VIRT_GF_RTC_NB 2 51 52 /* 1 goldfish-tty */ 53 #define VIRT_GF_TTY_MMIO_BASE 0xff008000 /* MMIO: 0xff008000 - 0xff008fff */ 54 #define VIRT_GF_TTY_IRQ_BASE PIC_IRQ(1, 32) /* PIC: #1, IRQ: #32 */ 55 56 /* 1 virt-ctrl */ 57 #define VIRT_CTRL_MMIO_BASE 0xff009000 /* MMIO: 0xff009000 - 0xff009fff */ 58 #define VIRT_CTRL_IRQ_BASE PIC_IRQ(1, 1) /* PIC: #1, IRQ: #1 */ 59 60 /* 61 * virtio-mmio size is 0x200 bytes 62 * we use 4 goldfish-pic to attach them, 63 * we can attach 32 virtio devices / goldfish-pic 64 * -> we can manage 32 * 4 = 128 virtio devices 65 */ 66 #define VIRT_VIRTIO_MMIO_BASE 0xff010000 /* MMIO: 0xff010000 - 0xff01ffff */ 67 #define VIRT_VIRTIO_IRQ_BASE PIC_IRQ(2, 1) /* PIC: 2, 3, 4, 5, IRQ: ALL */ 68