1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : VREG_AND_CHIP_RESET 8 // Version : 1 9 // Bus type : apb 10 // Description : control and status for on-chip voltage regulator and chip 11 // level reset subsystem 12 // ============================================================================= 13 #ifndef HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED 14 #define HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED 15 // ============================================================================= 16 // Register : VREG_AND_CHIP_RESET_VREG 17 // Description : Voltage regulator control and status 18 #define VREG_AND_CHIP_RESET_VREG_OFFSET 0x00000000 19 #define VREG_AND_CHIP_RESET_VREG_BITS 0x000010f3 20 #define VREG_AND_CHIP_RESET_VREG_RESET 0x000000b1 21 // ----------------------------------------------------------------------------- 22 // Field : VREG_AND_CHIP_RESET_VREG_ROK 23 // Description : regulation status 24 // 0=not in regulation, 1=in regulation 25 #define VREG_AND_CHIP_RESET_VREG_ROK_RESET 0x0 26 #define VREG_AND_CHIP_RESET_VREG_ROK_BITS 0x00001000 27 #define VREG_AND_CHIP_RESET_VREG_ROK_MSB 12 28 #define VREG_AND_CHIP_RESET_VREG_ROK_LSB 12 29 #define VREG_AND_CHIP_RESET_VREG_ROK_ACCESS "RO" 30 // ----------------------------------------------------------------------------- 31 // Field : VREG_AND_CHIP_RESET_VREG_VSEL 32 // Description : output voltage select 33 // 0000 to 0101 - 0.80V 34 // 0110 - 0.85V 35 // 0111 - 0.90V 36 // 1000 - 0.95V 37 // 1001 - 1.00V 38 // 1010 - 1.05V 39 // 1011 - 1.10V (default) 40 // 1100 - 1.15V 41 // 1101 - 1.20V 42 // 1110 - 1.25V 43 // 1111 - 1.30V 44 #define VREG_AND_CHIP_RESET_VREG_VSEL_RESET 0xb 45 #define VREG_AND_CHIP_RESET_VREG_VSEL_BITS 0x000000f0 46 #define VREG_AND_CHIP_RESET_VREG_VSEL_MSB 7 47 #define VREG_AND_CHIP_RESET_VREG_VSEL_LSB 4 48 #define VREG_AND_CHIP_RESET_VREG_VSEL_ACCESS "RW" 49 // ----------------------------------------------------------------------------- 50 // Field : VREG_AND_CHIP_RESET_VREG_HIZ 51 // Description : high impedance mode select 52 // 0=not in high impedance mode, 1=in high impedance mode 53 #define VREG_AND_CHIP_RESET_VREG_HIZ_RESET 0x0 54 #define VREG_AND_CHIP_RESET_VREG_HIZ_BITS 0x00000002 55 #define VREG_AND_CHIP_RESET_VREG_HIZ_MSB 1 56 #define VREG_AND_CHIP_RESET_VREG_HIZ_LSB 1 57 #define VREG_AND_CHIP_RESET_VREG_HIZ_ACCESS "RW" 58 // ----------------------------------------------------------------------------- 59 // Field : VREG_AND_CHIP_RESET_VREG_EN 60 // Description : enable 61 // 0=not enabled, 1=enabled 62 #define VREG_AND_CHIP_RESET_VREG_EN_RESET 0x1 63 #define VREG_AND_CHIP_RESET_VREG_EN_BITS 0x00000001 64 #define VREG_AND_CHIP_RESET_VREG_EN_MSB 0 65 #define VREG_AND_CHIP_RESET_VREG_EN_LSB 0 66 #define VREG_AND_CHIP_RESET_VREG_EN_ACCESS "RW" 67 // ============================================================================= 68 // Register : VREG_AND_CHIP_RESET_BOD 69 // Description : brown-out detection control 70 #define VREG_AND_CHIP_RESET_BOD_OFFSET 0x00000004 71 #define VREG_AND_CHIP_RESET_BOD_BITS 0x000000f1 72 #define VREG_AND_CHIP_RESET_BOD_RESET 0x00000091 73 // ----------------------------------------------------------------------------- 74 // Field : VREG_AND_CHIP_RESET_BOD_VSEL 75 // Description : threshold select 76 // 0000 - 0.473V 77 // 0001 - 0.516V 78 // 0010 - 0.559V 79 // 0011 - 0.602V 80 // 0100 - 0.645V 81 // 0101 - 0.688V 82 // 0110 - 0.731V 83 // 0111 - 0.774V 84 // 1000 - 0.817V 85 // 1001 - 0.860V (default) 86 // 1010 - 0.903V 87 // 1011 - 0.946V 88 // 1100 - 0.989V 89 // 1101 - 1.032V 90 // 1110 - 1.075V 91 // 1111 - 1.118V 92 #define VREG_AND_CHIP_RESET_BOD_VSEL_RESET 0x9 93 #define VREG_AND_CHIP_RESET_BOD_VSEL_BITS 0x000000f0 94 #define VREG_AND_CHIP_RESET_BOD_VSEL_MSB 7 95 #define VREG_AND_CHIP_RESET_BOD_VSEL_LSB 4 96 #define VREG_AND_CHIP_RESET_BOD_VSEL_ACCESS "RW" 97 // ----------------------------------------------------------------------------- 98 // Field : VREG_AND_CHIP_RESET_BOD_EN 99 // Description : enable 100 // 0=not enabled, 1=enabled 101 #define VREG_AND_CHIP_RESET_BOD_EN_RESET 0x1 102 #define VREG_AND_CHIP_RESET_BOD_EN_BITS 0x00000001 103 #define VREG_AND_CHIP_RESET_BOD_EN_MSB 0 104 #define VREG_AND_CHIP_RESET_BOD_EN_LSB 0 105 #define VREG_AND_CHIP_RESET_BOD_EN_ACCESS "RW" 106 // ============================================================================= 107 // Register : VREG_AND_CHIP_RESET_CHIP_RESET 108 // Description : Chip reset control and status 109 #define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET 0x00000008 110 #define VREG_AND_CHIP_RESET_CHIP_RESET_BITS 0x01110100 111 #define VREG_AND_CHIP_RESET_CHIP_RESET_RESET 0x00000000 112 // ----------------------------------------------------------------------------- 113 // Field : VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG 114 // Description : This is set by psm_restart from the debugger. 115 // Its purpose is to branch bootcode to a safe mode when the 116 // debugger has issued a psm_restart in order to recover from a 117 // boot lock-up. 118 // In the safe mode the debugger can repair the boot code, clear 119 // this flag then reboot the processor. 120 #define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET 0x0 121 #define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS 0x01000000 122 #define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB 24 123 #define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB 24 124 #define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_ACCESS "WC" 125 // ----------------------------------------------------------------------------- 126 // Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART 127 // Description : Last reset was from the debug port 128 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET 0x0 129 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS 0x00100000 130 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB 20 131 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB 20 132 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_ACCESS "RO" 133 // ----------------------------------------------------------------------------- 134 // Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN 135 // Description : Last reset was from the RUN pin 136 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET 0x0 137 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS 0x00010000 138 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB 16 139 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB 16 140 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_ACCESS "RO" 141 // ----------------------------------------------------------------------------- 142 // Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR 143 // Description : Last reset was from the power-on reset or brown-out detection 144 // blocks 145 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET 0x0 146 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS 0x00000100 147 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB 8 148 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB 8 149 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO" 150 // ============================================================================= 151 #endif // HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED 152