1 /****************************************************************************** 2 * Filename: hw_wdt_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_WDT_H__ 38 #define __HW_WDT_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // WDT component 44 // 45 //***************************************************************************** 46 // Configuration 47 #define WDT_O_LOAD 0x00000000 48 49 // Current Count Value 50 #define WDT_O_VALUE 0x00000004 51 52 // Control 53 #define WDT_O_CTL 0x00000008 54 55 // Interrupt Clear 56 #define WDT_O_ICR 0x0000000C 57 58 // Raw Interrupt Status 59 #define WDT_O_RIS 0x00000010 60 61 // Masked Interrupt Status 62 #define WDT_O_MIS 0x00000014 63 64 // Test Mode 65 #define WDT_O_TEST 0x00000418 66 67 // Interrupt Cause Test Mode 68 #define WDT_O_INT_CAUS 0x0000041C 69 70 // Lock 71 #define WDT_O_LOCK 0x00000C00 72 73 //***************************************************************************** 74 // 75 // Register: WDT_O_LOAD 76 // 77 //***************************************************************************** 78 // Field: [31:0] WDTLOAD 79 // 80 // This register is the 32-bit interval value used by the 32-bit counter. When 81 // this register is written, the value is immediately loaded and the counter is 82 // restarted to count down from the new value. If this register is loaded with 83 // 0x0000.0000, an interrupt is immediately generated. 84 #define WDT_LOAD_WDTLOAD_W 32 85 #define WDT_LOAD_WDTLOAD_M 0xFFFFFFFF 86 #define WDT_LOAD_WDTLOAD_S 0 87 88 //***************************************************************************** 89 // 90 // Register: WDT_O_VALUE 91 // 92 //***************************************************************************** 93 // Field: [31:0] WDTVALUE 94 // 95 // This register contains the current count value of the timer. 96 #define WDT_VALUE_WDTVALUE_W 32 97 #define WDT_VALUE_WDTVALUE_M 0xFFFFFFFF 98 #define WDT_VALUE_WDTVALUE_S 0 99 100 //***************************************************************************** 101 // 102 // Register: WDT_O_CTL 103 // 104 //***************************************************************************** 105 // Field: [2] INTTYPE 106 // 107 // WDT Interrupt Type 108 // 109 // 0: WDT interrupt is a standard interrupt. 110 // 1: WDT interrupt is a non-maskable interrupt. 111 // ENUMs: 112 // NONMASKABLE Non-maskable interrupt 113 // MASKABLE Maskable interrupt 114 #define WDT_CTL_INTTYPE 0x00000004 115 #define WDT_CTL_INTTYPE_BITN 2 116 #define WDT_CTL_INTTYPE_M 0x00000004 117 #define WDT_CTL_INTTYPE_S 2 118 #define WDT_CTL_INTTYPE_NONMASKABLE 0x00000004 119 #define WDT_CTL_INTTYPE_MASKABLE 0x00000000 120 121 // Field: [1] RESEN 122 // 123 // WDT Reset Enable. Defines the function of the WDT reset source (see 124 // PRCM:WARMRESET.WDT_STAT if enabled) 125 // 126 // 0: Disabled. 127 // 1: Enable the Watchdog reset output. 128 // ENUMs: 129 // EN Reset output Enabled 130 // DIS Reset output Disabled 131 #define WDT_CTL_RESEN 0x00000002 132 #define WDT_CTL_RESEN_BITN 1 133 #define WDT_CTL_RESEN_M 0x00000002 134 #define WDT_CTL_RESEN_S 1 135 #define WDT_CTL_RESEN_EN 0x00000002 136 #define WDT_CTL_RESEN_DIS 0x00000000 137 138 // Field: [0] INTEN 139 // 140 // WDT Interrupt Enable 141 // 142 // 0: Interrupt event disabled. 143 // 1: Interrupt event enabled. Once set, this bit can only be cleared by a 144 // hardware reset. 145 // ENUMs: 146 // EN Interrupt Enabled 147 // DIS Interrupt Disabled 148 #define WDT_CTL_INTEN 0x00000001 149 #define WDT_CTL_INTEN_BITN 0 150 #define WDT_CTL_INTEN_M 0x00000001 151 #define WDT_CTL_INTEN_S 0 152 #define WDT_CTL_INTEN_EN 0x00000001 153 #define WDT_CTL_INTEN_DIS 0x00000000 154 155 //***************************************************************************** 156 // 157 // Register: WDT_O_ICR 158 // 159 //***************************************************************************** 160 // Field: [31:0] WDTICR 161 // 162 // This register is the interrupt clear register. A write of any value to this 163 // register clears the WDT interrupt and reloads the 32-bit counter from the 164 // LOAD register. 165 #define WDT_ICR_WDTICR_W 32 166 #define WDT_ICR_WDTICR_M 0xFFFFFFFF 167 #define WDT_ICR_WDTICR_S 0 168 169 //***************************************************************************** 170 // 171 // Register: WDT_O_RIS 172 // 173 //***************************************************************************** 174 // Field: [0] WDTRIS 175 // 176 // This register is the raw interrupt status register. WDT interrupt events can 177 // be monitored via this register if the controller interrupt is masked. 178 // 179 // Value Description 180 // 181 // 0: The WDT has not timed out 182 // 1: A WDT time-out event has occurred 183 // 184 #define WDT_RIS_WDTRIS 0x00000001 185 #define WDT_RIS_WDTRIS_BITN 0 186 #define WDT_RIS_WDTRIS_M 0x00000001 187 #define WDT_RIS_WDTRIS_S 0 188 189 //***************************************************************************** 190 // 191 // Register: WDT_O_MIS 192 // 193 //***************************************************************************** 194 // Field: [0] WDTMIS 195 // 196 // This register is the masked interrupt status register. The value of this 197 // register is the logical AND of the raw interrupt bit and the WDT interrupt 198 // enable bit CTL.INTEN. 199 // 200 // Value Description 201 // 202 // 0: The WDT has not timed out or is masked. 203 // 1: An unmasked WDT time-out event has occurred. 204 #define WDT_MIS_WDTMIS 0x00000001 205 #define WDT_MIS_WDTMIS_BITN 0 206 #define WDT_MIS_WDTMIS_M 0x00000001 207 #define WDT_MIS_WDTMIS_S 0 208 209 //***************************************************************************** 210 // 211 // Register: WDT_O_TEST 212 // 213 //***************************************************************************** 214 // Field: [8] STALL 215 // 216 // WDT Stall Enable 217 // 218 // 0: The WDT timer continues counting if the CPU is stopped with a debugger. 219 // 1: If the CPU is stopped with a debugger, the WDT stops counting. Once the 220 // CPU is restarted, the WDT resumes counting. 221 // ENUMs: 222 // EN Enable STALL 223 // DIS Disable STALL 224 #define WDT_TEST_STALL 0x00000100 225 #define WDT_TEST_STALL_BITN 8 226 #define WDT_TEST_STALL_M 0x00000100 227 #define WDT_TEST_STALL_S 8 228 #define WDT_TEST_STALL_EN 0x00000100 229 #define WDT_TEST_STALL_DIS 0x00000000 230 231 // Field: [0] TEST_EN 232 // 233 // The test enable bit 234 // 235 // 0: Enable external reset 236 // 1: Disables the generation of an external reset. Instead bit 1 of the 237 // INT_CAUS register is set and an interrupt is generated 238 // ENUMs: 239 // EN Test mode Enabled 240 // DIS Test mode Disabled 241 #define WDT_TEST_TEST_EN 0x00000001 242 #define WDT_TEST_TEST_EN_BITN 0 243 #define WDT_TEST_TEST_EN_M 0x00000001 244 #define WDT_TEST_TEST_EN_S 0 245 #define WDT_TEST_TEST_EN_EN 0x00000001 246 #define WDT_TEST_TEST_EN_DIS 0x00000000 247 248 //***************************************************************************** 249 // 250 // Register: WDT_O_INT_CAUS 251 // 252 //***************************************************************************** 253 // Field: [1] CAUSE_RESET 254 // 255 // Indicates that the cause of an interrupt was a reset generated but blocked 256 // due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). 257 #define WDT_INT_CAUS_CAUSE_RESET 0x00000002 258 #define WDT_INT_CAUS_CAUSE_RESET_BITN 1 259 #define WDT_INT_CAUS_CAUSE_RESET_M 0x00000002 260 #define WDT_INT_CAUS_CAUSE_RESET_S 1 261 262 // Field: [0] CAUSE_INTR 263 // 264 // Replica of RIS.WDTRIS 265 #define WDT_INT_CAUS_CAUSE_INTR 0x00000001 266 #define WDT_INT_CAUS_CAUSE_INTR_BITN 0 267 #define WDT_INT_CAUS_CAUSE_INTR_M 0x00000001 268 #define WDT_INT_CAUS_CAUSE_INTR_S 0 269 270 //***************************************************************************** 271 // 272 // Register: WDT_O_LOCK 273 // 274 //***************************************************************************** 275 // Field: [31:0] WDTLOCK 276 // 277 // WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog registers 278 // for write access. A write of any other value reapplies the lock, preventing 279 // any register updates (NOTE: TEST.TEST_EN bit is not lockable). 280 // 281 // A read of this register returns the following values: 282 // 283 // 0x0000.0000: Unlocked 284 // 0x0000.0001: Locked 285 #define WDT_LOCK_WDTLOCK_W 32 286 #define WDT_LOCK_WDTLOCK_M 0xFFFFFFFF 287 #define WDT_LOCK_WDTLOCK_S 0 288 289 290 #endif // __WDT__ 291