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Searched refs:WRITE_REG (Results 1 – 25 of 43) sorted by relevance

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/lk-master/external/platform/stm32f0xx/STM32F0xx_HAL_Driver/inc/
A Dstm32f0xx_ll_iwdg.h128 #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALU…
163 WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE); in LL_IWDG_Enable()
174 WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD); in LL_IWDG_ReloadCounter()
185 WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); in LL_IWDG_EnableWriteAccess()
196 WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); in LL_IWDG_DisableWriteAccess()
215 WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); in LL_IWDG_SetPrescaler()
245 WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); in LL_IWDG_SetReloadCounter()
268 WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window); in LL_IWDG_SetWindow()
A Dstm32f0xx_ll_dma.h1689 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); in LL_DMA_ClearFlag_GI1()
1700 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); in LL_DMA_ClearFlag_GI2()
1711 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); in LL_DMA_ClearFlag_GI3()
1722 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); in LL_DMA_ClearFlag_GI4()
1733 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); in LL_DMA_ClearFlag_GI5()
1745 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); in LL_DMA_ClearFlag_GI6()
1758 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); in LL_DMA_ClearFlag_GI7()
1770 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); in LL_DMA_ClearFlag_TC1()
1781 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); in LL_DMA_ClearFlag_TC2()
1792 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); in LL_DMA_ClearFlag_TC3()
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A Dstm32f0xx_hal_iwdg.h132 #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_…
140 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_…
200 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_…
207 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_…
A Dstm32f0xx_ll_gpio.h228 #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALU…
684 WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); in LL_GPIO_LockPin()
685 WRITE_REG(GPIOx->LCKR, PinMask); in LL_GPIO_LockPin()
686 WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); in LL_GPIO_LockPin()
788 WRITE_REG(GPIOx->ODR, PortValue); in LL_GPIO_WriteOutputPort()
857 WRITE_REG(GPIOx->BSRR, PinMask); in LL_GPIO_SetOutputPin()
886 WRITE_REG(GPIOx->BRR, PinMask); in LL_GPIO_ResetOutputPin()
915 WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); in LL_GPIO_TogglePin()
A Dstm32f0xx_ll_crc.h141 #define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE…
289 WRITE_REG(CRCx->INIT, InitCrc); in LL_CRC_SetInitialData()
322 WRITE_REG(CRCx->POL, PolynomCoef); in LL_CRC_SetPolynomialCoef()
359 WRITE_REG(CRCx->DR, InData); in LL_CRC_FeedData32()
A Dstm32f0xx_ll_crs.h184 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE…
601 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); in LL_CRS_ClearFlag_SYNCOK()
611 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); in LL_CRS_ClearFlag_SYNCWARN()
622 WRITE_REG(CRS->ICR, CRS_ICR_ERRC); in LL_CRS_ClearFlag_ERR()
632 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); in LL_CRS_ClearFlag_ESYNC()
A Dstm32f0xx_ll_tim.h1286 WRITE_REG(TIMx->CNT, Counter); in LL_TIM_SetCounter()
1328 WRITE_REG(TIMx->PSC, Prescaler); in LL_TIM_SetPrescaler()
1355 WRITE_REG(TIMx->ARR, AutoReload); in LL_TIM_SetAutoReload()
2025 WRITE_REG(TIMx->CCR1, CompareValue); in LL_TIM_OC_SetCompareCH1()
2042 WRITE_REG(TIMx->CCR2, CompareValue); in LL_TIM_OC_SetCompareCH2()
2059 WRITE_REG(TIMx->CCR3, CompareValue); in LL_TIM_OC_SetCompareCH3()
2076 WRITE_REG(TIMx->CCR4, CompareValue); in LL_TIM_OC_SetCompareCH4()
3058 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); in LL_TIM_ClearFlag_UPDATE()
3080 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); in LL_TIM_ClearFlag_CC1()
3190 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); in LL_TIM_ClearFlag_TRIG()
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A Dstm32f0xx_ll_wwdg.h109 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALU…
282 WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF); in LL_WWDG_ClearFlag_EWKUP()
A Dstm32f0xx_ll_rtc.h593 #define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE…
901 WRITE_REG(RTCx->ISR, RTC_INIT_MASK); in LL_RTC_EnableInitMode()
913 WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT); in LL_RTC_DisableInitMode()
1058 WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE); in LL_RTC_EnableWriteProtection()
1069 WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1); in LL_RTC_DisableWriteProtection()
1070 WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); in LL_RTC_DisableWriteProtection()
1380 WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction); in LL_RTC_TIME_Synchronize()
2900 …WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)… in LL_RTC_ClearFlag_TSOV()
2911 …WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); in LL_RTC_ClearFlag_TS()
2923 …WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))… in LL_RTC_ClearFlag_WUT()
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A Dstm32f0xx_ll_usart.h2927 WRITE_REG(USARTx->ICR, USART_ICR_PECF); in LL_USART_ClearFlag_PE()
2938 WRITE_REG(USARTx->ICR, USART_ICR_FECF); in LL_USART_ClearFlag_FE()
2949 WRITE_REG(USARTx->ICR, USART_ICR_NCF); in LL_USART_ClearFlag_NE()
2960 WRITE_REG(USARTx->ICR, USART_ICR_ORECF); in LL_USART_ClearFlag_ORE()
2982 WRITE_REG(USARTx->ICR, USART_ICR_TCCF); in LL_USART_ClearFlag_TC()
2997 WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); in LL_USART_ClearFlag_LBD()
3011 WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); in LL_USART_ClearFlag_nCTS()
3022 WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); in LL_USART_ClearFlag_RTO()
3036 WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); in LL_USART_ClearFlag_EOB()
3048 WRITE_REG(USARTx->ICR, USART_ICR_CMCF); in LL_USART_ClearFlag_CM()
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A Dstm32f0xx_ll_exti.h220 #define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
989 WRITE_REG(EXTI->PR, ExtiLine); in LL_EXTI_ClearFlag_0_31()
A Dstm32f0xx_ll_i2c.h353 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE…
902 WRITE_REG(I2Cx->TIMINGR, Timing); in LL_I2C_SetTiming()
1120 WRITE_REG(I2Cx->TIMEOUTR, TimeoutA); in LL_I2C_SetSMBusTimeoutA()
1150 WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode); in LL_I2C_SetSMBusTimeoutAMode()
1180 WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); in LL_I2C_SetSMBusTimeoutB()
1765 WRITE_REG(I2Cx->ISR, I2C_ISR_TXE); in LL_I2C_ClearFlag_TXE()
2204 WRITE_REG(I2Cx->TXDR, Data); in LL_I2C_TransmitData8()
A Dstm32f0xx_ll_adc.h684 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE…
2092 WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); in LL_ADC_REG_SetSequencerChannels()
3104 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY); in LL_ADC_ClearFlag_ADRDY()
3115 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC); in LL_ADC_ClearFlag_EOC()
3126 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS); in LL_ADC_ClearFlag_EOS()
3137 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR); in LL_ADC_ClearFlag_OVR()
3148 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP); in LL_ADC_ClearFlag_EOSMP()
3159 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1); in LL_ADC_ClearFlag_AWD1()
/lk-master/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Inc/
A Dstm32f7xx_hal_iwdg.h154 #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_…
162 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_…
250 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_…
257 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_…
/lk-master/external/platform/stm32f0xx/STM32F0xx_HAL_Driver/
A Dstm32f0xx_hal_wwdg.c191 WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); in HAL_WWDG_Init()
194 …WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window)… in HAL_WWDG_Init()
249 WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter)); in HAL_WWDG_Refresh()
A Dstm32f0xx_hal_flash.c502 WRITE_REG(FLASH->KEYR, FLASH_KEY1); in HAL_FLASH_Unlock()
503 WRITE_REG(FLASH->KEYR, FLASH_KEY2); in HAL_FLASH_Unlock()
536 WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); in HAL_FLASH_OB_Unlock()
537 WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); in HAL_FLASH_OB_Unlock()
A Dstm32f0xx_hal_crc_ex.c109 WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); in HAL_CRCEx_Init()
241 WRITE_REG(hcrc->Instance->POL, Pol); in HAL_CRCEx_Polynomial_Set()
A Dstm32f0xx_hal_rcc_ex.c701 WRITE_REG(CRS->CFGR, value); in HAL_RCCEx_CRSConfig()
854 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); in HAL_RCCEx_CRS_IRQHandler()
863 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); in HAL_RCCEx_CRS_IRQHandler()
872 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); in HAL_RCCEx_CRS_IRQHandler()
896 WRITE_REG(CRS->ICR, CRS_ICR_ERRC); in HAL_RCCEx_CRS_IRQHandler()
A Dstm32f0xx_hal_crc.c156 WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); in HAL_CRC_Init()
160 WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); in HAL_CRC_Init()
A Dstm32f0xx_hal_comp.c532 WRITE_REG(EXTI->PR, extiline); in HAL_COMP_Start_IT()
571 WRITE_REG(EXTI->PR, extiline); in HAL_COMP_IRQHandler()
/lk-master/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Src/
A Dstm32f7xx_hal_qspi.c802 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive()
923 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_IT()
1055 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_DMA()
1127 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); in HAL_QSPI_AutoPolling()
1130 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); in HAL_QSPI_AutoPolling()
1133 WRITE_REG(hqspi->Instance->PIR, cfg->Interval); in HAL_QSPI_AutoPolling()
1228 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); in HAL_QSPI_AutoPolling_IT()
1231 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); in HAL_QSPI_AutoPolling_IT()
1234 WRITE_REG(hqspi->Instance->PIR, cfg->Interval); in HAL_QSPI_AutoPolling_IT()
1697 WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1)); in QSPI_Config()
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A Dstm32f7xx_hal_crc.c143 WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); in HAL_CRC_Init()
156 WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); in HAL_CRC_Init()
158 WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); in HAL_CRC_Init()
A Dstm32f7xx_hal_crc_ex.c150 WRITE_REG(hcrc->Instance->POL, Pol); in HAL_CRCEx_Polynomial_Set()
/lk-master/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/CMSIS/
A Dstm32f7xx.h164 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) macro
168 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |…
/lk-master/external/platform/stm32f0xx/CMSIS/inc/
A Dstm32f0xx.h218 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) macro
222 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |…

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