1 /* 2 * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * 1. Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its 15 * contributors may be used to endorse or promote products derived from this 16 * software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 * 30 * @file nrf9160.h 31 * @brief CMSIS HeaderFile 32 * @version 1 33 * @date 14. August 2020 34 * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:15 35 * from File 'nrf9160.svd', 36 * last modified on Friday, 14.08.2020 13:02:08 37 */ 38 39 40 41 /** @addtogroup Nordic Semiconductor 42 * @{ 43 */ 44 45 46 /** @addtogroup nrf9160 47 * @{ 48 */ 49 50 51 #ifndef NRF9160_H 52 #define NRF9160_H 53 54 #ifdef __cplusplus 55 extern "C" { 56 #endif 57 58 59 /** @addtogroup Configuration_of_CMSIS 60 * @{ 61 */ 62 63 64 65 /* =========================================================================================================================== */ 66 /* ================ Interrupt Number Definition ================ */ 67 /* =========================================================================================================================== */ 68 69 typedef enum { 70 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ 71 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 72 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 73 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 74 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 75 and No Match */ 76 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 77 related Fault */ 78 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 79 SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ 80 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 81 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 82 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 83 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 84 /* ========================================== nrf9160 Specific Interrupt Numbers =========================================== */ 85 SPU_IRQn = 3, /*!< 3 SPU */ 86 CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */ 87 UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn= 8, /*!< 8 UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 */ 88 UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQn= 9, /*!< 9 UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 */ 89 UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQn= 10, /*!< 10 UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 */ 90 UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQn= 11, /*!< 11 UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 */ 91 GPIOTE0_IRQn = 13, /*!< 13 GPIOTE0 */ 92 SAADC_IRQn = 14, /*!< 14 SAADC */ 93 TIMER0_IRQn = 15, /*!< 15 TIMER0 */ 94 TIMER1_IRQn = 16, /*!< 16 TIMER1 */ 95 TIMER2_IRQn = 17, /*!< 17 TIMER2 */ 96 RTC0_IRQn = 20, /*!< 20 RTC0 */ 97 RTC1_IRQn = 21, /*!< 21 RTC1 */ 98 WDT_IRQn = 24, /*!< 24 WDT */ 99 EGU0_IRQn = 27, /*!< 27 EGU0 */ 100 EGU1_IRQn = 28, /*!< 28 EGU1 */ 101 EGU2_IRQn = 29, /*!< 29 EGU2 */ 102 EGU3_IRQn = 30, /*!< 30 EGU3 */ 103 EGU4_IRQn = 31, /*!< 31 EGU4 */ 104 EGU5_IRQn = 32, /*!< 32 EGU5 */ 105 PWM0_IRQn = 33, /*!< 33 PWM0 */ 106 PWM1_IRQn = 34, /*!< 34 PWM1 */ 107 PWM2_IRQn = 35, /*!< 35 PWM2 */ 108 PWM3_IRQn = 36, /*!< 36 PWM3 */ 109 PDM_IRQn = 38, /*!< 38 PDM */ 110 I2S_IRQn = 40, /*!< 40 I2S */ 111 IPC_IRQn = 42, /*!< 42 IPC */ 112 FPU_IRQn = 44, /*!< 44 FPU */ 113 GPIOTE1_IRQn = 49, /*!< 49 GPIOTE1 */ 114 KMU_IRQn = 57, /*!< 57 KMU */ 115 CRYPTOCELL_IRQn = 64 /*!< 64 CRYPTOCELL */ 116 } IRQn_Type; 117 118 119 120 /* =========================================================================================================================== */ 121 /* ================ Processor and Core Peripheral Section ================ */ 122 /* =========================================================================================================================== */ 123 124 /* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ 125 #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ 126 #define __DSP_PRESENT 1 /*!< DSP present or not */ 127 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 128 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 129 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 130 #define __MPU_PRESENT 1 /*!< MPU present */ 131 #define __FPU_PRESENT 1 /*!< FPU present */ 132 #define __FPU_DP 0 /*!< Double Precision FPU */ 133 #define __SAUREGION_PRESENT 0 /*!< SAU region present */ 134 135 136 /** @} */ /* End of group Configuration_of_CMSIS */ 137 138 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ 139 #include "system_nrf9160.h" /*!< nrf9160 System */ 140 141 #ifndef __IM /*!< Fallback for older CMSIS versions */ 142 #define __IM __I 143 #endif 144 #ifndef __OM /*!< Fallback for older CMSIS versions */ 145 #define __OM __O 146 #endif 147 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 148 #define __IOM __IO 149 #endif 150 151 152 /* =========================================================================================================================== */ 153 /* ================ Device Specific Cluster Section ================ */ 154 /* =========================================================================================================================== */ 155 156 157 /** @addtogroup Device_Peripheral_clusters 158 * @{ 159 */ 160 161 162 /** 163 * @brief FICR_INFO [INFO] (Device info) 164 */ 165 typedef struct { 166 __IM uint32_t RESERVED; 167 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */ 168 __IM uint32_t PART; /*!< (@ 0x0000000C) Part code */ 169 __IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production 170 configuration */ 171 __IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */ 172 __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */ 173 __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */ 174 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size */ 175 __IM uint32_t CODESIZE; /*!< (@ 0x00000024) Code memory size */ 176 __IM uint32_t DEVICETYPE; /*!< (@ 0x00000028) Device type */ 177 } FICR_INFO_Type; /*!< Size = 44 (0x2c) */ 178 179 180 /** 181 * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) 182 */ 183 typedef struct { 184 __IM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Address */ 185 __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ 186 } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ 187 188 189 /** 190 * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) 191 */ 192 typedef struct { 193 __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ 194 __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ 195 __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ 196 __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ 197 __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ 198 __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ 199 __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ 200 __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ 201 } FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ 202 203 204 /** 205 * @brief UICR_KEYSLOT_CONFIG [CONFIG] (Unspecified) 206 */ 207 typedef struct { 208 __IOM uint32_t DEST; /*!< (@ 0x00000000) Description cluster: Destination address where 209 content of the key value registers (KEYSLOT.KEYn.VALUE[0-3 210 ) will be pushed by KMU. Note that this 211 address MUST match that of a peripherals 212 APB mapped write-only key registers, else 213 the KMU can push this key value into an 214 address range which the CPU can potentially 215 read! */ 216 __IOM uint32_t PERM; /*!< (@ 0x00000004) Description cluster: Define permissions for the 217 key slot. Bits 0-15 and 16-31 can only be 218 written when equal to 0xFFFF. */ 219 } UICR_KEYSLOT_CONFIG_Type; /*!< Size = 8 (0x8) */ 220 221 222 /** 223 * @brief UICR_KEYSLOT_KEY [KEY] (Unspecified) 224 */ 225 typedef struct { 226 __IOM uint32_t VALUE[4]; /*!< (@ 0x00000000) Description collection: Define bits [31+o*32:0+o*32] 227 of value assigned to KMU key slot. */ 228 } UICR_KEYSLOT_KEY_Type; /*!< Size = 16 (0x10) */ 229 230 231 /** 232 * @brief UICR_KEYSLOT [KEYSLOT] (Unspecified) 233 */ 234 typedef struct { 235 __IOM UICR_KEYSLOT_CONFIG_Type CONFIG[128]; /*!< (@ 0x00000000) Unspecified */ 236 __IOM UICR_KEYSLOT_KEY_Type KEY[128]; /*!< (@ 0x00000400) Unspecified */ 237 } UICR_KEYSLOT_Type; /*!< Size = 3072 (0xc00) */ 238 239 240 /** 241 * @brief TAD_PSEL [PSEL] (Unspecified) 242 */ 243 typedef struct { 244 __IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin number configuration for TRACECLK */ 245 __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin number configuration for TRACEDATA[0] */ 246 __IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin number configuration for TRACEDATA[1] */ 247 __IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin number configuration for TRACEDATA[2] */ 248 __IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin number configuration for TRACEDATA[3] */ 249 } TAD_PSEL_Type; /*!< Size = 20 (0x14) */ 250 251 252 /** 253 * @brief SPU_EXTDOMAIN [EXTDOMAIN] (Unspecified) 254 */ 255 typedef struct { 256 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access for bus access generated 257 from the external domain n List capabilities 258 of the external domain n */ 259 } SPU_EXTDOMAIN_Type; /*!< Size = 4 (0x4) */ 260 261 262 /** 263 * @brief SPU_DPPI [DPPI] (Unspecified) 264 */ 265 typedef struct { 266 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 267 non-secure attribute for the DPPI channels. */ 268 __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 269 of the corresponding PERM register */ 270 } SPU_DPPI_Type; /*!< Size = 8 (0x8) */ 271 272 273 /** 274 * @brief SPU_GPIOPORT [GPIOPORT] (Unspecified) 275 */ 276 typedef struct { 277 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 278 non-secure attribute for pins 0 to 31 of 279 port n. */ 280 __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 281 of the corresponding PERM register */ 282 } SPU_GPIOPORT_Type; /*!< Size = 8 (0x8) */ 283 284 285 /** 286 * @brief SPU_FLASHNSC [FLASHNSC] (Unspecified) 287 */ 288 typedef struct { 289 __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which flash region 290 can contain the non-secure callable (NSC) 291 region n */ 292 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 293 callable (NSC) region n */ 294 } SPU_FLASHNSC_Type; /*!< Size = 8 (0x8) */ 295 296 297 /** 298 * @brief SPU_RAMNSC [RAMNSC] (Unspecified) 299 */ 300 typedef struct { 301 __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which RAM region 302 can contain the non-secure callable (NSC) 303 region n */ 304 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 305 callable (NSC) region n */ 306 } SPU_RAMNSC_Type; /*!< Size = 8 (0x8) */ 307 308 309 /** 310 * @brief SPU_FLASHREGION [FLASHREGION] (Unspecified) 311 */ 312 typedef struct { 313 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for flash 314 region n */ 315 } SPU_FLASHREGION_Type; /*!< Size = 4 (0x4) */ 316 317 318 /** 319 * @brief SPU_RAMREGION [RAMREGION] (Unspecified) 320 */ 321 typedef struct { 322 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for RAM 323 region n */ 324 } SPU_RAMREGION_Type; /*!< Size = 4 (0x4) */ 325 326 327 /** 328 * @brief SPU_PERIPHID [PERIPHID] (Unspecified) 329 */ 330 typedef struct { 331 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: List capabilities and access 332 permissions for the peripheral with ID n */ 333 } SPU_PERIPHID_Type; /*!< Size = 4 (0x4) */ 334 335 336 /** 337 * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified) 338 */ 339 typedef struct { 340 __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU */ 341 __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) Status to indicate if data sent from the debugger 342 to the CPU has been read */ 343 __IM uint32_t RESERVED[30]; 344 __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger */ 345 __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) Status to indicate if data sent from the CPU 346 to the debugger has been read */ 347 } CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */ 348 349 350 /** 351 * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified) 352 */ 353 typedef struct { 354 __IOM uint32_t LOCK; /*!< (@ 0x00000000) Lock register ERASEPROTECT.DISABLE from being 355 written until next reset */ 356 __IOM uint32_t DISABLE; /*!< (@ 0x00000004) Disable ERASEPROTECT and perform ERASEALL */ 357 } CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */ 358 359 360 /** 361 * @brief SPIM_PSEL [PSEL] (Unspecified) 362 */ 363 typedef struct { 364 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 365 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 366 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 367 } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 368 369 370 /** 371 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 372 */ 373 typedef struct { 374 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 375 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 376 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 377 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 378 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 379 380 381 /** 382 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 383 */ 384 typedef struct { 385 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 386 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 387 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 388 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 389 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 390 391 392 /** 393 * @brief SPIS_PSEL [PSEL] (Unspecified) 394 */ 395 typedef struct { 396 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 397 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 398 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 399 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 400 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 401 402 403 /** 404 * @brief SPIS_RXD [RXD] (Unspecified) 405 */ 406 typedef struct { 407 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 408 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 409 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 410 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 411 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 412 413 414 /** 415 * @brief SPIS_TXD [TXD] (Unspecified) 416 */ 417 typedef struct { 418 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 419 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 420 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 421 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 422 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 423 424 425 /** 426 * @brief TWIM_PSEL [PSEL] (Unspecified) 427 */ 428 typedef struct { 429 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 430 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 431 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 432 433 434 /** 435 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 436 */ 437 typedef struct { 438 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 439 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 440 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 441 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 442 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 443 444 445 /** 446 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 447 */ 448 typedef struct { 449 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 450 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 451 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 452 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 453 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 454 455 456 /** 457 * @brief TWIS_PSEL [PSEL] (Unspecified) 458 */ 459 typedef struct { 460 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 461 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 462 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 463 464 465 /** 466 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 467 */ 468 typedef struct { 469 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 470 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 471 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 472 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 473 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 474 475 476 /** 477 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 478 */ 479 typedef struct { 480 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 481 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 482 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 483 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 484 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 485 486 487 /** 488 * @brief UARTE_PSEL [PSEL] (Unspecified) 489 */ 490 typedef struct { 491 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 492 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 493 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 494 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 495 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 496 497 498 /** 499 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 500 */ 501 typedef struct { 502 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 503 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 504 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 505 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 506 507 508 /** 509 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 510 */ 511 typedef struct { 512 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 513 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 514 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 515 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 516 517 518 /** 519 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 520 */ 521 typedef struct { 522 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or 523 above CH[n].LIMIT.HIGH */ 524 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or 525 below CH[n].LIMIT.LOW */ 526 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 527 528 529 /** 530 * @brief SAADC_PUBLISH_CH [PUBLISH_CH] (Publish configuration for events) 531 */ 532 typedef struct { 533 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Publish configuration for 534 event CH[n].LIMITH */ 535 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Publish configuration for 536 event CH[n].LIMITL */ 537 } SAADC_PUBLISH_CH_Type; /*!< Size = 8 (0x8) */ 538 539 540 /** 541 * @brief SAADC_CH [CH] (Unspecified) 542 */ 543 typedef struct { 544 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 545 for CH[n] */ 546 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 547 for CH[n] */ 548 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 549 CH[n] */ 550 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 551 monitoring a channel */ 552 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 553 554 555 /** 556 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 557 */ 558 typedef struct { 559 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 560 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 561 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 562 START */ 563 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 564 565 566 /** 567 * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks) 568 */ 569 typedef struct { 570 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 571 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 572 } DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 573 574 575 /** 576 * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks) 577 */ 578 typedef struct { 579 __IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe configuration 580 for task CHG[n].EN */ 581 __IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe configuration 582 for task CHG[n].DIS */ 583 } DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x8) */ 584 585 586 /** 587 * @brief PWM_SEQ [SEQ] (Unspecified) 588 */ 589 typedef struct { 590 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM 591 of this sequence */ 592 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) 593 in this sequence */ 594 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM 595 periods between samples loaded into compare 596 register */ 597 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ 598 __IM uint32_t RESERVED[4]; 599 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 600 601 602 /** 603 * @brief PWM_PSEL [PSEL] (Unspecified) 604 */ 605 typedef struct { 606 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for 607 PWM channel n */ 608 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 609 610 611 /** 612 * @brief PDM_PSEL [PSEL] (Unspecified) 613 */ 614 typedef struct { 615 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 616 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 617 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 618 619 620 /** 621 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 622 */ 623 typedef struct { 624 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 625 EasyDMA */ 626 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 627 mode */ 628 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 629 630 631 /** 632 * @brief I2S_CONFIG [CONFIG] (Unspecified) 633 */ 634 typedef struct { 635 __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 636 __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 637 __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 638 __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 639 __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 640 __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 641 __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 642 __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 643 __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 644 __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 645 } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 646 647 648 /** 649 * @brief I2S_RXD [RXD] (Unspecified) 650 */ 651 typedef struct { 652 __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 653 } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 654 655 656 /** 657 * @brief I2S_TXD [TXD] (Unspecified) 658 */ 659 typedef struct { 660 __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 661 } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 662 663 664 /** 665 * @brief I2S_RXTXD [RXTXD] (Unspecified) 666 */ 667 typedef struct { 668 __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 669 } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 670 671 672 /** 673 * @brief I2S_PSEL [PSEL] (Unspecified) 674 */ 675 typedef struct { 676 __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 677 __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 678 __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 679 __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 680 __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 681 } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 682 683 684 /** 685 * @brief VMC_RAM [RAM] (Unspecified) 686 */ 687 typedef struct { 688 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ 689 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ 690 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear 691 register */ 692 __IM uint32_t RESERVED; 693 } VMC_RAM_Type; /*!< Size = 16 (0x10) */ 694 695 696 /** @} */ /* End of group Device_Peripheral_clusters */ 697 698 699 /* =========================================================================================================================== */ 700 /* ================ Device Specific Peripheral Section ================ */ 701 /* =========================================================================================================================== */ 702 703 704 /** @addtogroup Device_Peripheral_peripherals 705 * @{ 706 */ 707 708 709 710 /* =========================================================================================================================== */ 711 /* ================ FICR_S ================ */ 712 /* =========================================================================================================================== */ 713 714 715 /** 716 * @brief Factory Information Configuration Registers (FICR_S) 717 */ 718 719 typedef struct { /*!< (@ 0x00FF0000) FICR_S Structure */ 720 __IM uint32_t RESERVED[128]; 721 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ 722 __IM uint32_t RESERVED1[53]; 723 __IOM FICR_TRIMCNF_Type TRIMCNF[256]; /*!< (@ 0x00000300) Unspecified */ 724 __IM uint32_t RESERVED2[64]; 725 __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ 726 } NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ 727 728 729 730 /* =========================================================================================================================== */ 731 /* ================ UICR_S ================ */ 732 /* =========================================================================================================================== */ 733 734 735 /** 736 * @brief User information configuration registers User information configuration registers (UICR_S) 737 */ 738 739 typedef struct { /*!< (@ 0x00FF8000) UICR_S Structure */ 740 __IOM uint32_t APPROTECT; /*!< (@ 0x00000000) Access port protection */ 741 __IM uint32_t RESERVED[4]; 742 __IOM uint32_t XOSC32M; /*!< (@ 0x00000014) Oscillator control */ 743 __IM uint32_t RESERVED1; 744 __IOM uint32_t HFXOSRC; /*!< (@ 0x0000001C) HFXO clock source selection */ 745 __IOM uint32_t HFXOCNT; /*!< (@ 0x00000020) HFXO startup counter */ 746 __IM uint32_t RESERVED2[2]; 747 __IOM uint32_t SECUREAPPROTECT; /*!< (@ 0x0000002C) Secure access port protection */ 748 __IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000030) Erase protection */ 749 __IM uint32_t RESERVED3[53]; 750 __IOM uint32_t OTP[190]; /*!< (@ 0x00000108) Description collection: One time programmable 751 memory */ 752 __IOM UICR_KEYSLOT_Type KEYSLOT; /*!< (@ 0x00000400) Unspecified */ 753 } NRF_UICR_Type; /*!< Size = 4096 (0x1000) */ 754 755 756 757 /* =========================================================================================================================== */ 758 /* ================ TAD_S ================ */ 759 /* =========================================================================================================================== */ 760 761 762 /** 763 * @brief Trace and debug control (TAD_S) 764 */ 765 766 typedef struct { /*!< (@ 0xE0080000) TAD_S Structure */ 767 __OM uint32_t CLOCKSTART; /*!< (@ 0x00000000) Start all trace and debug clocks. */ 768 __OM uint32_t CLOCKSTOP; /*!< (@ 0x00000004) Stop all trace and debug clocks. */ 769 __IM uint32_t RESERVED[318]; 770 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */ 771 __IOM TAD_PSEL_Type PSEL; /*!< (@ 0x00000504) Unspecified */ 772 __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface */ 773 } NRF_TAD_Type; /*!< Size = 1308 (0x51c) */ 774 775 776 777 /* =========================================================================================================================== */ 778 /* ================ SPU_S ================ */ 779 /* =========================================================================================================================== */ 780 781 782 /** 783 * @brief System protection unit (SPU_S) 784 */ 785 786 typedef struct { /*!< (@ 0x50003000) SPU_S Structure */ 787 __IM uint32_t RESERVED[64]; 788 __IOM uint32_t EVENTS_RAMACCERR; /*!< (@ 0x00000100) A security violation has been detected for the 789 RAM memory space */ 790 __IOM uint32_t EVENTS_FLASHACCERR; /*!< (@ 0x00000104) A security violation has been detected for the 791 flash memory space */ 792 __IOM uint32_t EVENTS_PERIPHACCERR; /*!< (@ 0x00000108) A security violation has been detected on one 793 or several peripherals */ 794 __IM uint32_t RESERVED1[29]; 795 __IOM uint32_t PUBLISH_RAMACCERR; /*!< (@ 0x00000180) Publish configuration for event RAMACCERR */ 796 __IOM uint32_t PUBLISH_FLASHACCERR; /*!< (@ 0x00000184) Publish configuration for event FLASHACCERR */ 797 __IOM uint32_t PUBLISH_PERIPHACCERR; /*!< (@ 0x00000188) Publish configuration for event PERIPHACCERR */ 798 __IM uint32_t RESERVED2[93]; 799 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 800 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 801 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 802 __IM uint32_t RESERVED3[61]; 803 __IM uint32_t CAP; /*!< (@ 0x00000400) Show implemented features for the current device */ 804 __IM uint32_t RESERVED4[15]; 805 __IOM SPU_EXTDOMAIN_Type EXTDOMAIN[1]; /*!< (@ 0x00000440) Unspecified */ 806 __IM uint32_t RESERVED5[15]; 807 __IOM SPU_DPPI_Type DPPI[1]; /*!< (@ 0x00000480) Unspecified */ 808 __IM uint32_t RESERVED6[14]; 809 __IOM SPU_GPIOPORT_Type GPIOPORT[1]; /*!< (@ 0x000004C0) Unspecified */ 810 __IM uint32_t RESERVED7[14]; 811 __IOM SPU_FLASHNSC_Type FLASHNSC[2]; /*!< (@ 0x00000500) Unspecified */ 812 __IM uint32_t RESERVED8[12]; 813 __IOM SPU_RAMNSC_Type RAMNSC[2]; /*!< (@ 0x00000540) Unspecified */ 814 __IM uint32_t RESERVED9[44]; 815 __IOM SPU_FLASHREGION_Type FLASHREGION[32]; /*!< (@ 0x00000600) Unspecified */ 816 __IM uint32_t RESERVED10[32]; 817 __IOM SPU_RAMREGION_Type RAMREGION[32]; /*!< (@ 0x00000700) Unspecified */ 818 __IM uint32_t RESERVED11[32]; 819 __IOM SPU_PERIPHID_Type PERIPHID[67]; /*!< (@ 0x00000800) Unspecified */ 820 } NRF_SPU_Type; /*!< Size = 2316 (0x90c) */ 821 822 823 824 /* =========================================================================================================================== */ 825 /* ================ REGULATORS_NS ================ */ 826 /* =========================================================================================================================== */ 827 828 829 /** 830 * @brief Voltage regulators control 0 (REGULATORS_NS) 831 */ 832 833 typedef struct { /*!< (@ 0x40004000) REGULATORS_NS Structure */ 834 __IM uint32_t RESERVED[320]; 835 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 836 __IM uint32_t RESERVED1[29]; 837 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC mode of the main voltage regulator. */ 838 } NRF_REGULATORS_Type; /*!< Size = 1404 (0x57c) */ 839 840 841 842 /* =========================================================================================================================== */ 843 /* ================ CLOCK_NS ================ */ 844 /* =========================================================================================================================== */ 845 846 847 /** 848 * @brief Clock management 0 (CLOCK_NS) 849 */ 850 851 typedef struct { /*!< (@ 0x40005000) CLOCK_NS Structure */ 852 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK source */ 853 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK source */ 854 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 855 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 856 __IM uint32_t RESERVED[28]; 857 __IOM uint32_t SUBSCRIBE_HFCLKSTART; /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART */ 858 __IOM uint32_t SUBSCRIBE_HFCLKSTOP; /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP */ 859 __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART */ 860 __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP */ 861 __IM uint32_t RESERVED1[28]; 862 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 863 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 864 __IM uint32_t RESERVED2[30]; 865 __IOM uint32_t PUBLISH_HFCLKSTARTED; /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED */ 866 __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED */ 867 __IM uint32_t RESERVED3[94]; 868 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 869 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 870 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 871 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 872 __IM uint32_t RESERVED4[62]; 873 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 874 triggered */ 875 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) The register shows if HFXO has been requested 876 by triggering HFCLKSTART task and if it 877 has been started (STATE) */ 878 __IM uint32_t RESERVED5; 879 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 880 triggered */ 881 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) The register shows which LFCLK source has been 882 requested (SRC) when triggering LFCLKSTART 883 task and if the source has been started 884 (STATE) */ 885 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set after LFCLKSTART 886 task has been triggered */ 887 __IM uint32_t RESERVED6[62]; 888 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK. LFCLKSTART task starts 889 starts a clock source selected with this 890 register. */ 891 } NRF_CLOCK_Type; /*!< Size = 1308 (0x51c) */ 892 893 894 895 /* =========================================================================================================================== */ 896 /* ================ POWER_NS ================ */ 897 /* =========================================================================================================================== */ 898 899 900 /** 901 * @brief Power control 0 (POWER_NS) 902 */ 903 904 typedef struct { /*!< (@ 0x40005000) POWER_NS Structure */ 905 __IM uint32_t RESERVED[30]; 906 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode. */ 907 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ 908 __IM uint32_t RESERVED1[30]; 909 __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */ 910 __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */ 911 __IM uint32_t RESERVED2[2]; 912 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 913 __IM uint32_t RESERVED3[2]; 914 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 915 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 916 __IM uint32_t RESERVED4[27]; 917 __IOM uint32_t PUBLISH_POFWARN; /*!< (@ 0x00000188) Publish configuration for event POFWARN */ 918 __IM uint32_t RESERVED5[2]; 919 __IOM uint32_t PUBLISH_SLEEPENTER; /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER */ 920 __IOM uint32_t PUBLISH_SLEEPEXIT; /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT */ 921 __IM uint32_t RESERVED6[89]; 922 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 923 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 924 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 925 __IM uint32_t RESERVED7[61]; 926 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 927 __IM uint32_t RESERVED8[15]; 928 __IM uint32_t POWERSTATUS; /*!< (@ 0x00000440) Modem domain power status */ 929 __IM uint32_t RESERVED9[54]; 930 __IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention 931 register */ 932 } NRF_POWER_Type; /*!< Size = 1316 (0x524) */ 933 934 935 936 /* =========================================================================================================================== */ 937 /* ================ CTRL_AP_PERI_S ================ */ 938 /* =========================================================================================================================== */ 939 940 941 /** 942 * @brief Control access port (CTRL_AP_PERI_S) 943 */ 944 945 typedef struct { /*!< (@ 0x50006000) CTRL_AP_PERI_S Structure */ 946 __IM uint32_t RESERVED[256]; 947 __IOM CTRLAPPERI_MAILBOX_Type MAILBOX; /*!< (@ 0x00000400) Unspecified */ 948 __IM uint32_t RESERVED1[30]; 949 __IOM CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT;/*!< (@ 0x00000500) Unspecified */ 950 } NRF_CTRLAPPERI_Type; /*!< Size = 1288 (0x508) */ 951 952 953 954 /* =========================================================================================================================== */ 955 /* ================ SPIM0_NS ================ */ 956 /* =========================================================================================================================== */ 957 958 959 /** 960 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0_NS) 961 */ 962 963 typedef struct { /*!< (@ 0x40008000) SPIM0_NS Structure */ 964 __IM uint32_t RESERVED[4]; 965 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 966 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 967 __IM uint32_t RESERVED1; 968 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 969 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 970 __IM uint32_t RESERVED2[27]; 971 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000090) Subscribe configuration for task START */ 972 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 973 __IM uint32_t RESERVED3; 974 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 975 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 976 __IM uint32_t RESERVED4[24]; 977 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 978 __IM uint32_t RESERVED5[2]; 979 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 980 __IM uint32_t RESERVED6; 981 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 982 __IM uint32_t RESERVED7; 983 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 984 __IM uint32_t RESERVED8[10]; 985 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 986 __IM uint32_t RESERVED9[13]; 987 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 988 __IM uint32_t RESERVED10[2]; 989 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 990 __IM uint32_t RESERVED11; 991 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000198) Publish configuration for event END */ 992 __IM uint32_t RESERVED12; 993 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 994 __IM uint32_t RESERVED13[10]; 995 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x000001CC) Publish configuration for event STARTED */ 996 __IM uint32_t RESERVED14[12]; 997 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 998 __IM uint32_t RESERVED15[64]; 999 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1000 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1001 __IM uint32_t RESERVED16[125]; 1002 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1003 __IM uint32_t RESERVED17; 1004 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1005 __IM uint32_t RESERVED18[4]; 1006 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1007 source selected. */ 1008 __IM uint32_t RESERVED19[3]; 1009 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1010 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1011 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1012 __IM uint32_t RESERVED20[26]; 1013 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 1014 case an over-read of the TXD buffer. */ 1015 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1016 1017 1018 1019 /* =========================================================================================================================== */ 1020 /* ================ SPIS0_NS ================ */ 1021 /* =========================================================================================================================== */ 1022 1023 1024 /** 1025 * @brief SPI Slave 0 (SPIS0_NS) 1026 */ 1027 1028 typedef struct { /*!< (@ 0x40008000) SPIS0_NS Structure */ 1029 __IM uint32_t RESERVED[9]; 1030 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1031 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1032 to acquire it */ 1033 __IM uint32_t RESERVED1[30]; 1034 __IOM uint32_t SUBSCRIBE_ACQUIRE; /*!< (@ 0x000000A4) Subscribe configuration for task ACQUIRE */ 1035 __IOM uint32_t SUBSCRIBE_RELEASE; /*!< (@ 0x000000A8) Subscribe configuration for task RELEASE */ 1036 __IM uint32_t RESERVED2[22]; 1037 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1038 __IM uint32_t RESERVED3[2]; 1039 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1040 __IM uint32_t RESERVED4[5]; 1041 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1042 __IM uint32_t RESERVED5[22]; 1043 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 1044 __IM uint32_t RESERVED6[2]; 1045 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1046 __IM uint32_t RESERVED7[5]; 1047 __IOM uint32_t PUBLISH_ACQUIRED; /*!< (@ 0x000001A8) Publish configuration for event ACQUIRED */ 1048 __IM uint32_t RESERVED8[21]; 1049 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1050 __IM uint32_t RESERVED9[64]; 1051 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1052 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1053 __IM uint32_t RESERVED10[61]; 1054 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1055 __IM uint32_t RESERVED11[15]; 1056 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1057 __IM uint32_t RESERVED12[47]; 1058 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1059 __IM uint32_t RESERVED13; 1060 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1061 __IM uint32_t RESERVED14[7]; 1062 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1063 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1064 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1065 __IM uint32_t RESERVED15; 1066 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1067 of an ignored transaction. */ 1068 __IM uint32_t RESERVED16[24]; 1069 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1070 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1071 1072 1073 1074 /* =========================================================================================================================== */ 1075 /* ================ TWIM0_NS ================ */ 1076 /* =========================================================================================================================== */ 1077 1078 1079 /** 1080 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0_NS) 1081 */ 1082 1083 typedef struct { /*!< (@ 0x40008000) TWIM0_NS Structure */ 1084 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1085 __IM uint32_t RESERVED; 1086 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1087 __IM uint32_t RESERVED1[2]; 1088 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1089 TWI master is not suspended. */ 1090 __IM uint32_t RESERVED2; 1091 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1092 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1093 __IM uint32_t RESERVED3[23]; 1094 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1095 __IM uint32_t RESERVED4; 1096 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1097 __IM uint32_t RESERVED5[2]; 1098 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1099 __IM uint32_t RESERVED6; 1100 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1101 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1102 __IM uint32_t RESERVED7[24]; 1103 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1104 __IM uint32_t RESERVED8[7]; 1105 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1106 __IM uint32_t RESERVED9[8]; 1107 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is 1108 now suspended. */ 1109 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1110 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1111 __IM uint32_t RESERVED10[2]; 1112 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1113 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1114 byte */ 1115 __IM uint32_t RESERVED11[8]; 1116 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1117 __IM uint32_t RESERVED12[7]; 1118 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1119 __IM uint32_t RESERVED13[8]; 1120 __IOM uint32_t PUBLISH_SUSPENDED; /*!< (@ 0x000001C8) Publish configuration for event SUSPENDED */ 1121 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1122 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1123 __IM uint32_t RESERVED14[2]; 1124 __IOM uint32_t PUBLISH_LASTRX; /*!< (@ 0x000001DC) Publish configuration for event LASTRX */ 1125 __IOM uint32_t PUBLISH_LASTTX; /*!< (@ 0x000001E0) Publish configuration for event LASTTX */ 1126 __IM uint32_t RESERVED15[7]; 1127 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1128 __IM uint32_t RESERVED16[63]; 1129 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1130 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1131 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1132 __IM uint32_t RESERVED17[110]; 1133 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1134 __IM uint32_t RESERVED18[14]; 1135 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1136 __IM uint32_t RESERVED19; 1137 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1138 __IM uint32_t RESERVED20[5]; 1139 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1140 source selected. */ 1141 __IM uint32_t RESERVED21[3]; 1142 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1143 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1144 __IM uint32_t RESERVED22[13]; 1145 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1146 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1147 1148 1149 1150 /* =========================================================================================================================== */ 1151 /* ================ TWIS0_NS ================ */ 1152 /* =========================================================================================================================== */ 1153 1154 1155 /** 1156 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0_NS) 1157 */ 1158 1159 typedef struct { /*!< (@ 0x40008000) TWIS0_NS Structure */ 1160 __IM uint32_t RESERVED[5]; 1161 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1162 __IM uint32_t RESERVED1; 1163 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1164 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1165 __IM uint32_t RESERVED2[3]; 1166 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1167 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1168 __IM uint32_t RESERVED3[23]; 1169 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1170 __IM uint32_t RESERVED4; 1171 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1172 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1173 __IM uint32_t RESERVED5[3]; 1174 __IOM uint32_t SUBSCRIBE_PREPARERX; /*!< (@ 0x000000B0) Subscribe configuration for task PREPARERX */ 1175 __IOM uint32_t SUBSCRIBE_PREPARETX; /*!< (@ 0x000000B4) Subscribe configuration for task PREPARETX */ 1176 __IM uint32_t RESERVED6[19]; 1177 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1178 __IM uint32_t RESERVED7[7]; 1179 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1180 __IM uint32_t RESERVED8[9]; 1181 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1182 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1183 __IM uint32_t RESERVED9[4]; 1184 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1185 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1186 __IM uint32_t RESERVED10[6]; 1187 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1188 __IM uint32_t RESERVED11[7]; 1189 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1190 __IM uint32_t RESERVED12[9]; 1191 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1192 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1193 __IM uint32_t RESERVED13[4]; 1194 __IOM uint32_t PUBLISH_WRITE; /*!< (@ 0x000001E4) Publish configuration for event WRITE */ 1195 __IOM uint32_t PUBLISH_READ; /*!< (@ 0x000001E8) Publish configuration for event READ */ 1196 __IM uint32_t RESERVED14[5]; 1197 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1198 __IM uint32_t RESERVED15[63]; 1199 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1200 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1201 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1202 __IM uint32_t RESERVED16[113]; 1203 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1204 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1205 a match */ 1206 __IM uint32_t RESERVED17[10]; 1207 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1208 __IM uint32_t RESERVED18; 1209 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1210 __IM uint32_t RESERVED19[9]; 1211 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1212 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1213 __IM uint32_t RESERVED20[13]; 1214 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1215 __IM uint32_t RESERVED21; 1216 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1217 mechanism */ 1218 __IM uint32_t RESERVED22[10]; 1219 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1220 of an over-read of the transmit buffer. */ 1221 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1222 1223 1224 1225 /* =========================================================================================================================== */ 1226 /* ================ UARTE0_NS ================ */ 1227 /* =========================================================================================================================== */ 1228 1229 1230 /** 1231 * @brief UART with EasyDMA 0 (UARTE0_NS) 1232 */ 1233 1234 typedef struct { /*!< (@ 0x40008000) UARTE0_NS Structure */ 1235 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1236 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1237 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1238 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1239 __IM uint32_t RESERVED[7]; 1240 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1241 __IM uint32_t RESERVED1[20]; 1242 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1243 __IOM uint32_t SUBSCRIBE_STOPRX; /*!< (@ 0x00000084) Subscribe configuration for task STOPRX */ 1244 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1245 __IOM uint32_t SUBSCRIBE_STOPTX; /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX */ 1246 __IM uint32_t RESERVED2[7]; 1247 __IOM uint32_t SUBSCRIBE_FLUSHRX; /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX */ 1248 __IM uint32_t RESERVED3[20]; 1249 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1250 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1251 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1252 transferred to Data RAM) */ 1253 __IM uint32_t RESERVED4; 1254 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1255 __IM uint32_t RESERVED5[2]; 1256 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1257 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1258 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1259 __IM uint32_t RESERVED6[7]; 1260 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1261 __IM uint32_t RESERVED7; 1262 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1263 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1264 __IM uint32_t RESERVED8; 1265 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1266 __IM uint32_t RESERVED9[9]; 1267 __IOM uint32_t PUBLISH_CTS; /*!< (@ 0x00000180) Publish configuration for event CTS */ 1268 __IOM uint32_t PUBLISH_NCTS; /*!< (@ 0x00000184) Publish configuration for event NCTS */ 1269 __IOM uint32_t PUBLISH_RXDRDY; /*!< (@ 0x00000188) Publish configuration for event RXDRDY */ 1270 __IM uint32_t RESERVED10; 1271 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1272 __IM uint32_t RESERVED11[2]; 1273 __IOM uint32_t PUBLISH_TXDRDY; /*!< (@ 0x0000019C) Publish configuration for event TXDRDY */ 1274 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1275 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1276 __IM uint32_t RESERVED12[7]; 1277 __IOM uint32_t PUBLISH_RXTO; /*!< (@ 0x000001C4) Publish configuration for event RXTO */ 1278 __IM uint32_t RESERVED13; 1279 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1280 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1281 __IM uint32_t RESERVED14; 1282 __IOM uint32_t PUBLISH_TXSTOPPED; /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED */ 1283 __IM uint32_t RESERVED15[9]; 1284 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1285 __IM uint32_t RESERVED16[63]; 1286 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1287 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1288 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1289 __IM uint32_t RESERVED17[93]; 1290 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write 1291 one to clear. */ 1292 __IM uint32_t RESERVED18[31]; 1293 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1294 __IM uint32_t RESERVED19; 1295 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1296 __IM uint32_t RESERVED20[3]; 1297 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1298 selected. */ 1299 __IM uint32_t RESERVED21[3]; 1300 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1301 __IM uint32_t RESERVED22; 1302 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1303 __IM uint32_t RESERVED23[7]; 1304 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1305 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1306 1307 1308 1309 /* =========================================================================================================================== */ 1310 /* ================ GPIOTE0_S ================ */ 1311 /* =========================================================================================================================== */ 1312 1313 1314 /** 1315 * @brief GPIO Tasks and Events 0 (GPIOTE0_S) 1316 */ 1317 1318 typedef struct { /*!< (@ 0x5000D000) GPIOTE0_S Structure */ 1319 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1320 specified in CONFIG[n].PSEL. Action on pin 1321 is configured in CONFIG[n].POLARITY. */ 1322 __IM uint32_t RESERVED[4]; 1323 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1324 specified in CONFIG[n].PSEL. Action on pin 1325 is to set it high. */ 1326 __IM uint32_t RESERVED1[4]; 1327 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1328 specified in CONFIG[n].PSEL. Action on pin 1329 is to set it low. */ 1330 __IOM uint32_t SUBSCRIBE_OUT[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1331 for task OUT[n] */ 1332 __IM uint32_t RESERVED2[4]; 1333 __IOM uint32_t SUBSCRIBE_SET[8]; /*!< (@ 0x000000B0) Description collection: Subscribe configuration 1334 for task SET[n] */ 1335 __IM uint32_t RESERVED3[4]; 1336 __IOM uint32_t SUBSCRIBE_CLR[8]; /*!< (@ 0x000000E0) Description collection: Subscribe configuration 1337 for task CLR[n] */ 1338 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1339 pin specified in CONFIG[n].PSEL */ 1340 __IM uint32_t RESERVED4[23]; 1341 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1342 with SENSE mechanism enabled */ 1343 __IOM uint32_t PUBLISH_IN[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 1344 for event IN[n] */ 1345 __IM uint32_t RESERVED5[23]; 1346 __IOM uint32_t PUBLISH_PORT; /*!< (@ 0x000001FC) Publish configuration for event PORT */ 1347 __IM uint32_t RESERVED6[65]; 1348 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1349 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1350 __IM uint32_t RESERVED7[129]; 1351 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 1352 SET[n] and CLR[n] tasks and IN[n] event */ 1353 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1354 1355 1356 1357 /* =========================================================================================================================== */ 1358 /* ================ SAADC_NS ================ */ 1359 /* =========================================================================================================================== */ 1360 1361 1362 /** 1363 * @brief Analog to Digital Converter 0 (SAADC_NS) 1364 */ 1365 1366 typedef struct { /*!< (@ 0x4000E000) SAADC_NS Structure */ 1367 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 1368 RAM */ 1369 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 1370 are sampled */ 1371 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 1372 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1373 __IM uint32_t RESERVED[28]; 1374 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1375 __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000084) Subscribe configuration for task SAMPLE */ 1376 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 1377 __IOM uint32_t SUBSCRIBE_CALIBRATEOFFSET; /*!< (@ 0x0000008C) Subscribe configuration for task CALIBRATEOFFSET */ 1378 __IM uint32_t RESERVED1[28]; 1379 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 1380 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 1381 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1382 on the mode, multiple conversions might 1383 be needed for a result to be transferred 1384 to RAM. */ 1385 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 1386 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1387 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 1388 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 1389 __IM uint32_t RESERVED2[10]; 1390 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 1391 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 1392 __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x00000188) Publish configuration for event DONE */ 1393 __IOM uint32_t PUBLISH_RESULTDONE; /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE */ 1394 __IOM uint32_t PUBLISH_CALIBRATEDONE; /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE */ 1395 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000194) Publish configuration for event STOPPED */ 1396 __IOM SAADC_PUBLISH_CH_Type PUBLISH_CH[8]; /*!< (@ 0x00000198) Publish configuration for events */ 1397 __IM uint32_t RESERVED3[74]; 1398 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1399 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1400 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1401 __IM uint32_t RESERVED4[61]; 1402 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1403 __IM uint32_t RESERVED5[63]; 1404 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 1405 __IM uint32_t RESERVED6[3]; 1406 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1407 __IM uint32_t RESERVED7[24]; 1408 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1409 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 1410 not be combined with SCAN. The RESOLUTION 1411 is applied before averaging, thus for high 1412 OVERSAMPLE a higher RESOLUTION should be 1413 used. */ 1414 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1415 __IM uint32_t RESERVED8[12]; 1416 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1417 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1418 1419 1420 1421 /* =========================================================================================================================== */ 1422 /* ================ TIMER0_NS ================ */ 1423 /* =========================================================================================================================== */ 1424 1425 1426 /** 1427 * @brief Timer/Counter 0 (TIMER0_NS) 1428 */ 1429 1430 typedef struct { /*!< (@ 0x4000F000) TIMER0_NS Structure */ 1431 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1432 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1433 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1434 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1435 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1436 __IM uint32_t RESERVED[11]; 1437 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 1438 CC[n] register */ 1439 __IM uint32_t RESERVED1[10]; 1440 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1441 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1442 __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */ 1443 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */ 1444 __IOM uint32_t SUBSCRIBE_SHUTDOWN; /*!< (@ 0x00000090) Deprecated register - Subscribe configuration 1445 for task SHUTDOWN */ 1446 __IM uint32_t RESERVED2[11]; 1447 __IOM uint32_t SUBSCRIBE_CAPTURE[6]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 1448 for task CAPTURE[n] */ 1449 __IM uint32_t RESERVED3[26]; 1450 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1451 match */ 1452 __IM uint32_t RESERVED4[26]; 1453 __IOM uint32_t PUBLISH_COMPARE[6]; /*!< (@ 0x000001C0) Description collection: Publish configuration 1454 for event COMPARE[n] */ 1455 __IM uint32_t RESERVED5[10]; 1456 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1457 __IM uint32_t RESERVED6[64]; 1458 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1459 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1460 __IM uint32_t RESERVED7[126]; 1461 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1462 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1463 __IM uint32_t RESERVED8; 1464 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1465 __IOM uint32_t ONESHOTEN[6]; /*!< (@ 0x00000514) Description collection: Enable one-shot operation 1466 for Capture/Compare channel n */ 1467 __IM uint32_t RESERVED9[5]; 1468 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 1469 n */ 1470 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1471 1472 1473 1474 /* =========================================================================================================================== */ 1475 /* ================ RTC0_NS ================ */ 1476 /* =========================================================================================================================== */ 1477 1478 1479 /** 1480 * @brief Real-time counter 0 (RTC0_NS) 1481 */ 1482 1483 typedef struct { /*!< (@ 0x40014000) RTC0_NS Structure */ 1484 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter */ 1485 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter */ 1486 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter */ 1487 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 */ 1488 __IM uint32_t RESERVED[28]; 1489 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1490 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1491 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x00000088) Subscribe configuration for task CLEAR */ 1492 __IOM uint32_t SUBSCRIBE_TRIGOVRFLW; /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW */ 1493 __IM uint32_t RESERVED1[28]; 1494 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on counter increment */ 1495 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on counter overflow */ 1496 __IM uint32_t RESERVED2[14]; 1497 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1498 match */ 1499 __IM uint32_t RESERVED3[12]; 1500 __IOM uint32_t PUBLISH_TICK; /*!< (@ 0x00000180) Publish configuration for event TICK */ 1501 __IOM uint32_t PUBLISH_OVRFLW; /*!< (@ 0x00000184) Publish configuration for event OVRFLW */ 1502 __IM uint32_t RESERVED4[14]; 1503 __IOM uint32_t PUBLISH_COMPARE[4]; /*!< (@ 0x000001C0) Description collection: Publish configuration 1504 for event COMPARE[n] */ 1505 __IM uint32_t RESERVED5[77]; 1506 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1507 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1508 __IM uint32_t RESERVED6[13]; 1509 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1510 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1511 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1512 __IM uint32_t RESERVED7[110]; 1513 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ 1514 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). 1515 Must be written when RTC is stopped. */ 1516 __IM uint32_t RESERVED8[13]; 1517 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 1518 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1519 1520 1521 1522 /* =========================================================================================================================== */ 1523 /* ================ DPPIC_NS ================ */ 1524 /* =========================================================================================================================== */ 1525 1526 1527 /** 1528 * @brief Distributed Programmable Peripheral Interconnect Controller 0 (DPPIC_NS) 1529 */ 1530 1531 typedef struct { /*!< (@ 0x40017000) DPPIC_NS Structure */ 1532 __OM DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 1533 __IM uint32_t RESERVED[20]; 1534 __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks */ 1535 __IM uint32_t RESERVED1[276]; 1536 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 1537 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 1538 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 1539 __IM uint32_t RESERVED2[189]; 1540 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note: 1541 Writes to this register is ignored if either 1542 SUBSCRIBE_CHG[n].EN/DIS are enabled. */ 1543 } NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */ 1544 1545 1546 1547 /* =========================================================================================================================== */ 1548 /* ================ WDT_NS ================ */ 1549 /* =========================================================================================================================== */ 1550 1551 1552 /** 1553 * @brief Watchdog Timer 0 (WDT_NS) 1554 */ 1555 1556 typedef struct { /*!< (@ 0x40018000) WDT_NS Structure */ 1557 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1558 __IM uint32_t RESERVED[31]; 1559 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1560 __IM uint32_t RESERVED1[31]; 1561 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1562 __IM uint32_t RESERVED2[31]; 1563 __IOM uint32_t PUBLISH_TIMEOUT; /*!< (@ 0x00000180) Publish configuration for event TIMEOUT */ 1564 __IM uint32_t RESERVED3[96]; 1565 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1566 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1567 __IM uint32_t RESERVED4[61]; 1568 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1569 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1570 __IM uint32_t RESERVED5[63]; 1571 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1572 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1573 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1574 __IM uint32_t RESERVED6[60]; 1575 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 1576 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1577 1578 1579 1580 /* =========================================================================================================================== */ 1581 /* ================ EGU0_NS ================ */ 1582 /* =========================================================================================================================== */ 1583 1584 1585 /** 1586 * @brief Event generator unit 0 (EGU0_NS) 1587 */ 1588 1589 typedef struct { /*!< (@ 0x4001B000) EGU0_NS Structure */ 1590 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 1591 the corresponding TRIGGERED[n] event */ 1592 __IM uint32_t RESERVED[16]; 1593 __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1594 for task TRIGGER[n] */ 1595 __IM uint32_t RESERVED1[16]; 1596 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 1597 by triggering the corresponding TRIGGER[n] 1598 task */ 1599 __IM uint32_t RESERVED2[16]; 1600 __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 1601 for event TRIGGERED[n] */ 1602 __IM uint32_t RESERVED3[80]; 1603 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1604 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1605 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1606 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1607 1608 1609 1610 /* =========================================================================================================================== */ 1611 /* ================ PWM0_NS ================ */ 1612 /* =========================================================================================================================== */ 1613 1614 1615 /** 1616 * @brief Pulse width modulation unit 0 (PWM0_NS) 1617 */ 1618 1619 typedef struct { /*!< (@ 0x40021000) PWM0_NS Structure */ 1620 __IM uint32_t RESERVED; 1621 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 1622 the end of current PWM period, and stops 1623 sequence playback */ 1624 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value 1625 on all enabled channels from sequence n, 1626 and starts playing that sequence at the 1627 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 1628 Causes PWM generation to start if not running. */ 1629 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 1630 all enabled channels if DECODER.MODE=NextStep. 1631 Does not cause PWM generation to start if 1632 not running. */ 1633 __IM uint32_t RESERVED1[28]; 1634 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1635 __IOM uint32_t SUBSCRIBE_SEQSTART[2]; /*!< (@ 0x00000088) Description collection: Subscribe configuration 1636 for task SEQSTART[n] */ 1637 __IOM uint32_t SUBSCRIBE_NEXTSTEP; /*!< (@ 0x00000090) Subscribe configuration for task NEXTSTEP */ 1638 __IM uint32_t RESERVED2[28]; 1639 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 1640 are no longer generated */ 1641 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started 1642 on sequence n */ 1643 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every 1644 sequence n, when last value from RAM has 1645 been applied to wave counter */ 1646 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 1647 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 1648 of times defined in LOOP.CNT */ 1649 __IM uint32_t RESERVED3[25]; 1650 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1651 __IOM uint32_t PUBLISH_SEQSTARTED[2]; /*!< (@ 0x00000188) Description collection: Publish configuration 1652 for event SEQSTARTED[n] */ 1653 __IOM uint32_t PUBLISH_SEQEND[2]; /*!< (@ 0x00000190) Description collection: Publish configuration 1654 for event SEQEND[n] */ 1655 __IOM uint32_t PUBLISH_PWMPERIODEND; /*!< (@ 0x00000198) Publish configuration for event PWMPERIODEND */ 1656 __IOM uint32_t PUBLISH_LOOPSDONE; /*!< (@ 0x0000019C) Publish configuration for event LOOPSDONE */ 1657 __IM uint32_t RESERVED4[24]; 1658 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1659 __IM uint32_t RESERVED5[63]; 1660 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1661 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1662 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1663 __IM uint32_t RESERVED6[125]; 1664 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 1665 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 1666 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 1667 counts */ 1668 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 1669 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 1670 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 1671 __IM uint32_t RESERVED7[2]; 1672 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 1673 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 1674 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 1675 1676 1677 1678 /* =========================================================================================================================== */ 1679 /* ================ PDM_NS ================ */ 1680 /* =========================================================================================================================== */ 1681 1682 1683 /** 1684 * @brief Pulse Density Modulation (Digital Microphone) Interface 0 (PDM_NS) 1685 */ 1686 1687 typedef struct { /*!< (@ 0x40026000) PDM_NS Structure */ 1688 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 1689 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 1690 __IM uint32_t RESERVED[30]; 1691 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1692 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1693 __IM uint32_t RESERVED1[30]; 1694 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 1695 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 1696 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 1697 by SAMPLE.MAXCNT (or the last sample after 1698 a STOP task has been received) to Data RAM */ 1699 __IM uint32_t RESERVED2[29]; 1700 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 1701 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1702 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000188) Publish configuration for event END */ 1703 __IM uint32_t RESERVED3[93]; 1704 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1705 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1706 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1707 __IM uint32_t RESERVED4[125]; 1708 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 1709 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 1710 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 1711 signals */ 1712 __IM uint32_t RESERVED5[3]; 1713 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 1714 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 1715 __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output 1716 sample rate. Change PDMCLKCTRL accordingly. */ 1717 __IM uint32_t RESERVED6[7]; 1718 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 1719 __IM uint32_t RESERVED7[6]; 1720 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 1721 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 1722 1723 1724 1725 /* =========================================================================================================================== */ 1726 /* ================ I2S_NS ================ */ 1727 /* =========================================================================================================================== */ 1728 1729 1730 /** 1731 * @brief Inter-IC Sound 0 (I2S_NS) 1732 */ 1733 1734 typedef struct { /*!< (@ 0x40028000) I2S_NS Structure */ 1735 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 1736 generator when this is enabled. */ 1737 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 1738 Triggering this task will cause the STOPPED 1739 event to be generated. */ 1740 __IM uint32_t RESERVED[30]; 1741 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1742 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1743 __IM uint32_t RESERVED1[31]; 1744 __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 1745 double-buffers. When the I2S module is started 1746 and RX is enabled, this event will be generated 1747 for every RXTXD.MAXCNT words that are received 1748 on the SDIN pin. */ 1749 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 1750 __IM uint32_t RESERVED2[2]; 1751 __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 1752 double-buffers. When the I2S module is started 1753 and TX is enabled, this event will be generated 1754 for every RXTXD.MAXCNT words that are sent 1755 on the SDOUT pin. */ 1756 __IM uint32_t RESERVED3[27]; 1757 __IOM uint32_t PUBLISH_RXPTRUPD; /*!< (@ 0x00000184) Publish configuration for event RXPTRUPD */ 1758 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000188) Publish configuration for event STOPPED */ 1759 __IM uint32_t RESERVED4[2]; 1760 __IOM uint32_t PUBLISH_TXPTRUPD; /*!< (@ 0x00000194) Publish configuration for event TXPTRUPD */ 1761 __IM uint32_t RESERVED5[90]; 1762 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1763 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1764 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1765 __IM uint32_t RESERVED6[125]; 1766 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 1767 __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 1768 __IM uint32_t RESERVED7[3]; 1769 __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 1770 __IM uint32_t RESERVED8; 1771 __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 1772 __IM uint32_t RESERVED9[3]; 1773 __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 1774 __IM uint32_t RESERVED10[3]; 1775 __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 1776 } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 1777 1778 1779 1780 /* =========================================================================================================================== */ 1781 /* ================ IPC_NS ================ */ 1782 /* =========================================================================================================================== */ 1783 1784 1785 /** 1786 * @brief Inter Processor Communication 0 (IPC_NS) 1787 */ 1788 1789 typedef struct { /*!< (@ 0x4002A000) IPC_NS Structure */ 1790 __OM uint32_t TASKS_SEND[8]; /*!< (@ 0x00000000) Description collection: Trigger events on channel 1791 enabled in SEND_CNF[n]. */ 1792 __IM uint32_t RESERVED[24]; 1793 __IOM uint32_t SUBSCRIBE_SEND[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1794 for task SEND[n] */ 1795 __IM uint32_t RESERVED1[24]; 1796 __IOM uint32_t EVENTS_RECEIVE[8]; /*!< (@ 0x00000100) Description collection: Event received on one 1797 or more of the enabled channels in RECEIVE_CNF[n]. */ 1798 __IM uint32_t RESERVED2[24]; 1799 __IOM uint32_t PUBLISH_RECEIVE[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 1800 for event RECEIVE[n] */ 1801 __IM uint32_t RESERVED3[88]; 1802 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1803 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1804 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1805 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 1806 __IM uint32_t RESERVED4[128]; 1807 __IOM uint32_t SEND_CNF[8]; /*!< (@ 0x00000510) Description collection: Send event configuration 1808 for TASKS_SEND[n]. */ 1809 __IM uint32_t RESERVED5[24]; 1810 __IOM uint32_t RECEIVE_CNF[8]; /*!< (@ 0x00000590) Description collection: Receive event configuration 1811 for EVENTS_RECEIVE[n]. */ 1812 __IM uint32_t RESERVED6[24]; 1813 __IOM uint32_t GPMEM[4]; /*!< (@ 0x00000610) Description collection: General purpose memory. */ 1814 } NRF_IPC_Type; /*!< Size = 1568 (0x620) */ 1815 1816 1817 1818 /* =========================================================================================================================== */ 1819 /* ================ FPU_NS ================ */ 1820 /* =========================================================================================================================== */ 1821 1822 1823 /** 1824 * @brief FPU 0 (FPU_NS) 1825 */ 1826 1827 typedef struct { /*!< (@ 0x4002C000) FPU_NS Structure */ 1828 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1829 } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 1830 1831 1832 1833 /* =========================================================================================================================== */ 1834 /* ================ KMU_NS ================ */ 1835 /* =========================================================================================================================== */ 1836 1837 1838 /** 1839 * @brief Key management unit 0 (KMU_NS) 1840 */ 1841 1842 typedef struct { /*!< (@ 0x40039000) KMU_NS Structure */ 1843 __OM uint32_t TASKS_PUSH_KEYSLOT; /*!< (@ 0x00000000) Push a key slot over secure APB */ 1844 __IM uint32_t RESERVED[63]; 1845 __IOM uint32_t EVENTS_KEYSLOT_PUSHED; /*!< (@ 0x00000100) Key slot successfully pushed over secure APB */ 1846 __IOM uint32_t EVENTS_KEYSLOT_REVOKED; /*!< (@ 0x00000104) Key slot has been revoked and cannot be tasked 1847 for selection */ 1848 __IOM uint32_t EVENTS_KEYSLOT_ERROR; /*!< (@ 0x00000108) No key slot selected, no destination address 1849 defined, or error during push operation */ 1850 __IM uint32_t RESERVED1[125]; 1851 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1852 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1853 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1854 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 1855 __IM uint32_t RESERVED2[63]; 1856 __IM uint32_t STATUS; /*!< (@ 0x0000040C) Status bits for KMU operation */ 1857 __IM uint32_t RESERVED3[60]; 1858 __IOM uint32_t SELECTKEYSLOT; /*!< (@ 0x00000500) Select key slot to be read over AHB or pushed 1859 over secure APB when TASKS_PUSH_KEYSLOT 1860 is started */ 1861 } NRF_KMU_Type; /*!< Size = 1284 (0x504) */ 1862 1863 1864 1865 /* =========================================================================================================================== */ 1866 /* ================ NVMC_NS ================ */ 1867 /* =========================================================================================================================== */ 1868 1869 1870 /** 1871 * @brief Non-volatile memory controller 0 (NVMC_NS) 1872 */ 1873 1874 typedef struct { /*!< (@ 0x40039000) NVMC_NS Structure */ 1875 __IM uint32_t RESERVED[256]; 1876 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 1877 __IM uint32_t RESERVED1; 1878 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 1879 __IM uint32_t RESERVED2[62]; 1880 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1881 __IM uint32_t RESERVED3; 1882 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 1883 __IM uint32_t RESERVED4[3]; 1884 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 1885 __IM uint32_t RESERVED5[8]; 1886 __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ 1887 __IM uint32_t RESERVED6; 1888 __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ 1889 __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ 1890 __IM uint32_t RESERVED7[13]; 1891 __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Unspecified */ 1892 __OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */ 1893 } NRF_NVMC_Type; /*!< Size = 1420 (0x58c) */ 1894 1895 1896 1897 /* =========================================================================================================================== */ 1898 /* ================ VMC_NS ================ */ 1899 /* =========================================================================================================================== */ 1900 1901 1902 /** 1903 * @brief Volatile Memory controller 0 (VMC_NS) 1904 */ 1905 1906 typedef struct { /*!< (@ 0x4003A000) VMC_NS Structure */ 1907 __IM uint32_t RESERVED[384]; 1908 __IOM VMC_RAM_Type RAM[8]; /*!< (@ 0x00000600) Unspecified */ 1909 } NRF_VMC_Type; /*!< Size = 1664 (0x680) */ 1910 1911 1912 1913 /* =========================================================================================================================== */ 1914 /* ================ CC_HOST_RGF_S ================ */ 1915 /* =========================================================================================================================== */ 1916 1917 1918 /** 1919 * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF_S) 1920 */ 1921 1922 typedef struct { /*!< (@ 0x50840000) CC_HOST_RGF_S Structure */ 1923 __IM uint32_t RESERVED[1678]; 1924 __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00001A38) AES hardware key select */ 1925 __IM uint32_t RESERVED1[4]; 1926 __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register. 1927 When this register is set, K_PRTL cannot 1928 be used and a zeroed key will be used instead. 1929 The value of this register is saved in the 1930 CRYPTOCELL AO power domain. */ 1931 __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00001A50) This register holds bits 31:0 of K_DR. The value 1932 of this register is saved in the CRYPTOCELL 1933 AO power domain. Reading from this address 1934 returns the K_DR valid status indicating 1935 if K_DR is successfully retained. */ 1936 __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00001A54) This register holds bits 63:32 of K_DR. The value 1937 of this register is saved in the CRYPTOCELL 1938 AO power domain. */ 1939 __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00001A58) This register holds bits 95:64 of K_DR. The value 1940 of this register is saved in the CRYPTOCELL 1941 AO power domain. */ 1942 __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00001A5C) This register holds bits 127:96 of K_DR. The 1943 value of this register is saved in the CRYPTOCELL 1944 AO power domain. */ 1945 __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00001A60) Controls lifecycle state (LCS) for CRYPTOCELL 1946 subsystem */ 1947 } NRF_CC_HOST_RGF_Type; /*!< Size = 6756 (0x1a64) */ 1948 1949 1950 1951 /* =========================================================================================================================== */ 1952 /* ================ CRYPTOCELL_S ================ */ 1953 /* =========================================================================================================================== */ 1954 1955 1956 /** 1957 * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL_S) 1958 */ 1959 1960 typedef struct { /*!< (@ 0x50840000) CRYPTOCELL_S Structure */ 1961 __IM uint32_t RESERVED[320]; 1962 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem */ 1963 } NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ 1964 1965 1966 1967 /* =========================================================================================================================== */ 1968 /* ================ P0_NS ================ */ 1969 /* =========================================================================================================================== */ 1970 1971 1972 /** 1973 * @brief GPIO Port 0 (P0_NS) 1974 */ 1975 1976 typedef struct { /*!< (@ 0x40842500) P0_NS Structure */ 1977 __IM uint32_t RESERVED; 1978 __IOM uint32_t OUT; /*!< (@ 0x00000004) Write GPIO port */ 1979 __IOM uint32_t OUTSET; /*!< (@ 0x00000008) Set individual bits in GPIO port */ 1980 __IOM uint32_t OUTCLR; /*!< (@ 0x0000000C) Clear individual bits in GPIO port */ 1981 __IM uint32_t IN; /*!< (@ 0x00000010) Read GPIO port */ 1982 __IOM uint32_t DIR; /*!< (@ 0x00000014) Direction of GPIO pins */ 1983 __IOM uint32_t DIRSET; /*!< (@ 0x00000018) DIR set register */ 1984 __IOM uint32_t DIRCLR; /*!< (@ 0x0000001C) DIR clear register */ 1985 __IOM uint32_t LATCH; /*!< (@ 0x00000020) Latch register indicating what GPIO pins that 1986 have met the criteria set in the PIN_CNF[n].SENSE 1987 registers */ 1988 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behavior 1989 and LDETECT mode (For non-secure pin only) */ 1990 __IOM uint32_t DETECTMODE_SEC; /*!< (@ 0x00000028) Select between default DETECT signal behavior 1991 and LDETECT mode (For secure pin only) */ 1992 __IM uint32_t RESERVED1[117]; 1993 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000200) Description collection: Configuration of GPIO 1994 pins */ 1995 } NRF_GPIO_Type; /*!< Size = 640 (0x280) */ 1996 1997 1998 /** @} */ /* End of group Device_Peripheral_peripherals */ 1999 2000 2001 /* =========================================================================================================================== */ 2002 /* ================ Device Specific Peripheral Address Map ================ */ 2003 /* =========================================================================================================================== */ 2004 2005 2006 /** @addtogroup Device_Peripheral_peripheralAddr 2007 * @{ 2008 */ 2009 2010 #define NRF_FICR_S_BASE 0x00FF0000UL 2011 #define NRF_UICR_S_BASE 0x00FF8000UL 2012 #define NRF_TAD_S_BASE 0xE0080000UL 2013 #define NRF_SPU_S_BASE 0x50003000UL 2014 #define NRF_REGULATORS_NS_BASE 0x40004000UL 2015 #define NRF_REGULATORS_S_BASE 0x50004000UL 2016 #define NRF_CLOCK_NS_BASE 0x40005000UL 2017 #define NRF_POWER_NS_BASE 0x40005000UL 2018 #define NRF_CLOCK_S_BASE 0x50005000UL 2019 #define NRF_POWER_S_BASE 0x50005000UL 2020 #define NRF_CTRL_AP_PERI_S_BASE 0x50006000UL 2021 #define NRF_SPIM0_NS_BASE 0x40008000UL 2022 #define NRF_SPIS0_NS_BASE 0x40008000UL 2023 #define NRF_TWIM0_NS_BASE 0x40008000UL 2024 #define NRF_TWIS0_NS_BASE 0x40008000UL 2025 #define NRF_UARTE0_NS_BASE 0x40008000UL 2026 #define NRF_SPIM0_S_BASE 0x50008000UL 2027 #define NRF_SPIS0_S_BASE 0x50008000UL 2028 #define NRF_TWIM0_S_BASE 0x50008000UL 2029 #define NRF_TWIS0_S_BASE 0x50008000UL 2030 #define NRF_UARTE0_S_BASE 0x50008000UL 2031 #define NRF_SPIM1_NS_BASE 0x40009000UL 2032 #define NRF_SPIS1_NS_BASE 0x40009000UL 2033 #define NRF_TWIM1_NS_BASE 0x40009000UL 2034 #define NRF_TWIS1_NS_BASE 0x40009000UL 2035 #define NRF_UARTE1_NS_BASE 0x40009000UL 2036 #define NRF_SPIM1_S_BASE 0x50009000UL 2037 #define NRF_SPIS1_S_BASE 0x50009000UL 2038 #define NRF_TWIM1_S_BASE 0x50009000UL 2039 #define NRF_TWIS1_S_BASE 0x50009000UL 2040 #define NRF_UARTE1_S_BASE 0x50009000UL 2041 #define NRF_SPIM2_NS_BASE 0x4000A000UL 2042 #define NRF_SPIS2_NS_BASE 0x4000A000UL 2043 #define NRF_TWIM2_NS_BASE 0x4000A000UL 2044 #define NRF_TWIS2_NS_BASE 0x4000A000UL 2045 #define NRF_UARTE2_NS_BASE 0x4000A000UL 2046 #define NRF_SPIM2_S_BASE 0x5000A000UL 2047 #define NRF_SPIS2_S_BASE 0x5000A000UL 2048 #define NRF_TWIM2_S_BASE 0x5000A000UL 2049 #define NRF_TWIS2_S_BASE 0x5000A000UL 2050 #define NRF_UARTE2_S_BASE 0x5000A000UL 2051 #define NRF_SPIM3_NS_BASE 0x4000B000UL 2052 #define NRF_SPIS3_NS_BASE 0x4000B000UL 2053 #define NRF_TWIM3_NS_BASE 0x4000B000UL 2054 #define NRF_TWIS3_NS_BASE 0x4000B000UL 2055 #define NRF_UARTE3_NS_BASE 0x4000B000UL 2056 #define NRF_SPIM3_S_BASE 0x5000B000UL 2057 #define NRF_SPIS3_S_BASE 0x5000B000UL 2058 #define NRF_TWIM3_S_BASE 0x5000B000UL 2059 #define NRF_TWIS3_S_BASE 0x5000B000UL 2060 #define NRF_UARTE3_S_BASE 0x5000B000UL 2061 #define NRF_GPIOTE0_S_BASE 0x5000D000UL 2062 #define NRF_SAADC_NS_BASE 0x4000E000UL 2063 #define NRF_SAADC_S_BASE 0x5000E000UL 2064 #define NRF_TIMER0_NS_BASE 0x4000F000UL 2065 #define NRF_TIMER0_S_BASE 0x5000F000UL 2066 #define NRF_TIMER1_NS_BASE 0x40010000UL 2067 #define NRF_TIMER1_S_BASE 0x50010000UL 2068 #define NRF_TIMER2_NS_BASE 0x40011000UL 2069 #define NRF_TIMER2_S_BASE 0x50011000UL 2070 #define NRF_RTC0_NS_BASE 0x40014000UL 2071 #define NRF_RTC0_S_BASE 0x50014000UL 2072 #define NRF_RTC1_NS_BASE 0x40015000UL 2073 #define NRF_RTC1_S_BASE 0x50015000UL 2074 #define NRF_DPPIC_NS_BASE 0x40017000UL 2075 #define NRF_DPPIC_S_BASE 0x50017000UL 2076 #define NRF_WDT_NS_BASE 0x40018000UL 2077 #define NRF_WDT_S_BASE 0x50018000UL 2078 #define NRF_EGU0_NS_BASE 0x4001B000UL 2079 #define NRF_EGU0_S_BASE 0x5001B000UL 2080 #define NRF_EGU1_NS_BASE 0x4001C000UL 2081 #define NRF_EGU1_S_BASE 0x5001C000UL 2082 #define NRF_EGU2_NS_BASE 0x4001D000UL 2083 #define NRF_EGU2_S_BASE 0x5001D000UL 2084 #define NRF_EGU3_NS_BASE 0x4001E000UL 2085 #define NRF_EGU3_S_BASE 0x5001E000UL 2086 #define NRF_EGU4_NS_BASE 0x4001F000UL 2087 #define NRF_EGU4_S_BASE 0x5001F000UL 2088 #define NRF_EGU5_NS_BASE 0x40020000UL 2089 #define NRF_EGU5_S_BASE 0x50020000UL 2090 #define NRF_PWM0_NS_BASE 0x40021000UL 2091 #define NRF_PWM0_S_BASE 0x50021000UL 2092 #define NRF_PWM1_NS_BASE 0x40022000UL 2093 #define NRF_PWM1_S_BASE 0x50022000UL 2094 #define NRF_PWM2_NS_BASE 0x40023000UL 2095 #define NRF_PWM2_S_BASE 0x50023000UL 2096 #define NRF_PWM3_NS_BASE 0x40024000UL 2097 #define NRF_PWM3_S_BASE 0x50024000UL 2098 #define NRF_PDM_NS_BASE 0x40026000UL 2099 #define NRF_PDM_S_BASE 0x50026000UL 2100 #define NRF_I2S_NS_BASE 0x40028000UL 2101 #define NRF_I2S_S_BASE 0x50028000UL 2102 #define NRF_IPC_NS_BASE 0x4002A000UL 2103 #define NRF_IPC_S_BASE 0x5002A000UL 2104 #define NRF_FPU_NS_BASE 0x4002C000UL 2105 #define NRF_FPU_S_BASE 0x5002C000UL 2106 #define NRF_GPIOTE1_NS_BASE 0x40031000UL 2107 #define NRF_KMU_NS_BASE 0x40039000UL 2108 #define NRF_NVMC_NS_BASE 0x40039000UL 2109 #define NRF_KMU_S_BASE 0x50039000UL 2110 #define NRF_NVMC_S_BASE 0x50039000UL 2111 #define NRF_VMC_NS_BASE 0x4003A000UL 2112 #define NRF_VMC_S_BASE 0x5003A000UL 2113 #define NRF_CC_HOST_RGF_S_BASE 0x50840000UL 2114 #define NRF_CRYPTOCELL_S_BASE 0x50840000UL 2115 #define NRF_P0_NS_BASE 0x40842500UL 2116 #define NRF_P0_S_BASE 0x50842500UL 2117 2118 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 2119 2120 2121 /* =========================================================================================================================== */ 2122 /* ================ Peripheral declaration ================ */ 2123 /* =========================================================================================================================== */ 2124 2125 2126 /** @addtogroup Device_Peripheral_declaration 2127 * @{ 2128 */ 2129 2130 #define NRF_FICR_S ((NRF_FICR_Type*) NRF_FICR_S_BASE) 2131 #define NRF_UICR_S ((NRF_UICR_Type*) NRF_UICR_S_BASE) 2132 #define NRF_TAD_S ((NRF_TAD_Type*) NRF_TAD_S_BASE) 2133 #define NRF_SPU_S ((NRF_SPU_Type*) NRF_SPU_S_BASE) 2134 #define NRF_REGULATORS_NS ((NRF_REGULATORS_Type*) NRF_REGULATORS_NS_BASE) 2135 #define NRF_REGULATORS_S ((NRF_REGULATORS_Type*) NRF_REGULATORS_S_BASE) 2136 #define NRF_CLOCK_NS ((NRF_CLOCK_Type*) NRF_CLOCK_NS_BASE) 2137 #define NRF_POWER_NS ((NRF_POWER_Type*) NRF_POWER_NS_BASE) 2138 #define NRF_CLOCK_S ((NRF_CLOCK_Type*) NRF_CLOCK_S_BASE) 2139 #define NRF_POWER_S ((NRF_POWER_Type*) NRF_POWER_S_BASE) 2140 #define NRF_CTRL_AP_PERI_S ((NRF_CTRLAPPERI_Type*) NRF_CTRL_AP_PERI_S_BASE) 2141 #define NRF_SPIM0_NS ((NRF_SPIM_Type*) NRF_SPIM0_NS_BASE) 2142 #define NRF_SPIS0_NS ((NRF_SPIS_Type*) NRF_SPIS0_NS_BASE) 2143 #define NRF_TWIM0_NS ((NRF_TWIM_Type*) NRF_TWIM0_NS_BASE) 2144 #define NRF_TWIS0_NS ((NRF_TWIS_Type*) NRF_TWIS0_NS_BASE) 2145 #define NRF_UARTE0_NS ((NRF_UARTE_Type*) NRF_UARTE0_NS_BASE) 2146 #define NRF_SPIM0_S ((NRF_SPIM_Type*) NRF_SPIM0_S_BASE) 2147 #define NRF_SPIS0_S ((NRF_SPIS_Type*) NRF_SPIS0_S_BASE) 2148 #define NRF_TWIM0_S ((NRF_TWIM_Type*) NRF_TWIM0_S_BASE) 2149 #define NRF_TWIS0_S ((NRF_TWIS_Type*) NRF_TWIS0_S_BASE) 2150 #define NRF_UARTE0_S ((NRF_UARTE_Type*) NRF_UARTE0_S_BASE) 2151 #define NRF_SPIM1_NS ((NRF_SPIM_Type*) NRF_SPIM1_NS_BASE) 2152 #define NRF_SPIS1_NS ((NRF_SPIS_Type*) NRF_SPIS1_NS_BASE) 2153 #define NRF_TWIM1_NS ((NRF_TWIM_Type*) NRF_TWIM1_NS_BASE) 2154 #define NRF_TWIS1_NS ((NRF_TWIS_Type*) NRF_TWIS1_NS_BASE) 2155 #define NRF_UARTE1_NS ((NRF_UARTE_Type*) NRF_UARTE1_NS_BASE) 2156 #define NRF_SPIM1_S ((NRF_SPIM_Type*) NRF_SPIM1_S_BASE) 2157 #define NRF_SPIS1_S ((NRF_SPIS_Type*) NRF_SPIS1_S_BASE) 2158 #define NRF_TWIM1_S ((NRF_TWIM_Type*) NRF_TWIM1_S_BASE) 2159 #define NRF_TWIS1_S ((NRF_TWIS_Type*) NRF_TWIS1_S_BASE) 2160 #define NRF_UARTE1_S ((NRF_UARTE_Type*) NRF_UARTE1_S_BASE) 2161 #define NRF_SPIM2_NS ((NRF_SPIM_Type*) NRF_SPIM2_NS_BASE) 2162 #define NRF_SPIS2_NS ((NRF_SPIS_Type*) NRF_SPIS2_NS_BASE) 2163 #define NRF_TWIM2_NS ((NRF_TWIM_Type*) NRF_TWIM2_NS_BASE) 2164 #define NRF_TWIS2_NS ((NRF_TWIS_Type*) NRF_TWIS2_NS_BASE) 2165 #define NRF_UARTE2_NS ((NRF_UARTE_Type*) NRF_UARTE2_NS_BASE) 2166 #define NRF_SPIM2_S ((NRF_SPIM_Type*) NRF_SPIM2_S_BASE) 2167 #define NRF_SPIS2_S ((NRF_SPIS_Type*) NRF_SPIS2_S_BASE) 2168 #define NRF_TWIM2_S ((NRF_TWIM_Type*) NRF_TWIM2_S_BASE) 2169 #define NRF_TWIS2_S ((NRF_TWIS_Type*) NRF_TWIS2_S_BASE) 2170 #define NRF_UARTE2_S ((NRF_UARTE_Type*) NRF_UARTE2_S_BASE) 2171 #define NRF_SPIM3_NS ((NRF_SPIM_Type*) NRF_SPIM3_NS_BASE) 2172 #define NRF_SPIS3_NS ((NRF_SPIS_Type*) NRF_SPIS3_NS_BASE) 2173 #define NRF_TWIM3_NS ((NRF_TWIM_Type*) NRF_TWIM3_NS_BASE) 2174 #define NRF_TWIS3_NS ((NRF_TWIS_Type*) NRF_TWIS3_NS_BASE) 2175 #define NRF_UARTE3_NS ((NRF_UARTE_Type*) NRF_UARTE3_NS_BASE) 2176 #define NRF_SPIM3_S ((NRF_SPIM_Type*) NRF_SPIM3_S_BASE) 2177 #define NRF_SPIS3_S ((NRF_SPIS_Type*) NRF_SPIS3_S_BASE) 2178 #define NRF_TWIM3_S ((NRF_TWIM_Type*) NRF_TWIM3_S_BASE) 2179 #define NRF_TWIS3_S ((NRF_TWIS_Type*) NRF_TWIS3_S_BASE) 2180 #define NRF_UARTE3_S ((NRF_UARTE_Type*) NRF_UARTE3_S_BASE) 2181 #define NRF_GPIOTE0_S ((NRF_GPIOTE_Type*) NRF_GPIOTE0_S_BASE) 2182 #define NRF_SAADC_NS ((NRF_SAADC_Type*) NRF_SAADC_NS_BASE) 2183 #define NRF_SAADC_S ((NRF_SAADC_Type*) NRF_SAADC_S_BASE) 2184 #define NRF_TIMER0_NS ((NRF_TIMER_Type*) NRF_TIMER0_NS_BASE) 2185 #define NRF_TIMER0_S ((NRF_TIMER_Type*) NRF_TIMER0_S_BASE) 2186 #define NRF_TIMER1_NS ((NRF_TIMER_Type*) NRF_TIMER1_NS_BASE) 2187 #define NRF_TIMER1_S ((NRF_TIMER_Type*) NRF_TIMER1_S_BASE) 2188 #define NRF_TIMER2_NS ((NRF_TIMER_Type*) NRF_TIMER2_NS_BASE) 2189 #define NRF_TIMER2_S ((NRF_TIMER_Type*) NRF_TIMER2_S_BASE) 2190 #define NRF_RTC0_NS ((NRF_RTC_Type*) NRF_RTC0_NS_BASE) 2191 #define NRF_RTC0_S ((NRF_RTC_Type*) NRF_RTC0_S_BASE) 2192 #define NRF_RTC1_NS ((NRF_RTC_Type*) NRF_RTC1_NS_BASE) 2193 #define NRF_RTC1_S ((NRF_RTC_Type*) NRF_RTC1_S_BASE) 2194 #define NRF_DPPIC_NS ((NRF_DPPIC_Type*) NRF_DPPIC_NS_BASE) 2195 #define NRF_DPPIC_S ((NRF_DPPIC_Type*) NRF_DPPIC_S_BASE) 2196 #define NRF_WDT_NS ((NRF_WDT_Type*) NRF_WDT_NS_BASE) 2197 #define NRF_WDT_S ((NRF_WDT_Type*) NRF_WDT_S_BASE) 2198 #define NRF_EGU0_NS ((NRF_EGU_Type*) NRF_EGU0_NS_BASE) 2199 #define NRF_EGU0_S ((NRF_EGU_Type*) NRF_EGU0_S_BASE) 2200 #define NRF_EGU1_NS ((NRF_EGU_Type*) NRF_EGU1_NS_BASE) 2201 #define NRF_EGU1_S ((NRF_EGU_Type*) NRF_EGU1_S_BASE) 2202 #define NRF_EGU2_NS ((NRF_EGU_Type*) NRF_EGU2_NS_BASE) 2203 #define NRF_EGU2_S ((NRF_EGU_Type*) NRF_EGU2_S_BASE) 2204 #define NRF_EGU3_NS ((NRF_EGU_Type*) NRF_EGU3_NS_BASE) 2205 #define NRF_EGU3_S ((NRF_EGU_Type*) NRF_EGU3_S_BASE) 2206 #define NRF_EGU4_NS ((NRF_EGU_Type*) NRF_EGU4_NS_BASE) 2207 #define NRF_EGU4_S ((NRF_EGU_Type*) NRF_EGU4_S_BASE) 2208 #define NRF_EGU5_NS ((NRF_EGU_Type*) NRF_EGU5_NS_BASE) 2209 #define NRF_EGU5_S ((NRF_EGU_Type*) NRF_EGU5_S_BASE) 2210 #define NRF_PWM0_NS ((NRF_PWM_Type*) NRF_PWM0_NS_BASE) 2211 #define NRF_PWM0_S ((NRF_PWM_Type*) NRF_PWM0_S_BASE) 2212 #define NRF_PWM1_NS ((NRF_PWM_Type*) NRF_PWM1_NS_BASE) 2213 #define NRF_PWM1_S ((NRF_PWM_Type*) NRF_PWM1_S_BASE) 2214 #define NRF_PWM2_NS ((NRF_PWM_Type*) NRF_PWM2_NS_BASE) 2215 #define NRF_PWM2_S ((NRF_PWM_Type*) NRF_PWM2_S_BASE) 2216 #define NRF_PWM3_NS ((NRF_PWM_Type*) NRF_PWM3_NS_BASE) 2217 #define NRF_PWM3_S ((NRF_PWM_Type*) NRF_PWM3_S_BASE) 2218 #define NRF_PDM_NS ((NRF_PDM_Type*) NRF_PDM_NS_BASE) 2219 #define NRF_PDM_S ((NRF_PDM_Type*) NRF_PDM_S_BASE) 2220 #define NRF_I2S_NS ((NRF_I2S_Type*) NRF_I2S_NS_BASE) 2221 #define NRF_I2S_S ((NRF_I2S_Type*) NRF_I2S_S_BASE) 2222 #define NRF_IPC_NS ((NRF_IPC_Type*) NRF_IPC_NS_BASE) 2223 #define NRF_IPC_S ((NRF_IPC_Type*) NRF_IPC_S_BASE) 2224 #define NRF_FPU_NS ((NRF_FPU_Type*) NRF_FPU_NS_BASE) 2225 #define NRF_FPU_S ((NRF_FPU_Type*) NRF_FPU_S_BASE) 2226 #define NRF_GPIOTE1_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE1_NS_BASE) 2227 #define NRF_KMU_NS ((NRF_KMU_Type*) NRF_KMU_NS_BASE) 2228 #define NRF_NVMC_NS ((NRF_NVMC_Type*) NRF_NVMC_NS_BASE) 2229 #define NRF_KMU_S ((NRF_KMU_Type*) NRF_KMU_S_BASE) 2230 #define NRF_NVMC_S ((NRF_NVMC_Type*) NRF_NVMC_S_BASE) 2231 #define NRF_VMC_NS ((NRF_VMC_Type*) NRF_VMC_NS_BASE) 2232 #define NRF_VMC_S ((NRF_VMC_Type*) NRF_VMC_S_BASE) 2233 #define NRF_CC_HOST_RGF_S ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_S_BASE) 2234 #define NRF_CRYPTOCELL_S ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_S_BASE) 2235 #define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE) 2236 #define NRF_P0_S ((NRF_GPIO_Type*) NRF_P0_S_BASE) 2237 2238 /** @} */ /* End of group Device_Peripheral_declaration */ 2239 2240 2241 #ifdef __cplusplus 2242 } 2243 #endif 2244 2245 #endif /* NRF9160_H */ 2246 2247 2248 /** @} */ /* End of group nrf9160 */ 2249 2250 /** @} */ /* End of group Nordic Semiconductor */ 2251