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Searched refs:channel (Results 1 – 25 of 39) sorted by relevance

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/lk-master/external/platform/pico/rp2_common/hardware_dma/include/hardware/
A Ddma.h49 check_dma_channel_param_impl(channel); in check_dma_channel_param()
54 check_dma_channel_param(channel); in dma_channel_hw_addr()
55 return &dma_hw->ch[channel]; in dma_channel_hw_addr()
67 void dma_channel_claim(uint channel);
87 void dma_channel_unclaim(uint channel);
460 check_dma_channel_param(channel); in dma_channel_abort()
461 dma_hw->abort = 1u << channel; in dma_channel_abort()
474 check_dma_channel_param(channel); in dma_channel_set_irq0_enabled()
503 check_dma_channel_param(channel); in dma_channel_set_irq1_enabled()
532 check_dma_channel_param(channel); in dma_channel_is_busy()
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/lk-master/external/platform/nrfx/drivers/src/
A Dnrfx_ppi.c230 nrf_ppi_channel_t channel; in nrfx_ppi_channel_alloc() local
235 for (channel = NRF_PPI_CHANNEL0; in nrfx_ppi_channel_alloc()
237 mask &= ~nrfx_ppi_channel_to_mask(channel), channel++) in nrfx_ppi_channel_alloc()
240 if ((mask & nrfx_ppi_channel_to_mask(channel)) && (!is_allocated_channel(channel))) in nrfx_ppi_channel_alloc()
243 *p_channel = channel; in nrfx_ppi_channel_alloc()
272 channel_allocated_clr(channel); in nrfx_ppi_channel_free()
301 channel, in nrfx_ppi_channel_assign()
337 if (!is_app_channel(channel)) in nrfx_ppi_channel_enable()
341 else if (is_programmable_app_channel(channel) && !is_allocated_channel(channel)) in nrfx_ppi_channel_enable()
358 if (!is_app_channel(channel)) in nrfx_ppi_channel_disable()
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A Dnrfx_dppi.c64 static bool channel_is_allocated(uint8_t channel) in channel_is_allocated() argument
106 uint8_t channel = 0; in nrfx_dppi_channel_alloc() local
118 channel++; in nrfx_dppi_channel_alloc()
121 m_allocated_channels |= DPPI_BIT_SET(channel); in nrfx_dppi_channel_alloc()
122 *p_channel = channel; in nrfx_dppi_channel_alloc()
125 NRFX_LOG_INFO("Allocated channel: %d.", channel); in nrfx_dppi_channel_alloc()
129 nrfx_err_t nrfx_dppi_channel_free(uint8_t channel) in nrfx_dppi_channel_free() argument
133 if (!channel_is_allocated(channel)) in nrfx_dppi_channel_free()
148 nrfx_err_t nrfx_dppi_channel_enable(uint8_t channel) in nrfx_dppi_channel_enable() argument
152 if (!channel_is_allocated(channel)) in nrfx_dppi_channel_enable()
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A Dnrfx_rtc.c140 NRFX_ASSERT(channel < p_instance->cc_channel_count); in nrfx_rtc_cc_disable()
143 uint32_t int_mask = RTC_CHANNEL_INT_MASK(channel); in nrfx_rtc_cc_disable()
144 nrf_rtc_event_t event = RTC_CHANNEL_EVENT_ADDR(channel); in nrfx_rtc_cc_disable()
162 (unsigned long)channel); in nrfx_rtc_cc_disable()
169 uint32_t channel, in nrfx_rtc_cc_set() argument
174 NRFX_ASSERT(channel < p_instance->cc_channel_count); in nrfx_rtc_cc_set()
177 uint32_t int_mask = RTC_CHANNEL_INT_MASK(channel); in nrfx_rtc_cc_set()
178 nrf_rtc_event_t event = RTC_CHANNEL_EVENT_ADDR(channel); in nrfx_rtc_cc_set()
186 nrf_rtc_cc_set(p_instance->p_reg,channel, val); in nrfx_rtc_cc_set()
204 nrf_rtc_cc_set(p_instance->p_reg,channel,val); in nrfx_rtc_cc_set()
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A Dnrfx_gpiote.c152 return m_cb.handlers[channel]; in channel_handler_get()
172 uint32_t start_idx = channel ? 0 : GPIOTE_CH_NUM; in channel_port_alloc()
182 pin_in_use_by_te_set(pin, i, handler, channel); in channel_port_alloc()
295 int8_t channel = channel_port_alloc(pin, NULL, true); in nrfx_gpiote_out_init() local
297 if (channel != NO_CHANNELS) in nrfx_gpiote_out_init()
300 (uint32_t)channel, in nrfx_gpiote_out_init()
527 if (channel != NO_CHANNELS) in nrfx_gpiote_in_init()
589 nrf_gpiote_event_enable(NRF_GPIOTE, (uint32_t)channel); in nrfx_gpiote_in_event_enable()
598 nrf_gpiote_int_enable(NRF_GPIOTE, 1 << channel); in nrfx_gpiote_in_event_enable()
615 int32_t channel = (int32_t)channel_port_get(pin); in nrfx_gpiote_in_event_disable() local
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A Dnrfx_saadc.c611 if (!(m_cb.channels_activated & (1 << channel))) in nrfx_saadc_limits_set()
616 nrf_saadc_channel_limits_set(NRF_SAADC, channel, limit_low, limit_high); in nrfx_saadc_limits_set()
618 uint32_t int_mask = nrf_saadc_limit_int_get(channel, NRF_SAADC_LIMIT_LOW); in nrfx_saadc_limits_set()
621 m_cb.limits_low_activated &= ~(1 << channel); in nrfx_saadc_limits_set()
626 m_cb.limits_low_activated |= (1 << channel); in nrfx_saadc_limits_set()
630 int_mask = nrf_saadc_limit_int_get(channel, NRF_SAADC_LIMIT_HIGH); in nrfx_saadc_limits_set()
633 m_cb.limits_high_activated &= ~(1 << channel); in nrfx_saadc_limits_set()
638 m_cb.limits_high_activated |= (1 << channel); in nrfx_saadc_limits_set()
794 uint8_t channel = __CLZ(__RBIT((uint32_t)limits_activated)); in saadc_event_limits_handle() local
795 limits_activated &= ~(1 << channel); in saadc_event_limits_handle()
[all …]
A Dnrfx_timer.c256 uint32_t channel) in nrfx_timer_compare_int_enable() argument
259 NRFX_ASSERT(channel < p_instance->cc_channel_count); in nrfx_timer_compare_int_enable()
262 nrf_timer_compare_event_get(channel)); in nrfx_timer_compare_int_enable()
264 nrf_timer_compare_int_get(channel)); in nrfx_timer_compare_int_enable()
268 uint32_t channel) in nrfx_timer_compare_int_disable() argument
271 NRFX_ASSERT(channel < p_instance->cc_channel_count); in nrfx_timer_compare_int_disable()
274 nrf_timer_compare_int_get(channel)); in nrfx_timer_compare_int_disable()
/lk-master/external/platform/nrfx/helpers/
A Dnrfx_gppi.h173 __STATIC_INLINE bool nrfx_gppi_channel_check(uint8_t channel);
227 __STATIC_INLINE void nrfx_gppi_channel_endpoints_setup(uint8_t channel,
347 __STATIC_INLINE bool nrfx_gppi_channel_check(uint8_t channel) in nrfx_gppi_channel_check() argument
463 __STATIC_INLINE bool nrfx_gppi_channel_check(uint8_t channel) in nrfx_gppi_channel_check() argument
465 return nrf_dppi_channel_check(NRF_DPPIC, channel); in nrfx_gppi_channel_check()
504 nrfx_gppi_event_endpoint_setup(channel, eep); in nrfx_gppi_channel_endpoints_setup()
505 nrfx_gppi_task_endpoint_setup(channel, tep); in nrfx_gppi_channel_endpoints_setup()
511 (void)channel; in nrfx_gppi_event_endpoint_clear()
518 (void)channel; in nrfx_gppi_task_endpoint_clear()
524 nrfx_gppi_task_endpoint_setup(channel, fork_tep); in nrfx_gppi_fork_endpoint_setup()
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/lk-master/external/platform/nrfx/hal/
A Dnrf_ppi.h227 nrf_ppi_channel_t channel,
403 p_reg->CHENSET = PPI_CHENSET_CH0_Set << ((uint32_t) channel); in nrf_ppi_channel_enable()
408 p_reg->CHENCLR = PPI_CHENCLR_CH0_Clear << ((uint32_t) channel); in nrf_ppi_channel_disable()
414 if (p_reg->CHEN & (PPI_CHEN_CH0_Msk << ((uint32_t) channel))) in nrf_ppi_channel_enable_get()
444 p_reg->CH[(uint32_t) channel].EEP = eep; in nrf_ppi_channel_endpoint_setup()
445 p_reg->CH[(uint32_t) channel].TEP = tep; in nrf_ppi_channel_endpoint_setup()
452 p_reg->CH[(uint32_t) channel].EEP = eep; in nrf_ppi_event_endpoint_setup()
459 p_reg->CH[(uint32_t) channel].TEP = tep; in nrf_ppi_task_endpoint_setup()
468 p_reg->FORK[(uint32_t) channel].TEP = fork_tep; in nrf_ppi_fork_endpoint_setup()
477 nrf_ppi_channel_endpoint_setup(p_reg, channel, eep, tep); in nrf_ppi_channel_and_fork_endpoint_setup()
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A Dnrf_saadc.h607 uint8_t channel,
668 ((uint32_t)channel | SAADC_SUBSCRIBE_START_EN_Msk); in nrf_saadc_subscribe_set()
681 ((uint32_t)channel | SAADC_PUBLISH_STARTED_EN_Msk); in nrf_saadc_publish_set()
708 p_reg->CH[channel].PSELN = pseln; in nrf_saadc_channel_input_set()
709 p_reg->CH[channel].PSELP = pselp; in nrf_saadc_channel_input_set()
716 p_reg->CH[channel].PSELP = pselp; in nrf_saadc_channel_pos_input_set()
724 p_reg->CH[channel].LIMIT = ( in nrf_saadc_channel_limits_set()
752 NRFX_ASSERT(channel < SAADC_CH_NUM); in nrf_saadc_limit_int_get()
755 return mask << (channel * 2); in nrf_saadc_limit_int_get()
851 p_reg->CH[channel].CONFIG = in nrf_saadc_channel_init()
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A Dnrf_egu.h148 NRF_STATIC_INLINE nrf_egu_task_t nrf_egu_trigger_task_get(uint8_t channel);
222 NRF_STATIC_INLINE nrf_egu_int_mask_t nrf_egu_channel_int_get(uint8_t channel);
235 uint8_t channel);
257 uint8_t channel);
312 NRF_STATIC_INLINE nrf_egu_task_t nrf_egu_trigger_task_get(uint8_t channel) in nrf_egu_trigger_task_get() argument
337 NRF_STATIC_INLINE nrf_egu_event_t nrf_egu_triggered_event_get(uint8_t channel) in nrf_egu_triggered_event_get() argument
360 NRF_STATIC_INLINE nrf_egu_int_mask_t nrf_egu_channel_int_get(uint8_t channel) in nrf_egu_channel_int_get() argument
368 uint8_t channel) in nrf_egu_subscribe_set() argument
371 ((uint32_t)channel | EGU_SUBSCRIBE_TRIGGER_EN_Msk); in nrf_egu_subscribe_set()
382 uint8_t channel) in nrf_egu_publish_set() argument
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A Dnrf_dppi.h105 NRF_STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel);
146 uint8_t channel);
245 NRF_STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel) in nrf_dppi_channel_check() argument
247 NRFX_ASSERT(channel < DPPI_CH_NUM); in nrf_dppi_channel_check()
248 return ((p_reg->CHEN & (DPPIC_CHEN_CH0_Enabled << (DPPIC_CHEN_CH0_Pos + channel))) != 0); in nrf_dppi_channel_check()
268 uint8_t channel) in nrf_dppi_subscribe_set() argument
270 NRFX_ASSERT(channel < DPPI_CH_NUM); in nrf_dppi_subscribe_set()
272 ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk); in nrf_dppi_subscribe_set()
A Dnrf_timer.h374 uint8_t channel);
396 uint8_t channel);
492 NRF_STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel);
501 NRF_STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel);
628 uint8_t channel) in nrf_timer_subscribe_set() argument
631 ((uint32_t)channel | TIMER_SUBSCRIBE_START_EN_Msk); in nrf_timer_subscribe_set()
642 uint8_t channel) in nrf_timer_publish_set() argument
645 ((uint32_t)channel | TIMER_PUBLISH_COMPARE_EN_Msk); in nrf_timer_publish_set()
706 NRF_STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel) in nrf_timer_capture_task_get() argument
711 NRF_STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel) in nrf_timer_compare_event_get() argument
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A Dnrf_pwm.h368 uint8_t channel);
390 uint8_t channel);
438 NRF_STATIC_INLINE uint32_t nrf_pwm_pin_get(NRF_PWM_Type const * p_reg, uint8_t channel);
608 uint8_t channel) in nrf_pwm_subscribe_set() argument
611 ((uint32_t)channel | PWM_SUBSCRIBE_STOP_EN_Msk); in nrf_pwm_subscribe_set()
622 uint8_t channel) in nrf_pwm_publish_set() argument
625 ((uint32_t)channel | PWM_PUBLISH_STOPPED_EN_Msk); in nrf_pwm_publish_set()
655 NRF_STATIC_INLINE uint32_t nrf_pwm_pin_get(NRF_PWM_Type const * p_reg, uint8_t channel) in nrf_pwm_pin_get() argument
657 NRFX_ASSERT(channel < NRF_PWM_CHANNEL_COUNT); in nrf_pwm_pin_get()
658 return p_reg->PSEL.OUT[channel]; in nrf_pwm_pin_get()
A Dnrf_wdt.h172 uint8_t channel);
193 uint8_t channel);
346 uint8_t channel) in nrf_wdt_subscribe_set() argument
349 ((uint32_t)channel | WDT_SUBSCRIBE_START_EN_Msk); in nrf_wdt_subscribe_set()
359 uint8_t channel) in nrf_wdt_publish_set() argument
362 ((uint32_t)channel | WDT_PUBLISH_TIMEOUT_EN_Msk); in nrf_wdt_publish_set()
A Dnrf_rtc.h155 uint8_t channel);
177 uint8_t channel);
320 uint8_t channel) in nrf_rtc_subscribe_set() argument
323 ((uint32_t)channel | RTC_SUBSCRIBE_START_EN_Msk); in nrf_rtc_subscribe_set()
334 uint8_t channel) in nrf_rtc_publish_set() argument
337 ((uint32_t)channel | RTC_PUBLISH_TICK_EN_Msk); in nrf_rtc_publish_set()
A Dnrf_ipc.h239 uint8_t channel);
260 uint8_t channel);
414 uint8_t channel) in nrf_ipc_subscribe_set() argument
417 ((uint32_t)channel | IPC_SUBSCRIBE_SEND_EN_Msk); in nrf_ipc_subscribe_set()
427 uint8_t channel) in nrf_ipc_publish_set() argument
430 ((uint32_t)channel | IPC_PUBLISH_RECEIVE_EN_Msk); in nrf_ipc_publish_set()
A Dnrf_twim.h235 uint8_t channel);
257 uint8_t channel);
494 uint8_t channel) in nrf_twim_subscribe_set() argument
497 ((uint32_t)channel | TWIM_SUBSCRIBE_STARTRX_EN_Msk); in nrf_twim_subscribe_set()
508 uint8_t channel) in nrf_twim_publish_set() argument
511 ((uint32_t)channel | TWIM_PUBLISH_STOPPED_EN_Msk); in nrf_twim_publish_set()
A Dnrf_pdm.h235 uint8_t channel);
256 uint8_t channel);
479 uint8_t channel) in nrf_pdm_subscribe_set() argument
482 ((uint32_t)channel | PDM_SUBSCRIBE_START_EN_Msk); in nrf_pdm_subscribe_set()
492 uint8_t channel) in nrf_pdm_publish_set() argument
495 ((uint32_t)channel | PDM_PUBLISH_STARTED_EN_Msk); in nrf_pdm_publish_set()
A Dnrf_spis.h225 uint8_t channel);
247 uint8_t channel);
516 uint8_t channel) in nrf_spis_subscribe_set() argument
519 ((uint32_t)channel | SPIS_SUBSCRIBE_ACQUIRE_EN_Msk); in nrf_spis_subscribe_set()
530 uint8_t channel) in nrf_spis_publish_set() argument
533 ((uint32_t)channel | SPIS_PUBLISH_END_EN_Msk); in nrf_spis_publish_set()
/lk-master/external/platform/nrfx/drivers/include/
A Dnrfx_ppi.h99 nrfx_err_t nrfx_ppi_channel_free(nrf_ppi_channel_t channel);
112 nrfx_err_t nrfx_ppi_channel_assign(nrf_ppi_channel_t channel, uint32_t eep, uint32_t tep);
124 nrfx_err_t nrfx_ppi_channel_fork_assign(nrf_ppi_channel_t channel, uint32_t fork_tep);
135 nrfx_err_t nrfx_ppi_channel_enable(nrf_ppi_channel_t channel);
146 nrfx_err_t nrfx_ppi_channel_disable(nrf_ppi_channel_t channel);
177 NRFX_STATIC_INLINE uint32_t nrfx_ppi_channel_to_mask(nrf_ppi_channel_t channel);
204 NRFX_STATIC_INLINE nrfx_err_t nrfx_ppi_channel_include_in_group(nrf_ppi_channel_t channel,
296 NRFX_STATIC_INLINE uint32_t nrfx_ppi_channel_to_mask(nrf_ppi_channel_t channel) in nrfx_ppi_channel_to_mask() argument
298 return (1uL << (uint32_t) channel); in nrfx_ppi_channel_to_mask()
304 return nrfx_ppi_channels_include_in_group(nrfx_ppi_channel_to_mask(channel), group); in nrfx_ppi_channel_include_in_group()
[all …]
A Dnrfx_dppi.h72 nrfx_err_t nrfx_dppi_channel_free(uint8_t channel);
82 nrfx_err_t nrfx_dppi_channel_enable(uint8_t channel);
92 nrfx_err_t nrfx_dppi_channel_disable(uint8_t channel);
125 nrfx_err_t nrfx_dppi_channel_include_in_group(uint8_t channel,
137 nrfx_err_t nrfx_dppi_channel_remove_from_group(uint8_t channel,
A Dnrfx_timer.h224 uint32_t channel);
246 uint32_t channel);
330 uint32_t channel);
339 uint32_t channel);
349 uint32_t channel) in nrfx_timer_capture_task_address_get() argument
351 NRFX_ASSERT(channel < p_instance->cc_channel_count); in nrfx_timer_capture_task_address_get()
352 return nrf_timer_task_address_get(p_instance->p_reg, nrf_timer_capture_task_get(channel)); in nrfx_timer_capture_task_address_get()
362 uint32_t channel) in nrfx_timer_compare_event_address_get() argument
364 NRFX_ASSERT(channel < p_instance->cc_channel_count); in nrfx_timer_compare_event_address_get()
365 return nrf_timer_event_address_get(p_instance->p_reg, nrf_timer_compare_event_get(channel)); in nrfx_timer_compare_event_address_get()
/lk-master/external/platform/pico/rp2_common/hardware_dma/
A Ddma.c22 void dma_channel_claim(uint channel) { in dma_channel_claim() argument
23 check_dma_channel_param(channel); in dma_channel_claim()
24 hw_claim_or_assert((uint8_t *) &_claimed, channel, "DMA channel %d is already claimed"); in dma_channel_claim()
33 void dma_channel_unclaim(uint channel) { in dma_channel_unclaim() argument
34 check_dma_channel_param(channel); in dma_channel_unclaim()
35 hw_claim_clear((uint8_t *) &_claimed, channel); in dma_channel_unclaim()
44 void print_dma_ctrl(dma_channel_hw_t *channel) { in print_dma_ctrl() argument
45 uint32_t ctrl = channel->ctrl_trig; in print_dma_ctrl()
64 void check_dma_channel_param_impl(uint channel) { in check_dma_channel_param_impl() argument
65 valid_params_if(DMA, channel < NUM_DMA_CHANNELS); in check_dma_channel_param_impl()
/lk-master/.github/workflows/
A Dnotify-irc.yml13 channel: "#lk"
24 channel: "#lk"
34 channel: "#lk"

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