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Searched refs:clock (Results 1 – 12 of 12) sorted by relevance

/lk-master/platform/stm32f0xx/
A Drcc.c7 switch (STM32_RCC_CLK_REG(clock)) { in stm32_rcc_get_clock_en_reg()
23 switch (STM32_RCC_CLK_REG(clock)) { in stm32_rcc_get_clock_rst_reg()
38 void stm32_rcc_set_enable(stm32_rcc_clk_t clock, bool enable) { in stm32_rcc_set_enable() argument
39 __IO uint32_t *reg = stm32_rcc_get_clock_en_reg(clock); in stm32_rcc_set_enable()
41 *reg |= 1 << STM32_RCC_CLK_INDEX(clock); in stm32_rcc_set_enable()
43 *reg &= ~(1 << STM32_RCC_CLK_INDEX(clock)); in stm32_rcc_set_enable()
47 void stm32_rcc_set_reset(stm32_rcc_clk_t clock, bool reset) { in stm32_rcc_set_reset() argument
48 switch (clock) { in stm32_rcc_set_reset()
61 __IO uint32_t *reg = stm32_rcc_get_clock_rst_reg(clock); in stm32_rcc_set_reset()
63 *reg |= 1 << STM32_RCC_CLK_INDEX(clock); in stm32_rcc_set_reset()
[all …]
A Dtimer_capture.c35 stm32_rcc_clk_t clock; member
44 .clock = STM32_RCC_CLK_TIM1,
55 .clock = STM32_RCC_CLK_TIM2,
63 .clock = STM32_RCC_CLK_TIM3,
71 .clock = STM32_RCC_CLK_TIM6,
79 .clock = STM32_RCC_CLK_TIM7,
87 .clock = STM32_RCC_CLK_TIM14,
95 .clock = STM32_RCC_CLK_TIM15,
103 .clock = STM32_RCC_CLK_TIM16,
111 .clock = STM32_RCC_CLK_TIM17,
[all …]
A Di2c.c48 stm32_rcc_clk_t clock; member
63 .clock = STM32_RCC_CLK_I2C1,
70 .clock = STM32_RCC_CLK_I2C2,
92 stm32_rcc_set_enable(i2c->clock, true); in stm32_i2c_early_init()
/lk-master/target/sifive-unleashed/dt/
A Dhifive-unleashed-a00.dts31 #clock-cells = <0>;
32 compatible = "fixed-clock";
33 clock-frequency = <33333333>;
34 clock-output-names = "hfclk";
38 #clock-cells = <0>;
39 compatible = "fixed-clock";
40 clock-frequency = <RTCCLK_FREQ>;
41 clock-output-names = "rtcclk";
A Dfu540-c000.dtsi6 #include <dt-bindings/clock/sifive-fu540-prci.h>
66 clock-frequency = <0>;
91 clock-frequency = <0>;
116 clock-frequency = <0>;
159 prci: clock-controller@10000000 {
163 #clock-cells = <1>;
234 clock-names = "pclk", "hclk";
/lk-master/external/platform/pico/rp2_common/hardware_clocks/
A Dclocks.c37 clock_hw_t *clock = &clocks_hw->clk[clk_index]; in clock_stop() local
38 hw_clear_bits(&clock->ctrl, CLOCKS_CLK_USB_CTRL_ENABLE_BITS); in clock_stop()
54 clock_hw_t *clock = &clocks_hw->clk[clk_index]; in clock_configure() local
59 if (div > clock->div) in clock_configure()
60 clock->div = div; in clock_configure()
66 hw_clear_bits(&clock->ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); in clock_configure()
67 while (!(clock->selected & 1u)) in clock_configure()
90 hw_write_masked(&clock->ctrl, in clock_configure()
96 hw_write_masked(&clock->ctrl, in clock_configure()
100 while (!(clock->selected & (1u << src))) in clock_configure()
[all …]
/lk-master/external/platform/lpc15xx/lpcopen/periph_systick/example/
A Dreadme.dox2 * @brief Systick example using systick timer, the SYSTICK clock divider, and the LED
36 * timer and SYSTICK clock divider. The LED state is toggled in the systick
40 * While one would expect a clock divider to delay an interrupt occurrence this implementation
41 * seems to hasten the interrupt occurrence. For example, if the SYSTICK clock divider is set
42 * to 1, 453 interrupts occur in a 30-second interval. If the SYSTICK clock divider is set
44 * though the clock divider were really a clock multiplier.<br>
47 * In addition, once the SYSTICK clock divider is set and SYSTICK is enabled, the SYSTICK clock
48 …* divider becomes static, changes seem to have no effect. Once the clock was running, the effecti…
49 * rate could not be changed or the SYSTICK timer clock disabled as described in the UM.
/lk-master/platform/stm32f0xx/include/platform/
A Drcc.h81 void stm32_rcc_set_enable(stm32_rcc_clk_t clock, bool enable);
82 void stm32_rcc_set_reset(stm32_rcc_clk_t clock, bool reset);
/lk-master/platform/nrf52xxx/
A Drules.mk46 $(LOCAL_DIR)/clock.c \
/lk-master/external/platform/lpc15xx/lpcopen/periph_clkout/example/
A Dreadme.dox36 * clock source on the CLKOUT pin. To use this example, you'll need to
/lk-master/external/platform/lpc15xx/lpcopen/periph_freqmeas/example/
A Dreadme.dox42 * oscillator, internal RC oscillator, and the divided system clock (via the
/lk-master/external/platform/nrfx/
A DCHANGELOG.md47 - Fixed a race condition in the CLOCK driver when requested clock was stopped during ramp-up from h…
59 - Added support for 1-MHz clock frequency in TWIM.
65 - Introduced new clock management system in the CLOCK driver.
66 - Introduced new audio clock configuration settings in the I2S and PDM drivers for nRF5340.

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