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Searched refs:ddr (Results 1 – 4 of 4) sorted by relevance

/lk-master/platform/zynq/
A Dplatform.c80 SLCR_REG(DDR_PLL_CFG) = PLL_CFG_LOCK_CNT(cfg->ddr.lock_cnt) | PLL_CFG_PLL_CP(cfg->ddr.cp) | in zynq_pll_init()
81 PLL_CFG_PLL_RES(cfg->ddr.res); in zynq_pll_init()
82 SLCR_REG(DDR_PLL_CTRL) = PLL_FDIV(cfg->ddr.fdiv) | PLL_BYPASS_FORCE | PLL_RESET; in zynq_pll_init()
/lk-master/target/uzed/
A Dtarget.c24 .ddr = {
/lk-master/target/zybo/
A Dtarget.c28 .ddr = {
/lk-master/platform/zynq/include/platform/
A Dzynq.h142 zynq_pll_cfg_t ddr; member

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