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Searched refs:divisor (Results 1 – 9 of 9) sorted by relevance

/lk-master/platform/mediatek/mt6735/
A Duart.c26 unsigned int quot, divisor, remainder; in uart_setbrg() local
44 divisor = uartclk / (quot * speed); in uart_setbrg()
48 divisor += 1; in uart_setbrg()
53 mt_reg_sync_writel((divisor & 0x00ff), UART_DLL(g_uart)); in uart_setbrg()
54 mt_reg_sync_writel(((divisor >> 8)&0x00ff), UART_DLH(g_uart)); in uart_setbrg()
61 divisor = (unsigned short)tmp_div; in uart_setbrg()
66 divisor = (unsigned short)(tmp_div+1); in uart_setbrg()
68 divisor = (unsigned short)tmp_div; in uart_setbrg()
70 sample_count=divisor-1; in uart_setbrg()
/lk-master/platform/mediatek/mt6797/
A Duart.c26 unsigned int quot, divisor, remainder; in uart_setbrg() local
44 divisor = uartclk / (quot * speed); in uart_setbrg()
48 divisor += 1; in uart_setbrg()
53 mt_reg_sync_writel((divisor & 0x00ff), UART_DLL(g_uart)); in uart_setbrg()
54 mt_reg_sync_writel(((divisor >> 8)&0x00ff), UART_DLH(g_uart)); in uart_setbrg()
61 divisor = (unsigned short)tmp_div; in uart_setbrg()
66 divisor = (unsigned short)(tmp_div+1); in uart_setbrg()
68 divisor = (unsigned short)tmp_div; in uart_setbrg()
70 sample_count=divisor-1; in uart_setbrg()
/lk-master/platform/pc/
A Dtimer.c33 static uint16_t divisor; variable
115 divisor = count & 0xffff; in set_pit_frequency()
131 outp(I8253_DATA_REG, divisor & 0xff); // LSB in set_pit_frequency()
132 outp(I8253_DATA_REG, divisor >> 8); // MSB in set_pit_frequency()
166 divisor = count & 0xffff; in platform_set_oneshot_timer()
171 outp(I8253_DATA_REG, divisor & 0xff); // LSB in platform_set_oneshot_timer()
172 outp(I8253_DATA_REG, divisor >> 8); // MSB in platform_set_oneshot_timer()
A Ddebug.c54 const int divisor = 115200 / uart_baud_rate; in platform_init_debug_early() local
59 outp(uart_io_port + 0, divisor & 0xff); // lsb in platform_init_debug_early()
60 outp(uart_io_port + 1, divisor >> 8); // msb in platform_init_debug_early()
A Duart.c73 int divisor = 115200 / config->baud_rate; in uart_init() local
76 outp(config->io_port + 0, divisor & 0xff); // lsb in uart_init()
77 outp(config->io_port + 1, divisor >> 8); // msb in uart_init()
/lk-master/platform/zynq/
A Dclocks.c55 uint32_t divisor = BITS_SHIFT(SLCR_REG(ARM_CLK_CTRL), 13, 8); in get_cpu_input_freq() local
74 return srcclk / divisor; in get_cpu_input_freq()
245 …zynq_periph periph, bool enable, enum zynq_clock_source source, uint32_t divisor, uint32_t divisor… in zynq_set_clock() argument
247 DEBUG_ASSERT(!enable || (divisor > 0 && divisor <= 0x3f)); in zynq_set_clock()
264 ctrl = (ctrl & ~(0x3f << 8)) | (divisor << 8); in zynq_set_clock()
322 uint32_t divisor = BITS_SHIFT(*REG32(clk_reg), 13, 8); in zynq_get_clock() local
323 if (divisor == 0) in zynq_get_clock()
333 uint32_t clk = srcclk / divisor / divisor2; in zynq_get_clock()
/lk-master/platform/qemu-mips/
A Ddebug.c40 int divisor = 115200 / uart_baud_rate; in uart_init_early() local
44 isa_write_8(uart_io_port + 0, divisor & 0xff); // lsb in uart_init_early()
45 isa_write_8(uart_io_port + 1, divisor >> 8); // msb in uart_init_early()
/lk-master/lib/fixed_point/include/lib/
A Dfixed_point.h26 fp_32_64_div_32_32(struct fp_32_64 *result, uint32_t dividend, uint32_t divisor) { in fp_32_64_div_32_32() argument
30 tmp = ((uint64_t)dividend << 32) / divisor; in fp_32_64_div_32_32()
31 rem = ((uint64_t)dividend << 32) % divisor; in fp_32_64_div_32_32()
34 tmp = ((uint64_t)rem << 32) / divisor; in fp_32_64_div_32_32()
/lk-master/platform/zynq/include/platform/
A Dzynq.h560 status_t zynq_set_clock(enum zynq_periph, bool enable, enum zynq_clock_source, uint32_t divisor, ui…

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