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Searched refs:fpga2_clk (Results 1 – 4 of 4) sorted by relevance

/lk-master/target/uzed/
A Dtarget.c156 .fpga2_clk = CLK_CTRL_DIVISOR0(30) | CLK_CTRL_DIVISOR1(1),
/lk-master/target/zybo/
A Dtarget.c160 .fpga2_clk = CLK_CTRL_SRCSEL(2) | CLK_CTRL_DIVISOR0(53) | CLK_CTRL_DIVISOR1(2),
/lk-master/platform/zynq/
A Dplatform.c146 SLCR_REG(FPGA2_CLK_CTRL) = zynq_clk_cfg.fpga2_clk; in zynq_clk_init()
/lk-master/platform/zynq/include/platform/
A Dzynq.h134 uint32_t fpga2_clk; member

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