Searched refs:fpga3_clk (Results 1 – 4 of 4) sorted by relevance

/lk-master/target/uzed/
A D	target.c	157 .fpga3_clk = CLK_CTRL_DIVISOR0(20) | CLK_CTRL_DIVISOR1(1),
/lk-master/target/zybo/
A D	target.c	161 .fpga3_clk = CLK_CTRL_DIVISOR1(1),
/lk-master/platform/zynq/
A D	platform.c	147 SLCR_REG(FPGA3_CLK_CTRL) = zynq_clk_cfg.fpga3_clk; in zynq_clk_init()
/lk-master/platform/zynq/include/platform/
A D	zynq.h	135 uint32_t fpga3_clk; member

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Last Index update Sun Aug 20 00:18:20 CST 2023