Searched refs:mcr (Results 1 – 6 of 6) sorted by relevance
| /lk-master/arch/arm/arm/ |
| A D | cache-ops.S | 34 mcr p15, 0, r1, c1, c0, 0 // disable dcache
45 mcr p15, 0, r1, c1, c0, 0 // disable icache
47 mcr p15, 0, r12, c7, c5, 0 // invalidate icache
66 mcr p15, 0, r12, c7, c6, 0 // invalidate dcache
69 mcr p15, 0, r1, c1, c0, 0 // enable dcache
75 mcr p15, 0, r12, c7, c5, 0 // invalidate icache
79 mcr p15, 0, r1, c1, c0, 0 // enable icache
104 mcr p15, 0, r0, c1, c0, 0 // disable dcache
132 mcr p15, 0, r0, c1, c0, 0 // disable icache
171 mcr p15, 0, r0, c1, c0, 0 // enable dcache
[all …]
|
| A D | start.S | 55 mcr p15, 0, r12, c1, c0, 0
282 mcr p15, 0, r0, c8, c7, 0
288 mcr p15, 0, r12, c2, c0, 2
295 mcr p15, 0, r12, c2, c0, 0 // TTBR0
300 mcr p15, 0, r12, c3, c0, 0
313 mcr p15, 0, r12, c1, c0, 0
322 mcr p15, 0, r8, c2, c0, 0
327 mcr p15, 0, r0, c8, c7, 0
|
| A D | ops.S | 48 mcr p15, 0, r0, c7, c0, #4
57 mcr p15, 0, r0, c8, c7, 0
|
| A D | asm.S | 116 mcr p15, 0, r12, c1, c0, 0
|
| /lk-master/platform/pc/ |
| A D | debug.c | 76 const uint8_t mcr = inp(uart_io_port + 4); in platform_init_debug() local
77 outp(uart_io_port + 4, mcr | 0x8); in platform_init_debug()
|
| /lk-master/platform/bcm28xx/ |
| A D | miniuart.c | 31 uint32_t mcr; member
|
Completed in 5 milliseconds