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Searched refs:riscv_csr_set (Results 1 – 6 of 6) sorted by relevance

/lk-master/arch/riscv/
A Darch.c79 riscv_csr_set(RISCV_CSR_XIE, RISCV_CSR_XIE_SIE); in riscv_init_percpu()
83 riscv_csr_set(RISCV_CSR_XIE, RISCV_CSR_XIE_EIE); in riscv_init_percpu()
A Dtime.c35 riscv_csr_set(RISCV_CSR_XIE, RISCV_CSR_XIE_TIE); in platform_set_oneshot_timer()
A Dmmu.cpp600 riscv_csr_set(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_SUM); in riscv_mmu_init_secondaries()
/lk-master/arch/riscv/include/arch/
A Darch_ops.h17 riscv_csr_set(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_IE); in arch_enable_ints()
A Dspinlock.h59 riscv_csr_set(RISCV_CSR_XSTATUS, old_state); in arch_interrupt_restore()
A Driscv.h133 #define riscv_csr_set(csr, bits) \ macro

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