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Searched refs:uint8_t (Results 1 – 25 of 791) sorted by relevance

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/lk-master/external/platform/stm32f0xx/STM32F0xx_HAL_Driver/inc/
A Dstm32f0xx_hal_gpio_ex.h107 #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
158 #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
204 #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
262 #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U)
338 #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U)
431 #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U)
496 #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
575 #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U)
635 #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
695 #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
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/lk-master/external/platform/cc13xx/cc13xxware/driverlib/
A Drf_prop_cmd.h142 uint8_t :2;
148 uint8_t pktLen; //!< Packet length
150 uint8_t* pPkt; //!< Pointer to packet
198 uint8_t :1;
208 uint8_t address0; //!< Address
251 uint8_t :2;
332 uint8_t :1;
403 uint8_t __dummy0;
657 uint8_t :1;
667 uint8_t address0; //!< Address
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A Drom_crypto.c71 typedef int8_t(*aes_ccm_encrypt_t)(uint8_t, uint8_t, uint8_t *, uint8_t *,
76 typedef int8_t(*aes_ccm_decrypt_t)(uint8_t, uint8_t, uint8_t *, uint8_t *,
85 AES_CCM_EncryptData(uint8_t encryptFlag, uint8_t MACLen, uint8_t *nonce, in AES_CCM_EncryptData()
88 uint8_t *aesKey, uint8_t *MAC, uint8_t ccmLVal) in AES_CCM_EncryptData()
98 AES_CCM_DecryptData(uint8_t decryptFlag, uint8_t MACLen, uint8_t *nonce, in AES_CCM_DecryptData()
101 uint8_t *aesKey, uint8_t *MAC, uint8_t ccmLVal) in AES_CCM_DecryptData()
109 typedef uint8_t(*aes_ctr_encrypt_t)(uint8_t *, uint16_t, uint8_t *, uint8_t *,
113 typedef uint8_t(*aes_ctr_decrypt_t)(uint8_t *, uint16_t, uint8_t *, uint8_t *,
120 uint8_t
131 uint8_t
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A Drf_common_cmd.h121 uint8_t triggerType:4; //!< The type of trigger
147 uint8_t triggerType:4; //!< The type of trigger
173 uint8_t triggerType:4; //!< The type of trigger
231 uint8_t triggerType:4; //!< The type of trigger
250 uint8_t __dummy0;
269 uint8_t triggerType:4; //!< The type of trigger
295 uint8_t triggerType:4; //!< The type of trigger
336 uint8_t triggerType:4; //!< The type of trigger
474 uint8_t __dummy0;
476 uint8_t __dummy1;
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A Drom_crypto.h70 extern void AES_ECB_EncryptData(uint8_t *text, uint16_t textLen, uint8_t *aesKey);
106 extern int8_t AES_CCM_EncryptData(uint8_t encryptFlag, uint8_t MACLen, uint8_t *nonce,
109 uint8_t *aesKey, uint8_t *MAC, uint8_t ccmLVal);
131 extern int8_t AES_CCM_DecryptData(uint8_t decryptFlag, uint8_t MACLen, uint8_t *nonce,
134 uint8_t *aesKey, uint8_t *MAC, uint8_t ccmLVal);
149 extern uint8_t AES_CTR_EncryptData(uint8_t *plainText, uint16_t textLen,
150 uint8_t *aesKey, uint8_t *nonce,
166 extern uint8_t AES_CTR_DecryptData(uint8_t *cipherText, uint16_t textLen,
167 uint8_t *aesKey, uint8_t *nonce,
370 extern uint8_t SHA256_execute(SHA256_memory_t *config, uint8_t *pBufIn,
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A Drf_data_entry.h71 uint8_t type:2; //!< \brief Type of data entry structure<br>
76 …uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry elemen…
98 uint8_t type:2; //!< \brief Type of data entry structure<br>
103 …uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry elemen…
113 …uint8_t data; //!< First byte of the data array to be received or tr…
126 uint8_t type:2; //!< \brief Type of data entry structure<br>
131 …uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry elemen…
156 uint8_t type:2; //!< \brief Type of data entry structure<br>
161 …uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry elemen…
184 uint8_t type:2; //!< \brief Type of data entry structure<br>
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/lk-master/external/platform/lpc15xx/lpcopen/lpc_chip_15xx/inc/
A Drom_dma_15xx.h48 #define DMA_ROM_CH_HWTRIG_BURSTPOWER_1 ((uint8_t) 0 << 0)
49 #define DMA_ROM_CH_HWTRIG_BURSTPOWER_2 ((uint8_t) 1 << 0)
50 #define DMA_ROM_CH_HWTRIG_BURSTPOWER_4 ((uint8_t) 2 << 0)
51 #define DMA_ROM_CH_HWTRIG_BURSTPOWER_8 ((uint8_t) 3 << 0)
95 uint8_t event; /*!< event type selection for DMA transfer
114 uint8_t priority; /*!< priority level
117 uint8_t reserved0;
126 uint8_t ch_num; /*!< DMA channel number */
127 uint8_t config; /*!< configuration of this task
146 uint8_t data_type; /*!<
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A Drom_can_15xx.h61 uint8_t data[8];
62 uint8_t dlc;
63 uint8_t msgobj;
80 uint8_t subindex;
81 uint8_t len;
87 uint8_t subindex;
89 uint8_t *val;
93 uint8_t node_id;
107 openclose, uint8_t *length, uint8_t *data, uint8_t *last);
109 openclose, uint8_t length, uint8_t *data, uint8_t *fast_resp);
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/lk-master/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Inc/
A Dstm32f7xx_hal_sd.h105 __IO uint8_t CSDStruct; /*!< CSD structure */
106 __IO uint8_t SysSpecVersion; /*!< System specification version */
107 __IO uint8_t Reserved1; /*!< Reserved */
152 __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
155 __IO uint8_t ProdName2; /*!< Product Name part2 */
156 __IO uint8_t ProdRev; /*!< Product Revision */
158 __IO uint8_t Reserved1; /*!< Reserved1 */
160 __IO uint8_t CID_CRC; /*!< CID CRC */
161 __IO uint8_t Reserved2; /*!< Always 1 */
337 #define SD_CMD_HS_BUSTEST_READ ((uint8_t)14)
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A Dstm32f7xx_hal_cortex.h146 #define MPU_REGION_ENABLE ((uint8_t)0x01)
147 #define MPU_REGION_DISABLE ((uint8_t)0x00)
191 #define MPU_TEX_LEVEL0 ((uint8_t)0x00)
192 #define MPU_TEX_LEVEL1 ((uint8_t)0x01)
193 #define MPU_TEX_LEVEL2 ((uint8_t)0x02)
249 #define MPU_REGION_NUMBER0 ((uint8_t)0x00)
250 #define MPU_REGION_NUMBER1 ((uint8_t)0x01)
251 #define MPU_REGION_NUMBER2 ((uint8_t)0x02)
252 #define MPU_REGION_NUMBER3 ((uint8_t)0x03)
253 #define MPU_REGION_NUMBER4 ((uint8_t)0x04)
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A Dstm32f7xx_hal_cryp.h364 … HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t…
365 … HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t…
366 … HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t…
367 …HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t…
368 …HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t…
369 …HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t…
372 …HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t…
392 … HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t…
393 …HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t…
394 … HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t…
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A Dstm32f7xx_hal_gpio_ex.h79 #define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
80 #define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
85 #define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
86 #define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
87 #define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
97 #define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */
103 #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
104 #define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
105 #define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
107 #define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
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A Dstm32f7xx_hal_cryp_ex.h122 …f HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t…
123 … HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t…
125 …f HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t…
130 …AL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t…
131 …L_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t…
132 …AL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t…
133 …L_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t…
136 …L_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t…
137 …_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t…
138 …L_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t…
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/lk-master/external/platform/stm32f2xx/STM32F2xx_StdPeriph_Driver/inc/
A Dstm32f2xx_can.h381 #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
599 void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
605 uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
606 void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
611 uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
614 uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
615 uint8_t CAN_Sleep(CAN_TypeDef* CANx);
616 uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
619 uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
620 uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
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A Dstm32f2xx_syscfg.h58 #define EXTI_PortSourceGPIOA ((uint8_t)0x00)
59 #define EXTI_PortSourceGPIOB ((uint8_t)0x01)
60 #define EXTI_PortSourceGPIOC ((uint8_t)0x02)
61 #define EXTI_PortSourceGPIOD ((uint8_t)0x03)
62 #define EXTI_PortSourceGPIOE ((uint8_t)0x04)
63 #define EXTI_PortSourceGPIOF ((uint8_t)0x05)
64 #define EXTI_PortSourceGPIOG ((uint8_t)0x06)
65 #define EXTI_PortSourceGPIOH ((uint8_t)0x07)
66 #define EXTI_PortSourceGPIOI ((uint8_t)0x08)
85 #define EXTI_PinSource0 ((uint8_t)0x00)
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A Dstm32f2xx_cryp.h289 ErrorStatus CRYP_AES_ECB(uint8_t Mode,
292 uint8_t *Output);
294 ErrorStatus CRYP_AES_CBC(uint8_t Mode,
298 uint8_t *Output);
300 ErrorStatus CRYP_AES_CTR(uint8_t Mode,
307 ErrorStatus CRYP_TDES_ECB(uint8_t Mode,
312 ErrorStatus CRYP_TDES_CBC(uint8_t Mode,
319 ErrorStatus CRYP_DES_ECB(uint8_t Mode,
320 uint8_t Key[8],
324 ErrorStatus CRYP_DES_CBC(uint8_t Mode,
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A Dstm32f2xx_gpio.h193 #define GPIO_PinSource0 ((uint8_t)0x00)
194 #define GPIO_PinSource1 ((uint8_t)0x01)
195 #define GPIO_PinSource2 ((uint8_t)0x02)
196 #define GPIO_PinSource3 ((uint8_t)0x03)
197 #define GPIO_PinSource4 ((uint8_t)0x04)
198 #define GPIO_PinSource5 ((uint8_t)0x05)
199 #define GPIO_PinSource6 ((uint8_t)0x06)
200 #define GPIO_PinSource7 ((uint8_t)0x07)
201 #define GPIO_PinSource8 ((uint8_t)0x08)
202 #define GPIO_PinSource9 ((uint8_t)0x09)
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/lk-master/external/platform/stm32f4xx/STM32F4xx_StdPeriph_Driver/inc/
A Dstm32f4xx_can.h381 #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
599 void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
605 uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
606 void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
611 uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
614 uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
615 uint8_t CAN_Sleep(CAN_TypeDef* CANx);
616 uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
619 uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
620 uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
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A Dstm32f4xx_cryp.h315 ErrorStatus CRYP_AES_ECB(uint8_t Mode,
320 ErrorStatus CRYP_AES_CBC(uint8_t Mode,
326 ErrorStatus CRYP_AES_CTR(uint8_t Mode,
332 ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16],
336 uint8_t *Output, uint8_t *AuthTAG);
338 ErrorStatus CRYP_AES_CCM(uint8_t Mode,
342 uint8_t* Header, uint32_t HLength, uint8_t *HBuffer,
347 ErrorStatus CRYP_TDES_ECB(uint8_t Mode,
352 ErrorStatus CRYP_TDES_CBC(uint8_t Mode,
359 ErrorStatus CRYP_DES_ECB(uint8_t Mode,
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A Dstm32f4xx_syscfg.h58 #define EXTI_PortSourceGPIOA ((uint8_t)0x00)
59 #define EXTI_PortSourceGPIOB ((uint8_t)0x01)
60 #define EXTI_PortSourceGPIOC ((uint8_t)0x02)
61 #define EXTI_PortSourceGPIOD ((uint8_t)0x03)
62 #define EXTI_PortSourceGPIOE ((uint8_t)0x04)
63 #define EXTI_PortSourceGPIOF ((uint8_t)0x05)
64 #define EXTI_PortSourceGPIOG ((uint8_t)0x06)
65 #define EXTI_PortSourceGPIOH ((uint8_t)0x07)
66 #define EXTI_PortSourceGPIOI ((uint8_t)0x08)
67 #define EXTI_PortSourceGPIOJ ((uint8_t)0x09)
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A Dstm32f4xx_gpio.h203 #define GPIO_PinSource0 ((uint8_t)0x00)
204 #define GPIO_PinSource1 ((uint8_t)0x01)
205 #define GPIO_PinSource2 ((uint8_t)0x02)
206 #define GPIO_PinSource3 ((uint8_t)0x03)
207 #define GPIO_PinSource4 ((uint8_t)0x04)
208 #define GPIO_PinSource5 ((uint8_t)0x05)
209 #define GPIO_PinSource6 ((uint8_t)0x06)
210 #define GPIO_PinSource7 ((uint8_t)0x07)
211 #define GPIO_PinSource8 ((uint8_t)0x08)
212 #define GPIO_PinSource9 ((uint8_t)0x09)
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/lk-master/external/platform/lpc15xx/lpcopen/lpc_chip_15xx/inc/usbd/
A Dusbd.h79 uint8_t L; /**< lower byte */
80 uint8_t H; /**< upper byte */
132 uint8_t Recipient : 5; /**< Recipient type. */
133 uint8_t Type : 2; /**< Request type. */
134 uint8_t Dir : 1; /**< Direction type. */
142 uint8_t B; /**< byte wide access memeber */
422 uint8_t bLength; /**< Size of descriptor */
425 uint8_t bDeviceClass; /**< Class Code */
426 uint8_t bDeviceSubClass; /**< SubClass Code */
427 uint8_t bDeviceProtocol; /**< Protocol Code */
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/lk-master/external/platform/stm32f1xx/STM32F10x_StdPeriph_Driver/inc/
A Dstm32f10x_can.h56 uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
349 #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
547 uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
550 void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
552 uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
553 uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
554 void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
555 void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
556 uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
559 uint8_t CAN_Sleep(CAN_TypeDef* CANx);
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/lk-master/dev/bus/pci/include/dev/bus/
A Dpci.h102 uint8_t sub_class;
107 uint8_t bist;
118 uint8_t min_grant;
126 uint8_t bus;
127 uint8_t dev_fn;
131 uint8_t id;
132 uint8_t next;
136 uint8_t bus;
137 uint8_t device;
146 uint8_t slot;
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/lk-master/platform/stm32f7xx/include/platform/
A Dn25q128a.h150 #define N25Q128A_SR_WIP ((uint8_t)0x01) /*!< Write in progress */
151 #define N25Q128A_SR_WREN ((uint8_t)0x02) /*!< Write enable latch */
166 #define N25Q128A_VCR_WRAP ((uint8_t)0x03) /*!< Wrap */
167 #define N25Q128A_VCR_XIP ((uint8_t)0x08) /*!< XIP */
172 #define N25Q128A_EVCR_VPPA ((uint8_t)0x08) /*!< Vpp accelerator */
173 #define N25Q128A_EVCR_RH ((uint8_t)0x10) /*!< Reset/hold */
174 #define N25Q128A_EVCR_DUAL ((uint8_t)0x40) /*!< Dual I/O protocol */
175 #define N25Q128A_EVCR_QUAD ((uint8_t)0x80) /*!< Quad I/O protocol */
178 #define N25Q128A_FSR_PRERR ((uint8_t)0x02) /*!< Protection error */
181 #define N25Q128A_FSR_PGERR ((uint8_t)0x10) /*!< Program error */
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