Home
last modified time | relevance | path

Searched refs:vector (Results 1 – 25 of 48) sorted by relevance

12

/lk-master/platform/qemu-virt-m68k/
A Dpic.c60 return vector / 32; in irq_to_pic_num()
64 return vector % 32; in irq_to_pic_vec()
75 LTRACEF("vector %u\n", vector); in mask_interrupt()
76 write_reg(irq_to_pic_num(vector), REG_DISABLE, 1U << irq_to_pic_vec(vector)); in mask_interrupt()
81 LTRACEF("vector %u\n", vector); in unmask_interrupt()
82 write_reg(irq_to_pic_num(vector), REG_ENABLE, 1U << irq_to_pic_vec(vector)); in unmask_interrupt()
92 handlers[vector].arg = arg; in register_int_handler()
118 KEVLOG_IRQ_ENTER(vector); in m68k_platform_irq()
121 if (handlers[vector].handler) { in m68k_platform_irq()
122 ret = handlers[vector].handler(handlers[vector].arg); in m68k_platform_irq()
[all …]
/lk-master/platform/armemu/
A Dinterrupts.c33 if (vector >= PIC_MAX_INT) in mask_interrupt()
38 *REG32(PIC_MASK_LATCH) = 1 << vector; in mask_interrupt()
44 if (vector >= PIC_MAX_INT) in unmask_interrupt()
49 *REG32(PIC_UNMASK_LATCH) = 1 << vector; in unmask_interrupt()
57 if (vector == 0xffffffff) in platform_irq()
61 KEVLOG_IRQ_ENTER(vector); in platform_irq()
69 if (int_handler_table[vector].handler) in platform_irq()
70 ret = int_handler_table[vector].handler(int_handler_table[vector].arg); in platform_irq()
74 KEVLOG_IRQ_EXIT(vector); in platform_irq()
84 if (vector >= PIC_MAX_INT) in register_int_handler()
[all …]
/lk-master/platform/pc/
A Dinterrupts.c71 if (vector >= PIC1_BASE && vector < PIC1_BASE + 8) { in enable()
72 vector -= PIC1_BASE; in enable()
87 } else if (vector >= PIC2_BASE && vector < PIC2_BASE + 8) { in enable()
88 vector -= PIC2_BASE; in enable()
123 if (vector >= PIC1_BASE && vector <= PIC1_BASE + 7) { in issueEOI()
125 } else if (vector >= PIC2_BASE && vector <= PIC2_BASE + 7) { in issueEOI()
145 enable(vector, false); in mask_interrupt()
173 enable(vector, true); in unmask_interrupt()
183 unsigned int vector = frame->vector; in platform_irq() local
191 ret = int_handler_table[vector].handler(int_handler_table[vector].arg); in platform_irq()
[all …]
/lk-master/platform/qemu-virt-riscv/
A Dplic.c51 *REG32(PLIC_ENABLE(vector, riscv_current_hart())) &= ~(1 << (vector % 32)); in mask_interrupt()
56 *REG32(PLIC_ENABLE(vector, riscv_current_hart())) |= (1 << (vector % 32)); in unmask_interrupt()
63 DEBUG_ASSERT(vector < NUM_IRQS); in register_int_handler()
65 handlers[vector].handler = handler; in register_int_handler()
66 handlers[vector].arg = arg; in register_int_handler()
72 LTRACEF("vector %u\n", vector); in riscv_platform_irq()
74 if (unlikely(vector == 0)) { in riscv_platform_irq()
80 KEVLOG_IRQ_ENTER(vector); in riscv_platform_irq()
83 if (handlers[vector].handler) { in riscv_platform_irq()
84 ret = handlers[vector].handler(handlers[vector].arg); in riscv_platform_irq()
[all …]
/lk-master/platform/sifive/
A Dplic.c51 *REG32(PLIC_ENABLE(vector, riscv_current_hart())) &= ~(1 << (vector % 32)); in mask_interrupt()
56 *REG32(PLIC_ENABLE(vector, riscv_current_hart())) |= (1 << (vector % 32)); in unmask_interrupt()
63 DEBUG_ASSERT(vector < SIFIVE_NUM_IRQS); in register_int_handler()
65 handlers[vector].handler = handler; in register_int_handler()
66 handlers[vector].arg = arg; in register_int_handler()
72 LTRACEF("vector %u\n", vector); in riscv_platform_irq()
74 if (unlikely(vector == 0)) { in riscv_platform_irq()
80 KEVLOG_IRQ_ENTER(vector); in riscv_platform_irq()
83 if (handlers[vector].handler) { in riscv_platform_irq()
84 ret = handlers[vector].handler(handlers[vector].arg); in riscv_platform_irq()
[all …]
/lk-master/platform/bcm28xx/
A Dintc.c86 LTRACEF("vector %u\n", vector); in mask_interrupt()
91 if (vector >= INTERRUPT_ARM_LOCAL_CNTPSIRQ && vector <= INTERRUPT_ARM_LOCAL_CNTVIRQ) { in mask_interrupt()
100 if (vector >= ARM_IRQ0_BASE) in mask_interrupt()
118 LTRACEF("vector %u\n", vector); in unmask_interrupt()
123 if (vector >= INTERRUPT_ARM_LOCAL_CNTPSIRQ && vector <= INTERRUPT_ARM_LOCAL_CNTVIRQ) { in unmask_interrupt()
132 if (vector >= ARM_IRQ0_BASE) in unmask_interrupt()
150 if (vector >= MAX_INT) in register_int_handler()
163 uint vector; in platform_irq() local
211 vector = 0xffffffff; in platform_irq()
235 if (vector == 0xffffffff) { in platform_irq()
[all …]
/lk-master/platform/qemu-mips/
A Dintc.c92 if (vector < 8) { in enable()
106 } else if (vector < 16) { in enable()
107 vector -= 8; in enable()
140 if (vector < 8) { in issueEOI()
142 } else if (vector < 16) { in issueEOI()
173 if (vector >= INT_VECTORS) in mask_interrupt()
181 enable(vector, false); in mask_interrupt()
200 if (vector >= INT_VECTORS) in unmask_interrupt()
208 enable(vector, true); in unmask_interrupt()
234 vector = val; in platform_irq()
[all …]
/lk-master/dev/interrupt/or1k_pic/
A Dor1k_pic.c29 void register_int_handler(unsigned int vector, int_handler handler, void *arg) { in register_int_handler() argument
32 if (vector >= MAX_INT) in register_int_handler()
33 panic("%s: vector out of range %d\n", __FUNCTION__, vector); in register_int_handler()
37 int_handler_table[vector].handler = handler; in register_int_handler()
38 int_handler_table[vector].arg = arg; in register_int_handler()
43 status_t mask_interrupt(unsigned int vector) { in mask_interrupt() argument
44 if (vector >= MAX_INT) in mask_interrupt()
47 mtspr(OR1K_SPR_PIC_PICMR_ADDR, mfspr(OR1K_SPR_PIC_PICMR_ADDR) & ~(1 << vector)); in mask_interrupt()
52 status_t unmask_interrupt(unsigned int vector) { in unmask_interrupt() argument
53 if (vector >= MAX_INT) in unmask_interrupt()
[all …]
/lk-master/platform/microblaze/
A Dintc.c42 void register_int_handler(unsigned int vector, int_handler handler, void *arg) { in register_int_handler() argument
43 LTRACEF("vector %u, handler %p, arg %p\n", vector, handler, arg); in register_int_handler()
45 if (vector >= MAX_INT) in register_int_handler()
51 int_handler_table[vector].handler = handler; in register_int_handler()
52 int_handler_table[vector].arg = arg; in register_int_handler()
57 status_t mask_interrupt(unsigned int vector) { in mask_interrupt() argument
58 LTRACEF("vector %u\n", vector); in mask_interrupt()
60 INTC_REG(R_CIE) = 1 << vector; in mask_interrupt()
65 status_t unmask_interrupt(unsigned int vector) { in unmask_interrupt() argument
66 LTRACEF("vector %u\n", vector); in unmask_interrupt()
[all …]
/lk-master/dev/interrupt/arm_gic/
A Darm_gic.c81 if (vector < GIC_MAX_PER_CPU_INT) in get_int_handler()
93 if (vector >= MAX_INT) in register_int_handler()
159 int reg = vector / 32; in gic_set_enable()
216 if ((vector >= MAX_INT) || (vector < GIC_BASE_SPI)) { in gic_configure_interrupt()
227 uint32_t reg_ndx = vector >> 4; in gic_configure_interrupt()
353 if (vector >= MAX_INT) in mask_interrupt()
363 if (vector >= MAX_INT) in unmask_interrupt()
367 gic_set_enable(vector, true); in unmask_interrupt()
378 if (vector >= 0x3fe) { in __platform_irq()
384 KEVLOG_IRQ_ENTER(vector); in __platform_irq()
[all …]
/lk-master/platform/include/platform/
A Dinterrupts.h20 status_t mask_interrupt(unsigned int vector);
21 status_t unmask_interrupt(unsigned int vector);
25 void register_int_handler(unsigned int vector, int_handler handler, void *arg);
/lk-master/arch/x86/
A Dfaults.c85 printf("vector %u\n", (uint)frame->vector); in x86_unhandled_exception()
157 unsigned int vector = frame->vector; in x86_exception_handler() local
164 switch (vector) { in x86_exception_handler()
/lk-master/arch/arm/arm-m/include/arch/arm/
A Dcm.h148 static inline void arm_cm_trigger_interrupt(int vector) { in arm_cm_trigger_interrupt() argument
149 NVIC->STIR = vector; in arm_cm_trigger_interrupt()
/lk-master/arch/or1k/
A Dfaults.c77 void or1k_unhandled_exception(struct or1k_iframe *frame, uint32_t vector) { in or1k_unhandled_exception() argument
78 dprintf(CRITICAL, "unhandled exception (vector: 0x%08x)", vector); in or1k_unhandled_exception()
A Dlinker.ld11 /* vector table goes at 0 */
/lk-master/arch/microblaze/
A Dstart.S14 # start vector
A Dlinker.ld11 /* vector table goes at 0, for qemu target, at least */
/lk-master/external/arch/arm/arm-m/CMSIS/Include/
A Dcore_cm0plus.h950 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) in __NVIC_SetVector() argument
954 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; in __NVIC_SetVector()
957 …*(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to acc… in __NVIC_SetVector()
A Dcore_cm0.h832 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) in __NVIC_SetVector() argument
835 …*(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to acc… in __NVIC_SetVector()
A Dcore_cm1.h859 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) in __NVIC_SetVector() argument
862 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; in __NVIC_SetVector()
A Dcore_sc000.h910 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) in __NVIC_SetVector() argument
913 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; in __NVIC_SetVector()
/lk-master/arch/x86/include/arch/
A Dx86.h30 uint32_t vector; // pushed by stub member
39 uint64_t vector; // pushed by stub member
/lk-master/external/platform/nrfx/mdk/
A Diar_startup_nrf51.s25 ; The vector table is normally located at address 0.
28 ; it is where the SP start value is found, and the NVIC vector
A Diar_startup_nrf52805.s25 ; The vector table is normally located at address 0.
28 ; it is where the SP start value is found, and the NVIC vector
A Diar_startup_nrf5340_network.s25 ; The vector table is normally located at address 0.
28 ; it is where the SP start value is found, and the NVIC vector

Completed in 43 milliseconds

12