1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3  * Copyright 2018-2021 NXP
4  *
5  * Brief   CAAM Descriptor defines.
6  */
7 #ifndef __CAAM_DESC_DEFINES_H__
8 #define __CAAM_DESC_DEFINES_H__
9 
10 #include <util.h>
11 
12 /*
13  * Common Command constants
14  */
15 #define CMD_TYPE(cmd)		SHIFT_U32((cmd) & 0x1F, 27)
16 #define GET_CMD_TYPE(op)	((op) & (SHIFT_U32(0x1F, 27)))
17 #define CMD_CLASS(val)		SHIFT_U32((val) & 0x3, 25)
18 #define CLASS_NO		0x0
19 #define CLASS_1			0x1
20 #define CLASS_2			0x2
21 #define CLASS_DECO		0x3
22 
23 #define CMD_SGT			BIT32(24)
24 #define CMD_IMM			BIT32(23)
25 
26 /*
27  * HEADER Job Descriptor Header format
28  */
29 #define CMD_HDR_JD_TYPE		CMD_TYPE(0x16)
30 
31 /* Must be ONE */
32 #define HDR_JD_ONE		BIT32(23)
33 
34 /* Start Index if SHR = 0 */
35 #define HDR_JD_START_IDX(line)	SHIFT_U32((line) & 0x3F, 16)
36 
37 /* Descriptor Length */
38 #define HDR_JD_DESCLEN(len)	SHIFT_U32((len) & 0x7F, 0)
39 #define GET_JD_DESCLEN(entry)	((entry) & 0x7F)
40 
41 /*
42  * KEY Command fields
43  */
44 #define CMD_KEY_TYPE		CMD_TYPE(0x00)
45 
46 /* Key Destination */
47 #define KEY_DEST(val)		SHIFT_U32((KEY_DEST_##val) & 0x3, 16)
48 #define KEY_DEST_REG		0x0
49 #define KEY_DEST_PKHA_E		0x1
50 #define KEY_DEST_AFHA_SBOX	0x2
51 #define KEY_DEST_MDHA_SPLIT	0x3
52 
53 /* Plaintext Store */
54 #define KEY_PTS			BIT32(14)
55 
56 /* Key Length */
57 #define KEY_LENGTH(len)		SHIFT_U32((len) & 0x3FF, 0)
58 
59 /*
60  * LOAD Command fields
61  */
62 #define CMD_LOAD_TYPE		CMD_TYPE(0x02)
63 
64 /* Load Destination */
65 #define LOAD_DST(reg)		SHIFT_U32((reg) & 0x7F, 16)
66 
67 /* Offset in destination register */
68 #define LOAD_OFFSET(off)	SHIFT_U32((off) & 0xFF, 8)
69 
70 /* Length */
71 #define LOAD_LENGTH(len)	SHIFT_U32((len) & 0xFF, 0)
72 
73 /*
74  * STORE Command fields
75  */
76 #define CMD_STORE_TYPE		CMD_TYPE(0x0A)
77 #define CMD_STORE_SEQ_TYPE	CMD_TYPE(0x0B)
78 
79 /* Store Source */
80 #define STORE_SRC(reg)		SHIFT_U32((reg) & 0x7F, 16)
81 
82 /* Offset in source register */
83 #define STORE_OFFSET(off)	SHIFT_U32((off) & 0xFF, 8)
84 
85 /* Length */
86 #define STORE_LENGTH(len)	SHIFT_U32((len) & 0xFF, 0)
87 
88 /*
89  * Define the Load/Store Registers Source and Destination
90  */
91 #define REG_MODE			0x00
92 #define REG_KEY_SIZE			0x01
93 #define REG_DATA_SIZE			0x02
94 #define REG_ICV_SIZE			0x03
95 #define REG_DECO_MID_STATUS		0x04
96 #define REG_DECO_CTRL2			0x05
97 #define REG_CHA_CTRL			0x06
98 #define REG_DECO_CTRL			0x06
99 #define REG_IRQ_CTRL			0x07
100 #define REG_DECO_PROT_OVERWRITE		0x07
101 #define REG_CLEAR_WRITTEN		0x08
102 #define REG_MATH0			0x08
103 #define REG_MATH1			0x09
104 #define REG_MATH2			0x0A
105 #define REG_CHA_INST_SELECT		0x0A
106 #define REG_AAD_SIZE			0x0B
107 #define REG_MATH3			0x0B
108 #define REG_ALT_DATA_SIZE_C1		0x0F
109 #define REG_PKHA_A_SIZE			0x10
110 #define REG_PKHA_B_SIZE			0x11
111 #define REG_PKHA_N_SIZE			0x12
112 #define REG_PKHA_E_SIZE			0x13
113 #define REG_CTX				0x20
114 #define REG_MATH0_DW			0x30
115 #define REG_MATH1_DW			0x31
116 #define REG_MATH2_DW			0x32
117 #define REG_MATH3_DW			0x33
118 #define REG_MATH0_B			0x38
119 #define REG_MATH1_B			0x39
120 #define REG_MATH2_B			0x3A
121 #define REG_MATH3_B			0x3B
122 #define REG_KEY				0x40
123 #define REG_DECO_DESC			0x40
124 #define REG_NFIFO_n_SIZE		0x70
125 #define REG_NFIFO_MATH			0x73
126 #define REG_SIZE			0x74
127 #define REG_SIZE_MATH			0x75
128 #define REG_IFIFO_SHIFT			0x76
129 #define REG_OFIFO_SHIFT			0x77
130 #define REG_AUX_FIFO			0x78
131 #define REG_NFIFO			0x7A
132 #define REG_IFIFO			0x7C
133 #define REG_OFIFO			0x7E
134 
135 /*
136  * FIFO LOAD Command fields
137  */
138 #define CMD_FIFO_LOAD_TYPE	CMD_TYPE(0x04)
139 
140 /* Extended Length */
141 #define FIFO_LOAD_EXT		BIT32(22)
142 
143 /* Input data */
144 #define FIFO_LOAD_INPUT(reg)	SHIFT_U32((FIFO_LOAD_##reg) & 0x3F, 16)
145 #define FIFO_LOAD_ACTION(act)	SHIFT_U32((FIFO_LOAD_##act) & 0x3F, 16)
146 
147 /* Length */
148 #define FIFO_LOAD_MAX		0xFFFF
149 #define FIFO_LOAD_LENGTH(len)	SHIFT_U32((len) & FIFO_LOAD_MAX, 0)
150 
151 /*
152  * Define the FIFO Load Type Input
153  */
154 #define FIFO_LOAD_PKHA_A0		0x00
155 #define FIFO_LOAD_PKHA_A1		0x01
156 #define FIFO_LOAD_PKHA_A2		0x02
157 #define FIFO_LOAD_PKHA_A3		0x03
158 #define FIFO_LOAD_PKHA_B0		0x04
159 #define FIFO_LOAD_PKHA_B1		0x05
160 #define FIFO_LOAD_PKHA_B2		0x06
161 #define FIFO_LOAD_PKHA_B3		0x07
162 #define FIFO_LOAD_PKHA_N		0x08
163 #define FIFO_LOAD_PKHA_A		0x0C
164 #define FIFO_LOAD_PKHA_B		0x0D
165 #define FIFO_LOAD_NO_INFO_NFIFO		0x0F
166 #define FIFO_LOAD_MSG			0x10
167 #define FIFO_LOAD_MSG_C1_OUT_C2		0x18
168 #define FIFO_LOAD_IV			0x20
169 #define FIFO_LOAD_BITDATA		0x2C
170 #define FIFO_LOAD_AAD			0x30
171 #define FIFO_LOAD_ICV			0x38
172 
173 /* Define Action of some FIFO Data */
174 #define FIFO_LOAD_NOACTION		0x0
175 #define FIFO_LOAD_FLUSH			0x1
176 #define FIFO_LOAD_LAST_C1		0x2
177 #define FIFO_LOAD_LAST_C2		0x4
178 
179 /*
180  * FIFO STORE Command fields
181  */
182 #define CMD_FIFO_STORE_TYPE	CMD_TYPE(0x0C)
183 #define CMD_SEQ_FIFO_STORE_TYPE CMD_TYPE(0x0D)
184 
185 /* Extended Length */
186 #define FIFO_STORE_EXT		BIT32(22)
187 
188 /* Output data */
189 #define FIFO_STORE_OUTPUT(reg)	SHIFT_U32((FIFO_STORE_##reg) & 0x3F, 16)
190 
191 /* Length */
192 #define FIFO_STORE_MAX		0xFFFF
193 #define FIFO_STORE_LENGTH(len)	SHIFT_U32((len) & FIFO_STORE_MAX, 0)
194 
195 /*
196  * Define the FIFO Store Type Output
197  */
198 #define FIFO_STORE_PKHA_A0                           0x00
199 #define FIFO_STORE_PKHA_A1                           0x01
200 #define FIFO_STORE_PKHA_A2                           0x02
201 #define FIFO_STORE_PKHA_A3                           0x03
202 #define FIFO_STORE_PKHA_B0                           0x04
203 #define FIFO_STORE_PKHA_B1                           0x05
204 #define FIFO_STORE_PKHA_B2                           0x06
205 #define FIFO_STORE_PKHA_B3                           0x07
206 #define FIFO_STORE_PKHA_N                            0x08
207 #define FIFO_STORE_PKHA_A                            0x0C
208 #define FIFO_STORE_PKHA_B                            0x0D
209 #define FIFO_STORE_AFHA_SBOX_AES_CCM_JKEK            0x10
210 #define FIFO_STORE_AFHA_SBOX_AES_CCM_TKEK            0x11
211 #define FIFO_STORE_PKHA_E_AES_CCM_JKEK               0x12
212 #define FIFO_STORE_PKHA_E_AES_CCM_TKEK               0x13
213 #define FIFO_STORE_KEY_AES_CCM_JKEK                  0x14
214 #define FIFO_STORE_KEY_AES_CCM_TKEK                  0x15
215 #define FIFO_STORE_C2_MDHA_SPLIT_KEY_AES_CCM_JKEK    0x16
216 #define FIFO_STORE_C2_MDHA_SPLIT_KEY_AES_CCM_TKEK    0x17
217 #define FIFO_STORE_AFHA_SBOX_AES_ECB_JKEK            0x20
218 #define FIFO_STORE_AFHA_SBOX_AES_ECB_TKEK            0x21
219 #define FIFO_STORE_PKHA_E_AES_ECB_JKEK               0x22
220 #define FIFO_STORE_PKHA_E_AES_ECB_TKEK               0x23
221 #define FIFO_STORE_KEY_AES_ECB_JKEK                  0x24
222 #define FIFO_STORE_KEY_AES_ECB_TKEK                  0x25
223 #define FIFO_STORE_C2_MDHA_SPLIT_KEY_AES_ECB_JKEK    0x26
224 #define FIFO_STORE_C2_MDHA_SPLIT_KEY_AES_ECB_TKEK    0x27
225 #define FIFO_STORE_MSG_DATA                          0x30
226 #define FIFO_STORE_RNG_TO_MEM                        0x34
227 #define FIFO_STORE_RNG_STAY_FIFO                     0x35
228 #define FIFO_STORE_SKIP                              0x3F
229 
230 /*
231  * MOVE Command fields
232  */
233 #define CMD_MOVE_TYPE		CMD_TYPE(0x0F)
234 
235 /* Auxiliary */
236 #define MOVE_AUX(val)		SHIFT_U32((val) & 0x3, 25)
237 
238 /* Wait for completion */
239 #define MOVE_WC			BIT32(24)
240 
241 /* Source */
242 #define MOVE_SRC(src)			MOVE_SRC_##src
243 #define MOVE_REG_SRC(reg)		SHIFT_U32((reg) & 0xF, 20)
244 #define MOVE_SRC_C1_CTX_REG		MOVE_REG_SRC(0x0)
245 #define MOVE_SRC_C2_CTX_REG		MOVE_REG_SRC(0x1)
246 #define MOVE_SRC_OFIFO			MOVE_REG_SRC(0x2)
247 #define MOVE_SRC_DESC_BUF		MOVE_REG_SRC(0x3)
248 #define MOVE_SRC_MATH_REG0		MOVE_REG_SRC(0x4)
249 #define MOVE_SRC_MATH_REG1		MOVE_REG_SRC(0x5)
250 #define MOVE_SRC_MATH_REG2		MOVE_REG_SRC(0x6)
251 #define MOVE_SRC_MATH_REG3		MOVE_REG_SRC(0x7)
252 #define MOVE_SRC_NFIFO_DECO_ALIGN	MOVE_REG_SRC(0x8)
253 #define MOVE_SRC_NFIFO_C1_ALIGN		(MOVE_REG_SRC(0x9) | MOVE_AUX(0x1))
254 #define MOVE_SRC_NFIFO_C2_ALIGN		(MOVE_REG_SRC(0x9) | MOVE_AUX(0x0))
255 #define MOVE_SRC_DECO_ALIGN		(MOVE_REG_SRC(0xA) | MOVE_AUX(0x0))
256 #define MOVE_SRC_C1_ALIGN		(MOVE_REG_SRC(0xA) | MOVE_AUX(0x1))
257 #define MOVE_SRC_C2_ALIGN		(MOVE_REG_SRC(0xA) | MOVE_AUX(0x2))
258 #define MOVE_SRC_C1_KEY			MOVE_REG_SRC(0xD)
259 #define MOVE_SRC_C2_KEY			MOVE_REG_SRC(0xE)
260 
261 /* Destination */
262 #define MOVE_DST(dst)			SHIFT_U32((MOVE_DST_##dst), 16)
263 #define MOVE_DST_C1_CTX_REG		0x0
264 #define MOVE_DST_C2_CTX_REG		0x1
265 #define MOVE_DST_OFIFO			0x2
266 #define MOVE_DST_DESC_BUF		0x3
267 #define MOVE_DST_MATH_REG0		0x4
268 #define MOVE_DST_MATH_REG1		0x5
269 #define MOVE_DST_MATH_REG2		0x6
270 #define MOVE_DST_MATH_REG3		0x7
271 #define MOVE_DST_IFIFO_C1		0x8
272 #define MOVE_DST_IFIFO_C2		0x9
273 #define MOVE_DST_IFIFO_C2_LC2		((0x9 << 16 | MOVE_AUX(0x1)) >> 16)
274 #define MOVE_DST_IFIFO			0xA
275 #define MOVE_DST_PKHA_A			0xC
276 #define MOVE_DST_C1_KEY			0xD
277 #define MOVE_DST_C2_KEY			0xE
278 #define MOVE_DST_AUX_FIFO		0xF
279 
280 /* Offset */
281 #define MOVE_OFFSET(off)	SHIFT_U32((off) & 0xFF, 8)
282 
283 /* Length */
284 #define MOVE_LENGTH(len)	SHIFT_U32((len) & 0xFF, 0)
285 
286 /*
287  * Operation Command fields
288  * Algorithm/Protocol/PKHA
289  */
290 #define CMD_OP_TYPE		CMD_TYPE(0x10)
291 
292 /* Operation Type */
293 #define OP_TYPE(type) SHIFT_U32((OP_TYPE_##type) & 0x7, 24)
294 #define OP_TYPE_UNI		0x0
295 #define OP_TYPE_PKHA		0x1
296 #define OP_TYPE_CLASS1		0x2
297 #define OP_TYPE_CLASS2		0x4
298 #define OP_TYPE_DECAPS		0x6
299 #define OP_TYPE_ENCAPS		0x7
300 
301 /* Protocol Identifier */
302 #define PROTID(id)		SHIFT_U32((PROTID_##id) & 0xFF, 16)
303 #define PROTID_BLOB		0x0D
304 #define PROTID_MPKEY		0x14
305 #define PROTID_PKKEY		0x14
306 #define PROTID_MPSIGN		0x15
307 #define PROTID_DSASIGN		0x15
308 #define PROTID_DSAVERIFY	0x16
309 #define PROTID_SHARED_SECRET	0x17
310 #define PROTID_RSA_ENC		0x18
311 #define PROTID_RSA_DEC		0x19
312 #define PROTID_RSA_FINISH_KEY	0x1A
313 
314 /*
315  * RSA Protocol Information
316  */
317 #define PROT_RSA_FMT(format)	SHIFT_U32((PROT_RSA_FMT_##format) & 0x1, 12)
318 #define PROT_RSA_FMT_NO		0
319 #define PROT_RSA_FMT_PKCS_V1_5	1
320 
321 #define PROT_RSA_DEC_KEYFORM(format)	SHIFT_U32(((format) - 1) & 0x3, 0)
322 
323 /* RSA Key Protocol Information */
324 #define PROT_RSA_KEY(format)	SHIFT_U32((PROT_RSA_KEY_##format) & 0x3, 0)
325 #define PROT_RSA_KEY_ALL	0
326 #define PROT_RSA_KEY_N_D	2
327 
328 /*
329  * ECC Protocol Information
330  */
331 #define PROT_PK_MSG(type)	SHIFT_U32(PROT_PK_MSG_##type, 10)
332 #define PROT_PK_MSG_HASHED	2
333 #define PROT_PK_TYPE(type)	SHIFT_U32(PROT_PK_##type, 1)
334 #define PROT_PK_DL		0
335 #define PROT_PK_ECC		1
336 
337 /*
338  * BLOB Protocol Information
339  */
340 #define PROT_BLOB_FMT_MSTR		BIT32(1)
341 #define PROT_BLOB_TYPE(type)		SHIFT_U32(1, PROT_BLOB_TYPE_##type)
342 #define PROT_BLOB_TYPE_BLACK_KEY	2
343 #define PROT_BLOB_EKT			8
344 #define PROT_BLOB_INFO(aes)		SHIFT_U32(PROT_BLOB_AES_##aes, \
345 						PROT_BLOB_EKT)
346 #define PROT_BLOB_AES_CCM		1
347 #define PROT_BLOB_AES_ECB		0
348 #define PROT_BLOB_FORMAT(format)	SHIFT_U32(0, PROT_BLOB_FORMAT_##format)
349 #define PROT_BLOB_FORMAT_NORMAL		0
350 
351 /*
352  * Algorithm Identifier
353  */
354 #define OP_ALGO(algo)		SHIFT_U32((ALGO_##algo) & 0xFF, 16)
355 #define ALGO_AES		0x10
356 #define ALGO_DES		0x20
357 #define ALGO_3DES		0x21
358 #define ALGO_ARC4		0x30
359 #define ALGO_RNG		0x50
360 #define ALGO_MD5		0x40
361 #define ALGO_SHA1		0x41
362 #define ALGO_SHA224		0x42
363 #define ALGO_SHA256		0x43
364 #define ALGO_SHA384		0x44
365 #define ALGO_SHA512		0x45
366 #define ALGO_SHA512_224		0x46
367 #define ALGO_SHA512_256		0x47
368 
369 /* Algorithm Additional Information */
370 #define ALGO_AAI(info)		SHIFT_U32((AAI_##info) & 0x1FF, 4)
371 
372 /* AES AAI */
373 #define AAI_AES_CTR_MOD128	0x00
374 #define AAI_AES_CBC		0x10
375 #define AAI_AES_ECB		0x20
376 #define AAI_AES_CFB		0x30
377 #define AAI_AES_OFB		0x40
378 #define AAI_AES_CMAC		0x60
379 #define AAI_AES_XCBC_MAC	0x70
380 #define AAI_AES_CCM		0x80
381 #define AAI_AES_GCM		0x90
382 
383 /* DES AAI */
384 #define AAI_DES_CBC		0x10
385 #define AAI_DES_ECB		0x20
386 #define AAI_DES_CFB		0x30
387 #define AAI_DES_OFB		0x40
388 
389 /* Digest MD5/SHA AAI */
390 #define AAI_DIGEST_HASH		0x00
391 #define AAI_DIGEST_HMAC		0x01
392 #define AAI_DIGEST_SMAC		0x02
393 #define AAI_DIGEST_HMAC_PRECOMP	0x04
394 
395 /* Algorithm State */
396 #define ALGO_AS(state)		SHIFT_U32((AS_##state) & 0x3, 2)
397 #define AS_UPDATE		0x0
398 #define AS_INIT			0x1
399 #define AS_FINAL		0x2
400 #define AS_INIT_FINAL		0x3
401 
402 /* Algorithm Encrypt/Decrypt */
403 #define ALGO_DECRYPT		SHIFT_U32(0x0, 0)
404 #define ALGO_ENCRYPT		SHIFT_U32(0x1, 0)
405 
406 /*
407  * Specific RNG Algorithm bits 12-0
408  */
409 /* Secure Key */
410 #define ALGO_RNG_SK		BIT32(12)
411 
412 /* State Handle */
413 #define ALGO_RNG_SH(sh)		SHIFT_U32((sh) & 0x3, 4)
414 
415 /* Prediction Resistance */
416 #define ALGO_RNG_PR BIT32(1)
417 
418 /* State */
419 #define AS_RNG_GENERATE		0x0
420 #define AS_RNG_INSTANTIATE	0x1
421 #define AS_RNG_RESEED		0x2
422 #define AS_RNG_UNINSTANTIATE	0x3
423 
424 /*
425  * JUMP Command fields
426  */
427 #define CMD_JUMP_TYPE		CMD_TYPE(0x14)
428 
429 /* Jump Select Type */
430 #define JMP_JSL			BIT32(24)
431 
432 /* Jump Type */
433 #define JUMP_TYPE(type)		SHIFT_U32((JMP_##type) & 0xF, 20)
434 #define JMP_LOCAL		0x0
435 #define JMP_LOCAL_INC		0x1
436 #define JMP_SUBROUTINE_CALL	0x2
437 #define JMP_LOCAL_DEC		0x3
438 #define JMP_NON_LOCAL		0x4
439 #define JMP_SUBROUTINE_RET	0x6
440 #define JMP_HALT		0x8
441 #define JMP_HALT_USER_STATUS	0xC
442 
443 /* Test Type */
444 #define JUMP_TST_TYPE(type)	SHIFT_U32((JMP_TST_##type) & 0x3, 16)
445 #define JMP_TST_ALL_COND_TRUE	0x0
446 #define JMP_TST_ALL_COND_FALSE	0x1
447 #define JMP_TST_ANY_COND_TRUE	0x2
448 #define JMP_TST_ANY_COND_FALSE	0x3
449 
450 /* Jump Source to increment/decrement */
451 #define JMP_SRC(src)	SHIFT_U32((JMP_SRC_##src) & 0xF, 12)
452 #define JMP_SRC_MATH_0	0x0
453 
454 /* Test Condition */
455 #define JMP_COND(cond)		SHIFT_U32((JMP_COND_##cond) & 0xFF, 8)
456 #define JMP_COND_MATH(cond)	SHIFT_U32((JMP_COND_MATH_##cond) & 0xF, 8)
457 #define JMP_COND_NONE		0x00
458 #define JMP_COND_PKHA_IS_ZERO	0x80
459 #define JMP_COND_PKHA_GCD_1	0x40
460 #define JMP_COND_PKHA_IS_PRIME	0x20
461 #define JMP_COND_MATH_N		0x08
462 #define JMP_COND_MATH_Z		0x04
463 #define JMP_COND_NIFP		0x04
464 #define JMP_COND_MATH_C		0x02
465 #define JMP_COND_MATH_NV	0x01
466 
467 /* Local Offset */
468 #define JMP_LOCAL_OFFSET(off)	SHIFT_U32((off) & 0xFF, 0)
469 
470 /*
471  * MATH Command fields
472  */
473 #define CMD_MATH_TYPE		CMD_TYPE(0x15)
474 #define CMD_MATHI_TYPE		CMD_TYPE(0x1D)
475 
476 /* Immediate Four Bytes */
477 #define MATH_IFB		BIT32(26)
478 
479 /* Function Mathematical */
480 #define MATH_FUNC(func)		SHIFT_U32((MATH_FUNC_##func) & 0xF, 20)
481 #define MATH_FUNC_ADD		0x0
482 #define MATH_FUNC_ADD_W_CARRY	0x1
483 #define MATH_FUNC_SUB		0x2
484 #define MATH_FUNC_SUB_W_BORROW	0x3
485 #define MATH_FUNC_OR		0x4
486 #define MATH_FUNC_AND		0x5
487 #define MATH_FUNC_XOR		0x6
488 #define MATH_FUNC_SHIFT_L	0x7
489 #define MATH_FUNC_SHIFT_R	0x8
490 #define MATH_FUNC_SHLD		0x9
491 #define MATH_FUNC_ZBYTE		0xA
492 #define MATH_FUNC_SWAP_BYTES	0xB
493 
494 /* Source 0 */
495 #define MATH_SRC0(reg)		SHIFT_U32((MATH_SRC0_##reg) & 0xF, 16)
496 #define MATH_SRC0_REG0		0x0
497 #define MATH_SRC0_REG1		0x1
498 #define MATH_SRC0_REG2		0x2
499 #define MATH_SRC0_IMM_DATA	0x4
500 #define MATH_SRC0_DPOVRD	0x7
501 #define MATH_SRC0_SIL		0x8
502 #define MATH_SRC0_SOL		0x9
503 #define MATH_SRC0_VSIL		0xA
504 #define MATH_SRC0_VSOL		0xB
505 #define MATH_SRC0_ZERO		0xC
506 #define MATH_SRC0_ONE		0xF
507 
508 /* Source 1 */
509 #define MATH_SRC1(reg)		SHIFT_U32((MATH_SRC1_##reg) & 0xF, 12)
510 #define MATH_SRC1_REG0		0x0
511 #define MATH_SRC1_REG1		0x1
512 #define MATH_SRC1_REG2		0x2
513 #define MATH_SRC1_IMM_DATA	0x4
514 #define MATH_SRC1_DPOVRD	0x7
515 #define MATH_SRC1_VSIL		0x8
516 #define MATH_SRC1_VSOL		0x9
517 #define MATH_SRC1_IFIFO		0xA
518 #define MATH_SRC1_OFIFO		0xB
519 #define MATH_SRC1_ONE		0xC
520 #define MATH_SRC1_ZERO		0xF
521 
522 /* Destination */
523 #define MATH_DST(reg)		SHIFT_U32((MATH_DST_##reg) & 0xF, 8)
524 #define MATH_DST_REG0		0x0
525 #define MATH_DST_REG1		0x1
526 #define MATH_DST_REG2		0x2
527 #define MATH_DST_DPOVRD		0x7
528 #define MATH_DST_SIL		0x8
529 #define MATH_DST_SOL		0x9
530 #define MATH_DST_VSIL		0xA
531 #define MATH_DST_VSOL		0xB
532 #define MATH_DST_NODEST		0xF
533 
534 /* Length */
535 #define MATH_LENGTH(len)	SHIFT_U32((len) & 0xF, 0)
536 
537 /* Immediate Value - MATHI operation */
538 #define MATHI_SRC(reg)		SHIFT_U32((MATH_SRC0_##reg) & 0xF, 16)
539 #define MATHI_DST(reg)		SHIFT_U32((MATH_DST_##reg) & 0xF, 12)
540 #define MATHI_IMM_VALUE(val)	SHIFT_U32((val) & 0xFF, 4)
541 
542 /*
543  * Sequence Input/Output
544  */
545 #define CMD_SEQ_IN_TYPE		CMD_TYPE(0x1E)
546 #define CMD_SEQ_OUT_TYPE	CMD_TYPE(0x1F)
547 
548 /* Extended Length */
549 #define SEQ_EXT BIT(22)
550 
551 /* Length */
552 #define SEQ_LENGTH(len)		SHIFT_U32((len) & 0xFFFF, 0)
553 
554 /*
555  * PKHA Operation
556  */
557 #define PKHA_ALG		SHIFT_U32(0x8, 20)
558 
559 #define PKHA_F2M		BIT32(17)
560 
561 #define PKHA_OUTSEL(dst)	SHIFT_U32((PKHA_OUTSEL_##dst) & 0x3, 8)
562 #define PKHA_OUTSEL_B		0x0
563 #define PKHA_OUTSEL_A		0x1
564 
565 #define PKHA_FUNC(func)		SHIFT_U32((PKHA_FUNC_##func) & 0x3F, 0)
566 #define PKHA_FUNC_CPY_NSIZE		0x10
567 #define PKHA_FUNC_CPY_SSIZE		0x11
568 #define PKHA_FUNC_MOD_ADD_A_B		0x02
569 #define PKHA_FUNC_MOD_SUB_A_B		0x03
570 #define PKHA_FUNC_MOD_SUB_B_A		0x04
571 #define PKHA_FUNC_MOD_MUL_A_B		0x05
572 #define PKHA_FUNC_MOD_EXP_A_E		0x06
573 #define PKHA_FUNC_MOD_AMODN		0x07
574 #define PKHA_FUNC_MOD_INV_A		0x08
575 #define PKHA_FUNC_ECC_POINT_ADD_P1_P2	0x09
576 #define PKHA_FUNC_ECC_POINT_DBL_P1	0x0A
577 #define PKHA_FUNC_ECC_POINT_MUL_E_P1	0x0B
578 #define PKHA_FUNC_MONT_RADIX_R2_MODE_N	0x0C
579 #define PKHA_FUNC_GCD_A_N		0x0E
580 #define PKHA_FUNC_MR_PRIMER_TEST	0x0F
581 #define PKHA_FUNC_MOD_CHECK_POINT	0x1C
582 
583 /* PKHA Copy Memory Source and Destination */
584 #define PKHA_REG_SRC(reg)	SHIFT_U32((PKHA_REG_##reg) & 0x7, 17)
585 #define PKHA_REG_DST(reg)	SHIFT_U32((PKHA_REG_##reg) & 0x3, 10)
586 #define PKHA_REG_A		0x0
587 #define PKHA_REG_B		0x1
588 #define PKHA_REG_E		0x2
589 #define PKHA_REG_N		0x3
590 
591 #define PKHA_SEG_SRC(seg)	SHIFT_U32((seg) & 0x3, 8)
592 #define PKHA_SEG_DST(seg)	SHIFT_U32((seg) & 0x3, 6)
593 
594 #define PKHA_CPY_SRC(src)	PKHA_CPY_SRC_##src
595 #define PKHA_CPY_SRC_A0		(PKHA_REG_SRC(A) | PKHA_SEG_SRC(0))
596 #define PKHA_CPY_SRC_A1		(PKHA_REG_SRC(A) | PKHA_SEG_SRC(1))
597 #define PKHA_CPY_SRC_A2		(PKHA_REG_SRC(A) | PKHA_SEG_SRC(2))
598 #define PKHA_CPY_SRC_A3		(PKHA_REG_SRC(A) | PKHA_SEG_SRC(3))
599 #define PKHA_CPY_SRC_B0		(PKHA_REG_SRC(B) | PKHA_SEG_SRC(0))
600 #define PKHA_CPY_SRC_B1		(PKHA_REG_SRC(B) | PKHA_SEG_SRC(1))
601 #define PKHA_CPY_SRC_B2		(PKHA_REG_SRC(B) | PKHA_SEG_SRC(2))
602 #define PKHA_CPY_SRC_B3		(PKHA_REG_SRC(B) | PKHA_SEG_SRC(3))
603 #define PKHA_CPY_SRC_N0		(PKHA_REG_SRC(N) | PKHA_SEG_SRC(0))
604 #define PKHA_CPY_SRC_N1		(PKHA_REG_SRC(N) | PKHA_SEG_SRC(1))
605 #define PKHA_CPY_SRC_N2		(PKHA_REG_SRC(N) | PKHA_SEG_SRC(2))
606 #define PKHA_CPY_SRC_N3		(PKHA_REG_SRC(N) | PKHA_SEG_SRC(3))
607 
608 #define PKHA_CPY_DST(dst)	PKHA_CPY_DST_##dst
609 #define PKHA_CPY_DST_A0		(PKHA_REG_DST(A) | PKHA_SEG_DST(0))
610 #define PKHA_CPY_DST_A1		(PKHA_REG_DST(A) | PKHA_SEG_DST(1))
611 #define PKHA_CPY_DST_A2		(PKHA_REG_DST(A) | PKHA_SEG_DST(2))
612 #define PKHA_CPY_DST_A3		(PKHA_REG_DST(A) | PKHA_SEG_DST(3))
613 #define PKHA_CPY_DST_B0		(PKHA_REG_DST(B) | PKHA_SEG_DST(0))
614 #define PKHA_CPY_DST_B1		(PKHA_REG_DST(B) | PKHA_SEG_DST(1))
615 #define PKHA_CPY_DST_B2		(PKHA_REG_DST(B) | PKHA_SEG_DST(2))
616 #define PKHA_CPY_DST_B3		(PKHA_REG_DST(B) | PKHA_SEG_DST(3))
617 #define PKHA_CPY_DST_N0		(PKHA_REG_DST(N) | PKHA_SEG_DST(0))
618 #define PKHA_CPY_DST_N1		(PKHA_REG_DST(N) | PKHA_SEG_DST(1))
619 #define PKHA_CPY_DST_N2		(PKHA_REG_DST(N) | PKHA_SEG_DST(2))
620 #define PKHA_CPY_DST_N3		(PKHA_REG_DST(N) | PKHA_SEG_DST(3))
621 #define PKHA_CPY_DST_E		(PKHA_REG_DST(E))
622 
623 /*
624  * Descriptor Protocol Data Block
625  */
626 /* RSA Encryption */
627 #define PDB_RSA_ENC_SGT_F	SHIFT_U32(1, 31)
628 #define PDB_RSA_ENC_SGT_G	SHIFT_U32(1, 30)
629 #define PDB_RSA_ENC_E_SIZE(len)	SHIFT_U32((len) & 0xFFF, 12)
630 #define PDB_RSA_ENC_N_SIZE(len)	SHIFT_U32((len) & 0xFFF, 0)
631 #define PDB_RSA_ENC_F_SIZE(len)	SHIFT_U32((len) & 0xFFF, 0)
632 
633 /* RSA Decryption */
634 #define PDB_RSA_DEC_SGT_G	SHIFT_U32(1, 31)
635 #define PDB_RSA_DEC_SGT_F	SHIFT_U32(1, 30)
636 #define PDB_RSA_DEC_D_SIZE(len)	SHIFT_U32((len) & 0xFFF, 12)
637 #define PDB_RSA_DEC_N_SIZE(len)	SHIFT_U32((len) & 0xFFF, 0)
638 #define PDB_RSA_DEC_Q_SIZE(len)	SHIFT_U32((len) & 0xFFF, 12)
639 #define PDB_RSA_DEC_P_SIZE(len)	SHIFT_U32((len) & 0xFFF, 0)
640 
641 /* RSA Finalize Key */
642 #define PDB_RSA_KEY_P_SIZE(len)	SHIFT_U32((len) & 0x1FF, 0)
643 #define PDB_RSA_KEY_E_SIZE(len)	SHIFT_U32((len) & 0x3FF, 0)
644 #define PDB_RSA_KEY_N_SIZE(len)	SHIFT_U32((len) & 0x3FF, 16)
645 
646 /* Manufacturing Curve Select */
647 #define PDB_MP_CSEL_P256	0x03
648 #define PDB_MP_CSEL_P384	0x04
649 #define PDB_MP_CSEL_P521	0x05
650 
651 /* Public Key Generation */
652 #define PDB_PKGEN_PD1		SHIFT_U32(1, 25)
653 /* Public Key Signature */
654 #define PDB_PKSIGN_PD1		SHIFT_U32(1, 22)
655 /* Public Key Verify */
656 #define PDB_PKVERIFY_PD1	SHIFT_U32(1, 22)
657 /* Shared Secret */
658 #define PDB_SHARED_SECRET_PD1	SHIFT_U32(1, 25)
659 
660 /* DSA Signatures */
661 #define PDB_DSA_SIGN_N(len) SHIFT_U32((len) & (0x7F), 0)
662 #define PDB_DSA_SIGN_L(len) SHIFT_U32((len) & (0x3FF), 7)
663 
664 /* SGT Flags Signature */
665 #define PDB_SGT_PKSIGN_MSG	SHIFT_U32(1, 27)
666 #define PDB_SGT_PKSIGN_SIGN_C	SHIFT_U32(1, 26)
667 #define PDB_SGT_PKSIGN_SIGN_D	SHIFT_U32(1, 25)
668 
669 /* DSA Verify */
670 #define PDB_DSA_VERIF_N(len) SHIFT_U32((len) & (0x7F), 0)
671 #define PDB_DSA_VERIF_L(len) SHIFT_U32((len) & (0x3FF), 7)
672 
673 /* SGT Flags Verify */
674 #define PDB_SGT_PKVERIF_MSG	SHIFT_U32(1, 27)
675 #define PDB_SGT_PKVERIF_SIGN_C	SHIFT_U32(1, 26)
676 #define PDB_SGT_PKVERIF_SIGN_D	SHIFT_U32(1, 25)
677 
678 /* SGT Flags Shared Secret */
679 #define PDB_SGT_PKDH_SECRET	SHIFT_U32(1, 27)
680 
681 /* DL Keypair Generation */
682 #define PDB_DL_KEY_L_SIZE(len) SHIFT_U32((len) & (0x3FF), 7)
683 #define PDB_DL_KEY_N_MASK      0x7F
684 #define PDB_DL_KEY_N_SIZE(len) SHIFT_U32((len) & (PDB_DL_KEY_N_MASK), 0)
685 
686 /* ECC Domain Selection */
687 #define PDB_ECC_ECDSEL(curve)	SHIFT_U32((curve) & 0x3F, 7)
688 
689 /* Black key padding */
690 #define BLACK_KEY_NONCE_SIZE	6
691 #define BLACK_KEY_ICV_SIZE	6
692 
693 /*
694  * ECC Predefined Domain
695  */
696 enum caam_ecc_curve {
697 	CAAM_ECC_P192 = (0x00),
698 	CAAM_ECC_P224,
699 	CAAM_ECC_P256,
700 	CAAM_ECC_P384,
701 	CAAM_ECC_P521,
702 	CAAM_ECC_MAX,
703 	CAAM_ECC_UNKNOWN = (0xFF),
704 };
705 
706 #endif /* __CAAM_DESC_DEFINES_H__ */
707