1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Header file for the Atmel DDR/SDR SDRAM Controller 4 * 5 * Copyright (C) 2010 Atmel Corporation 6 * Nicolas Ferre <nicolas.ferre@atmel.com> 7 */ 8 9 #ifndef AT91_DDRSDR_H 10 #define AT91_DDRSDR_H 11 12 /* Mode Register */ 13 #define AT91_DDRSDRC_MR 0x00 14 /* Command Mode */ 15 #define AT91_DDRSDRC_MODE SHIFT_U32(0x7, 0) 16 #define AT91_DDRSDRC_MODE_NORMAL 0 17 #define AT91_DDRSDRC_MODE_NOP 1 18 #define AT91_DDRSDRC_MODE_PRECHARGE 2 19 #define AT91_DDRSDRC_MODE_LMR 3 20 #define AT91_DDRSDRC_MODE_REFRESH 4 21 #define AT91_DDRSDRC_MODE_EXT_LMR 5 22 #define AT91_DDRSDRC_MODE_DEEP 6 23 24 /* Refresh Timer Register */ 25 #define AT91_DDRSDRC_RTR 0x04 26 /* Refresh Timer Counter */ 27 #define AT91_DDRSDRC_COUNT SHIFT_U32(0xfff, 0) 28 29 /* Configuration Register */ 30 #define AT91_DDRSDRC_CR 0x08 31 /* Number of Column Bits */ 32 #define AT91_DDRSDRC_NC SHIFT_U32(3, 0) 33 #define AT91_DDRSDRC_NC_SDR8 SHIFT_U32(0, 0) 34 #define AT91_DDRSDRC_NC_SDR9 BIT(0) 35 #define AT91_DDRSDRC_NC_SDR10 SHIFT_U32(2, 0) 36 #define AT91_DDRSDRC_NC_SDR11 SHIFT_U32(3, 0) 37 #define AT91_DDRSDRC_NC_DDR9 SHIFT_U32(0, 0) 38 #define AT91_DDRSDRC_NC_DDR10 BIT(0) 39 #define AT91_DDRSDRC_NC_DDR11 SHIFT_U32(2, 0) 40 #define AT91_DDRSDRC_NC_DDR12 SHIFT_U32(3, 0) 41 /* Number of Row Bits */ 42 #define AT91_DDRSDRC_NR SHIFT_U32(3, 2) 43 #define AT91_DDRSDRC_NR_11 SHIFT_U32(0, 2) 44 #define AT91_DDRSDRC_NR_12 BIT(2) 45 #define AT91_DDRSDRC_NR_13 SHIFT_U32(2, 2) 46 #define AT91_DDRSDRC_NR_14 SHIFT_U32(3, 2) 47 /* CAS Latency */ 48 #define AT91_DDRSDRC_CAS SHIFT_U32(7, 4) 49 #define AT91_DDRSDRC_CAS_2 SHIFT_U32(2, 4) 50 #define AT91_DDRSDRC_CAS_3 SHIFT_U32(3, 4) 51 #define AT91_DDRSDRC_CAS_25 SHIFT_U32(6, 4) 52 /* Reset DLL */ 53 #define AT91_DDRSDRC_RST_DLL BIT(7) 54 /* Output impedance control */ 55 #define AT91_DDRSDRC_DICDS BIT(8) 56 /* Disable DLL [SAM9 Only] */ 57 #define AT91_DDRSDRC_DIS_DLL BIT(9) 58 /* Off-Chip Driver [SAM9 Only] */ 59 #define AT91_DDRSDRC_OCD BIT(12) 60 /* Mask Data is Shared [SAM9 Only] */ 61 #define AT91_DDRSDRC_DQMS BIT(16) 62 /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */ 63 #define AT91_DDRSDRC_ACTBST BIT(18) 64 65 /* Timing 0 Register */ 66 #define AT91_DDRSDRC_T0PR 0x0C 67 /* Active to Precharge delay */ 68 #define AT91_DDRSDRC_TRAS SHIFT_U32(0xf, 0) 69 /* Row to Column delay */ 70 #define AT91_DDRSDRC_TRCD SHIFT_U32(0xf, 4) 71 /* Write recovery delay */ 72 #define AT91_DDRSDRC_TWR SHIFT_U32(0xf, 8) 73 /* Row cycle delay */ 74 #define AT91_DDRSDRC_TRC SHIFT_U32(0xf, 12) 75 /* Row precharge delay */ 76 #define AT91_DDRSDRC_TRP SHIFT_U32(0xf, 16) 77 /* Active BankA to BankB */ 78 #define AT91_DDRSDRC_TRRD SHIFT_U32(0xf, 20) 79 /* Internal Write to Read delay */ 80 #define AT91_DDRSDRC_TWTR SHIFT_U32(0x7, 24) 81 /* Reduce Write to Read Delay [SAM9 Only] */ 82 #define AT91_DDRSDRC_RED_WRRD SHIFT_U32(0x1, 27) 83 /* Load mode to active/refresh delay */ 84 #define AT91_DDRSDRC_TMRD SHIFT_U32(0xf, 28) 85 86 /* Timing 1 Register */ 87 #define AT91_DDRSDRC_T1PR 0x10 88 /* Row Cycle Delay */ 89 #define AT91_DDRSDRC_TRFC SHIFT_U32(0x1f, 0) 90 /* Exit self-refresh to non-read */ 91 #define AT91_DDRSDRC_TXSNR SHIFT_U32(0xff, 8) 92 /* Exit self-refresh to read */ 93 #define AT91_DDRSDRC_TXSRD SHIFT_U32(0xff, 16) 94 /* Exit power-down delay */ 95 #define AT91_DDRSDRC_TXP SHIFT_U32(0xf, 24) 96 97 /* Timing 2 Register [SAM9 Only] */ 98 #define AT91_DDRSDRC_T2PR 0x14 99 /* Exit active power down delay to read command in mode "Fast Exit" */ 100 #define AT91_DDRSDRC_TXARD SHIFT_U32(0xf, 0) 101 /* Exit active power down delay to read command in mode "Slow Exit" */ 102 #define AT91_DDRSDRC_TXARDS SHIFT_U32(0xf, 4) 103 /* Row Precharge All delay */ 104 #define AT91_DDRSDRC_TRPA SHIFT_U32(0xf, 8) 105 /* Read to Precharge delay */ 106 #define AT91_DDRSDRC_TRTP SHIFT_U32(0x7, 12) 107 108 /* Low Power Register */ 109 #define AT91_DDRSDRC_LPR 0x1C 110 /* Low-power Configurations */ 111 #define AT91_DDRSDRC_LPCB SHIFT_U32(3, 0) 112 #define AT91_DDRSDRC_LPCB_DISABLE 0 113 #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 114 #define AT91_DDRSDRC_LPCB_POWER_DOWN 2 115 #define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 116 /* Clock Frozen */ 117 #define AT91_DDRSDRC_CLKFR BIT(2) 118 /* LPDDR Power Off */ 119 #define AT91_DDRSDRC_LPDDR2_PWOFF BIT(3) 120 /* Partial Array Self Refresh */ 121 #define AT91_DDRSDRC_PASR SHIFT_U32(7, 4) 122 /* Temperature Compensated Self Refresh */ 123 #define AT91_DDRSDRC_TCSR SHIFT_U32(3, 8) 124 /* Drive Strength */ 125 #define AT91_DDRSDRC_DS SHIFT_U32(3, 10) 126 /* Time to define when Low Power Mode is enabled */ 127 #define AT91_DDRSDRC_TIMEOUT SHIFT_U32(3, 12) 128 #define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES SHIFT_U32(0, 12) 129 #define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES BIT(12) 130 #define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES SHIFT_U32(2, 12) 131 /* Active power down exit time */ 132 #define AT91_DDRSDRC_APDE BIT(16) 133 /* Update load mode register and extended mode register */ 134 #define AT91_DDRSDRC_UPD_MR SHIFT_U32(3, 20) 135 136 /* Memory Device Register */ 137 #define AT91_DDRSDRC_MDR 0x20 138 /* Memory Device Type */ 139 #define AT91_DDRSDRC_MD SHIFT_U32(7, 0) 140 #define AT91_DDRSDRC_MD_SDR 0 141 #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 142 #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 143 #define AT91_DDRSDRC_MD_LPDDR3 5 144 /* [SAM9 Only] */ 145 #define AT91_DDRSDRC_MD_DDR2 6 146 #define AT91_DDRSDRC_MD_LPDDR2 7 147 /* Data Bus Width */ 148 #define AT91_DDRSDRC_DBW BIT(4) 149 #define AT91_DDRSDRC_DBW_32BITS SHIFT_U32(0, 4) 150 #define AT91_DDRSDRC_DBW_16BITS BIT(4) 151 152 /* DLL Information Register */ 153 #define AT91_DDRSDRC_DLL 0x24 154 /* Master Delay increment */ 155 #define AT91_DDRSDRC_MDINC BIT(0) 156 /* Master Delay decrement */ 157 #define AT91_DDRSDRC_MDDEC BIT(1) 158 /* Master Delay Overflow */ 159 #define AT91_DDRSDRC_MDOVF BIT(2) 160 /* Master Delay value */ 161 #define AT91_DDRSDRC_MDVAL SHIFT_U32(0xff, 8) 162 163 /* High Speed Register [SAM9 Only] */ 164 #define AT91_DDRSDRC_HS 0x2C 165 /* Anticip read access is disabled */ 166 #define AT91_DDRSDRC_DIS_ATCP_RD BIT(2) 167 168 /* Delay I/O Register n */ 169 #define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) 170 171 /* Write Protect Mode Register [SAM9 Only] */ 172 #define AT91_DDRSDRC_WPMR 0xE4 173 /* Write protect enable */ 174 #define AT91_DDRSDRC_WP BIT(0) 175 /* Write protect key */ 176 #define AT91_DDRSDRC_WPKEY SHIFT_U32(0xffffff, 8) 177 /* Write protect key = "DDR" */ 178 #define AT91_DDRSDRC_KEY SHIFT_U32(0x444452, 8) 179 180 /* Write Protect Status Register [SAM9 Only] */ 181 #define AT91_DDRSDRC_WPSR 0xE8 182 /* Write protect violation status */ 183 #define AT91_DDRSDRC_WPVS BIT(0) 184 /* Write protect violation source */ 185 #define AT91_DDRSDRC_WPVSRC SHIFT_U32(0xffff, 8) 186 187 #endif 188