Home
last modified time | relevance | path

Searched refs:BIT (Results 1 – 25 of 156) sorted by relevance

1234567

/optee_os-3.20.0/core/include/drivers/
A Dstm32mp13_rcc.h339 #define RCC_BDCR_LSEON BIT(0)
340 #define RCC_BDCR_LSEBYP BIT(1)
341 #define RCC_BDCR_LSERDY BIT(2)
342 #define RCC_BDCR_DIGBYP BIT(3)
345 #define RCC_BDCR_LSECSSON BIT(8)
346 #define RCC_BDCR_LSECSSD BIT(9)
349 #define RCC_BDCR_RTCCKEN BIT(20)
460 #define RCC_PLL1CR_PLLON BIT(0)
496 #define RCC_PLL2CR_PLLON BIT(0)
532 #define RCC_PLL3CR_PLLON BIT(0)
[all …]
A Dstm32mp1_rcc.h241 #define RCC_TZCR_TZEN BIT(0)
242 #define RCC_TZCR_MCKPROT BIT(1)
291 #define RCC_BDCR_LSEON BIT(0)
292 #define RCC_BDCR_LSEBYP BIT(1)
293 #define RCC_BDCR_LSERDY BIT(2)
294 #define RCC_BDCR_DIGBYP BIT(3)
309 #define RCC_PLLNCR_PLLON BIT(0)
349 #define RCC_OCENR_HSION BIT(0)
351 #define RCC_OCENR_CSION BIT(4)
353 #define RCC_OCENR_DIGBYP BIT(7)
[all …]
A Dtpm2_ptp_fifo.h35 #define TPM2_ACCESS_REQUEST_USE BIT(1)
38 #define TPM2_ACCESS_VALID BIT(7)
41 #define TPM2_STS_RESPONSE_RETRY BIT(1)
43 #define TPM2_STS_DATA_EXPECT BIT(3)
44 #define TPM2_STS_DATA_AVAIL BIT(4)
45 #define TPM2_STS_GO BIT(5)
46 #define TPM2_STS_COMMAND_READY BIT(6)
47 #define TPM2_STS_VALID BIT(7)
50 #define TPM2_STS_FAMILY_TPM2 BIT(26)
58 #define TPM2_INT_STS_VALID_INT BIT(1)
[all …]
A Dimx_wdog.h35 #define WDT_WCR_WDA BIT(5)
36 #define WDT_WCR_SRS BIT(4)
37 #define WDT_WCR_WRE BIT(3)
38 #define WDT_WCR_WDE BIT(2)
39 #define WDT_WCR_WDZST BIT(0)
58 #define WDOG_CS_CMD32EN BIT(13)
59 #define WDOG_CS_ULK BIT(11)
60 #define WDOG_CS_RCS BIT(10)
61 #define WDOG_CS_EN BIT(7)
62 #define WDOG_CS_UPDATE BIT(5)
A Dzynqmp_efuse.h44 #define ZYNQMP_EFUSE_MISC_USER_CTRL_USR_WRLK_0 BIT(0)
45 #define ZYNQMP_EFUSE_MISC_USER_CTRL_USR_WRLK_1 BIT(1)
46 #define ZYNQMP_EFUSE_MISC_USER_CTRL_USR_WRLK_2 BIT(2)
47 #define ZYNQMP_EFUSE_MISC_USER_CTRL_USR_WRLK_3 BIT(3)
48 #define ZYNQMP_EFUSE_MISC_USER_CTRL_USR_WRLK_4 BIT(4)
49 #define ZYNQMP_EFUSE_MISC_USER_CTRL_USR_WRLK_5 BIT(5)
50 #define ZYNQMP_EFUSE_MISC_USER_CTRL_USR_WRLK_6 BIT(6)
51 #define ZYNQMP_EFUSE_MISC_USER_CTRL_USR_WRLK_7 BIT(7)
A Dstpmic1.h94 #define LDO_BUCK_RANK_MASK BIT(0)
95 #define LDO_BUCK_RESET_MASK BIT(0)
121 #define ICC_EVENT_ENABLED BIT(4)
122 #define PWRCTRL_POLARITY_HIGH BIT(3)
123 #define PWRCTRL_PIN_VALID BIT(2)
129 #define PWRCTRL_PD_ACTIVE BIT(3)
130 #define PWRCTRL_PU_ACTIVE BIT(2)
131 #define WAKEUP_PD_ACTIVE BIT(1)
132 #define PONKEY_PU_ACTIVE BIT(0)
135 #define SWIN_DETECTOR_ENABLED BIT(7)
[all …]
/optee_os-3.20.0/core/drivers/clk/sam/
A Dat91_pmc.h22 #define AT91_PMC_PCK BIT(0)
23 #define AT91RM9200_PMC_UDP BIT(1)
25 #define AT91RM9200_PMC_UHP BIT(4)
28 #define AT91_PMC_PCK0 BIT(8)
29 #define AT91_PMC_PCK1 BIT(9)
30 #define AT91_PMC_PCK2 BIT(10)
31 #define AT91_PMC_PCK3 BIT(11)
32 #define AT91_PMC_PCK4 BIT(12)
33 #define AT91_PMC_HCK0 BIT(16)
34 #define AT91_PMC_HCK1 BIT(17)
[all …]
/optee_os-3.20.0/core/arch/arm/plat-rzn1/
A Drzn1_tz.h17 #define TZ_INIT_CSB_SEC BIT(7) /* CoreSight AHB */
18 #define TZ_INIT_CSA_SEC BIT(6) /* CoreSight AXI */
22 #define TZ_INIT_Z_SEC BIT(2) /* Packet Engine */
23 #define TZ_INIT_I_SEC BIT(1) /* Peripheral Group */
27 #define TZ_TARG_W_SEC BIT(14) /* RTC */
29 #define TZ_TARG_RA_SEC BIT(8) /* CoreSight */
30 #define TZ_TARG_QB_SEC BIT(7) /* System Control */
31 #define TZ_TARG_QA_SEC BIT(6) /* PG0 */
32 #define TZ_TARG_NB_SEC BIT(5) /* Packet Engine */
36 #define TZ_TARG_UB_SEC BIT(1) /* 2MB SRAM */
[all …]
/optee_os-3.20.0/core/include/drivers/sam/
A Dat91_ddr.h34 #define AT91_DDRSDRC_NC_SDR9 BIT(0)
38 #define AT91_DDRSDRC_NC_DDR10 BIT(0)
44 #define AT91_DDRSDRC_NR_12 BIT(2)
53 #define AT91_DDRSDRC_RST_DLL BIT(7)
55 #define AT91_DDRSDRC_DICDS BIT(8)
59 #define AT91_DDRSDRC_OCD BIT(12)
61 #define AT91_DDRSDRC_DQMS BIT(16)
117 #define AT91_DDRSDRC_CLKFR BIT(2)
148 #define AT91_DDRSDRC_DBW BIT(4)
174 #define AT91_DDRSDRC_WP BIT(0)
[all …]
/optee_os-3.20.0/core/include/mm/
A Dtee_mmu_types.h14 #define TEE_MATTR_VALID_BLOCK BIT(0)
15 #define TEE_MATTR_TABLE BIT(3)
16 #define TEE_MATTR_PR BIT(4)
17 #define TEE_MATTR_PW BIT(5)
18 #define TEE_MATTR_PX BIT(6)
22 #define TEE_MATTR_UR BIT(7)
23 #define TEE_MATTR_UW BIT(8)
24 #define TEE_MATTR_UX BIT(9)
31 #define TEE_MATTR_GLOBAL BIT(10)
32 #define TEE_MATTR_SECURE BIT(11)
[all …]
/optee_os-3.20.0/lib/libutee/include/
A Dpta_stm32mp_bsec.h83 #define PTA_BSEC_LOCK_PERM BIT(30)
84 #define PTA_BSEC_LOCK_SHADOW_R BIT(29)
85 #define PTA_BSEC_LOCK_SHADOW_W BIT(28)
86 #define PTA_BSEC_LOCK_SHADOW_P BIT(27)
87 #define PTA_BSEC_LOCK_ERROR BIT(26)
/optee_os-3.20.0/core/drivers/
A Dcdns_uart.c43 #define CDNS_UART_CONTROL_RXRES BIT(0)
44 #define CDNS_UART_CONTROL_TXRES BIT(1)
45 #define CDNS_UART_CONTROL_RXEN BIT(2)
46 #define CDNS_UART_CONTROL_TXEN BIT(4)
52 #define CDNS_UART_CHANNEL_STATUS_TFUL BIT(4)
53 #define CDNS_UART_CHANNEL_STATUS_TEMPTY BIT(3)
54 #define CDNS_UART_CHANNEL_STATUS_REMPTY BIT(1)
56 #define CDNS_UART_IRQ_RXTRIG BIT(0)
57 #define CDNS_UART_IRQ_RXTOUT BIT(8)
A Dstm32_tamp.c46 #define _TAMP_SECCFGR_CNT2SEC BIT(14)
47 #define _TAMP_SECCFGR_CNT1SEC BIT(15)
50 #define _TAMP_SECCFGR_BHKLOCK BIT(30)
51 #define _TAMP_SECCFGR_TAMPSEC BIT(31)
60 #define _TAMP_SMCR_DPROT BIT(31)
64 #define _TAMP_PRIVCFG_CNT2PRIV BIT(14)
65 #define _TAMP_PRIVCFG_CNT1PRIV BIT(15)
67 #define _TAMP_PRIVCFG_BKPWPRIV BIT(30)
68 #define _TAMP_PRIVCFG_TAMPPRIV BIT(31)
75 #define _TAMP_PRIVCFG_CNT2PRIV BIT(14)
[all …]
A Dpl061_gpio.c55 if (data & BIT(offset)) in pl061_get_direction()
71 io_setbits8(base_addr + GPIODIR, BIT(offset)); in pl061_set_direction()
73 io_clrbits8(base_addr + GPIODIR, BIT(offset)); in pl061_set_direction()
94 if (io_read8(base_addr + BIT(offset + 2))) in pl061_get_value()
115 io_write8(base_addr + BIT(offset + 2), BIT(offset)); in pl061_set_value()
117 io_write8(base_addr + BIT(offset + 2), 0); in pl061_set_value()
132 if (data & BIT(offset)) in pl061_get_interrupt()
149 io_setbits8(base_addr + GPIOIE, BIT(offset)); in pl061_set_interrupt()
151 io_clrbits8(base_addr + GPIOIE, BIT(offset)); in pl061_set_interrupt()
198 if (data & BIT(offset)) in pl061_get_mode_control()
[all …]
A Dstm32_i2c.c42 #define I2C_CR1_PE BIT(0)
43 #define I2C_CR1_TXIE BIT(1)
44 #define I2C_CR1_RXIE BIT(2)
48 #define I2C_CR1_TCIE BIT(6)
49 #define I2C_CR1_ERRIE BIT(7)
55 #define I2C_CR1_SBC BIT(16)
58 #define I2C_CR1_GCEN BIT(19)
92 #define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10))
93 #define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10))
127 #define I2C_ISR_TXE BIT(0)
[all …]
A Datmel_rtc.c24 #define RTC_CR_UPDCAL BIT(1)
25 #define RTC_CR_UPDTIM BIT(0)
28 #define RTC_MR_HR_MODE BIT(0)
29 #define RTC_MR_PERSIAN BIT(1)
30 #define RTC_MR_UTC BIT(2)
31 #define RTC_MR_NEGPPM BIT(4)
41 #define RTC_SR_ACKUPD BIT(0)
42 #define RTC_SR_SEC BIT(2)
49 #define RTC_VER_NVTIM BIT(0)
50 #define RTC_VER_NVCAL BIT(1)
[all …]
/optee_os-3.20.0/core/arch/arm/include/
A Darm.h16 #define MIDR_PRIMARY_PART_NUM_MASK (BIT(MIDR_PRIMARY_PART_NUM_WIDTH) - 1)
20 #define MIDR_IMPLEMENTER_MASK (BIT(MIDR_IMPLEMENTER_WIDTH) - 1)
25 #define MIDR_VARIANT_MASK (BIT(MIDR_VARIANT_WIDTH) - 1)
29 #define MIDR_REVISION_MASK (BIT(MIDR_REVISION_WIDTH) - 1)
68 #define MPIDR_MT_MASK BIT(MPIDR_MT_SHIFT)
92 #define CTR_DMINLINE_MASK (BIT(4) - 1)
109 #define ARM32_CPSR_T BIT(5)
111 #define ARM32_CPSR_F BIT(6)
112 #define ARM32_CPSR_I BIT(7)
113 #define ARM32_CPSR_A BIT(8)
[all …]
A Dffa.h86 #define FFA_MEM_ACC_RW BIT(1)
89 #define FFA_MEM_ACC_EXE BIT(3)
95 #define FFA_MEMORY_REGION_FLAG_CLEAR BIT(0)
97 #define FFA_MEMORY_REGION_FLAG_TIME_SLICE BIT(1)
99 #define FFA_MEMORY_REGION_FLAG_CLEAR_RELINQUISH BIT(2)
110 #define FFA_MEM_PERM_INSTRUCTION_PERM BIT(2)
111 #define FFA_MEM_PERM_NX BIT(2)
127 #define FFA_PARTITION_DIRECT_REQ_RECV_SUPPORT BIT(0)
128 #define FFA_PARTITION_DIRECT_REQ_SEND_SUPPORT BIT(1)
/optee_os-3.20.0/core/drivers/scmi-msg/
A Dreset_domain.h19 #define SCMI_RESET_STATE_ARCH BIT(31)
51 #define SCMI_RESET_DOMAIN_ATTR_ASYNC BIT(31)
52 #define SCMI_RESET_DOMAIN_ATTR_NOTIF BIT(30)
77 #define SCMI_RESET_DOMAIN_ASYNC BIT(2)
78 #define SCMI_RESET_DOMAIN_EXPLICIT BIT(1)
79 #define SCMI_RESET_DOMAIN_AUTO BIT(0)
96 #define SCMI_RESET_DOMAIN_DO_NOTIFY BIT(0)
A Dclock.h75 BIT(SCMI_CLOCK_RATE_SET_ASYNC_POS)
77 BIT(SCMI_CLOCK_RATE_SET_NO_DELAYED_RESPONSE_POS)
79 BIT(SCMI_CLOCK_RATE_SET_ROUND_UP_POS)
81 BIT(SCMI_CLOCK_RATE_SET_ROUND_AUTO_POS)
100 BIT(SCMI_CLOCK_CONFIG_SET_ENABLE_POS)
121 #define SCMI_CLOCK_DESCRIBE_RATES_FORMAT_MASK BIT(12)
/optee_os-3.20.0/core/arch/arm/plat-imx/
A Dimx-regs.h54 #define ARM_WFI_STAT_MASK(n) BIT(n)
56 #define ARM_WFI_STAT_MASK_7D(n) BIT(25 + ((n) & 1))
72 #define SNVS_LPCR_TOP_MASK BIT(6)
73 #define SNVS_LPCR_DP_EN_MASK BIT(5)
82 #define GPC_PGC_PCG_MASK BIT(0)
88 #define GPC_PGC_SW_PDN_PUP_REQ_CORE1_MASK BIT(1)
A Dmmdc.h22 #define MSTR_DDR3 BIT(0)
23 #define MSTR_LPDDR2 BIT(2)
24 #define MSTR_LPDDR3 BIT(3)
/optee_os-3.20.0/ldelf/include/
A Dldelf.h42 #define DUMP_MAP_READ BIT(0)
43 #define DUMP_MAP_WRITE BIT(1)
44 #define DUMP_MAP_EXEC BIT(2)
45 #define DUMP_MAP_SECURE BIT(3)
46 #define DUMP_MAP_EPHEM BIT(4)
47 #define DUMP_MAP_LDELF BIT(7)
/optee_os-3.20.0/core/arch/arm/plat-stm32mp1/drivers/
A Dstm32mp1_pwr.c13 #define PWR_CR3_USB33_EN BIT(24)
14 #define PWR_CR3_USB33_RDY BIT(26)
15 #define PWR_CR3_REG18_EN BIT(28)
16 #define PWR_CR3_REG18_RDY BIT(29)
17 #define PWR_CR3_REG11_EN BIT(30)
18 #define PWR_CR3_REG11_RDY BIT(31)
/optee_os-3.20.0/core/arch/arm/include/sm/
A Doptee_smc.h301 #define OPTEE_SMC_NSEC_CAP_UNIPROCESSOR BIT(0)
303 #define OPTEE_SMC_SEC_CAP_HAVE_RESERVED_SHM BIT(0)
305 #define OPTEE_SMC_SEC_CAP_UNREGISTERED_SHM BIT(1)
310 #define OPTEE_SMC_SEC_CAP_DYNAMIC_SHM BIT(2)
312 #define OPTEE_SMC_SEC_CAP_VIRTUALIZATION BIT(3)
314 #define OPTEE_SMC_SEC_CAP_MEMREF_NULL BIT(4)
316 #define OPTEE_SMC_SEC_CAP_ASYNC_NOTIF BIT(5)
318 #define OPTEE_SMC_SEC_CAP_RPC_ARG BIT(6)
543 #define OPTEE_SMC_ASYNC_NOTIF_VALID BIT(0)
544 #define OPTEE_SMC_ASYNC_NOTIF_PENDING BIT(1)

Completed in 63 milliseconds

1234567