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Searched refs:BIT32 (Results 1 – 25 of 54) sorted by relevance

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/optee_os-3.20.0/core/arch/arm/plat-imx/registers/
A Dimx6-dcp.h52 #define DCP_CTRL_SFTRST BIT32(31)
53 #define DCP_CTRL_CLKGATE BIT32(30)
76 #define DCP_CONTROL0_HASH_TERM BIT32(13)
77 #define DCP_CONTROL0_HASH_INIT BIT32(12)
79 #define DCP_CONTROL0_OTP_KEY BIT32(10)
80 #define DCP_CONTROL0_CIPHER_INIT BIT32(9)
81 #define DCP_CONTROL0_CIPHER_ENCRYPT BIT32(8)
82 #define DCP_CONTROL0_ENABLE_BLIT BIT32(7)
83 #define DCP_CONTROL0_ENABLE_HASH BIT32(6)
84 #define DCP_CONTROL0_ENABLE_CIPHER BIT32(5)
[all …]
A Dimx6-crm.h489 BIT32(BS_CCM_CLPCR_VSTBY)
492 BIT32(BS_CCM_CLPCR_DIS_REF_OSC)
495 BIT32(BS_CCM_CLPCR_SBYOS)
533 BIT32(BS_CCM_CISR_COSC_READY)
536 BIT32(BS_CCM_CISR_LRF_PLL)
565 BIT32(BS_CCM_CIMR_MASK_LRF_PLL)
570 BIT32(BS_CCM_CCOSR_CKO2_EN)
579 BIT32(BS_CCM_CCOSR_CLK_OUT_SEL)
582 BIT32(BS_CCM_CCOSR_CKOL_EN)
825 BIT32(BS_CCM_ANALOG_PLL_LOCK)
[all …]
A Dimx7ulp-crm.h12 #define PCC_ENABLE_CLOCK BIT32(PCC_CGC_BIT_SHIFT)
13 #define PCC_DISABLE_CLOCK BIT32(0)
/optee_os-3.20.0/core/arch/arm/include/
A Darm32.h35 #define PMCR_DP BIT32(5)
37 #define SCR_NS BIT32(0)
38 #define SCR_IRQ BIT32(1)
39 #define SCR_FIQ BIT32(2)
40 #define SCR_EA BIT32(3)
41 #define SCR_FW BIT32(4)
42 #define SCR_AW BIT32(5)
43 #define SCR_NET BIT32(6)
44 #define SCR_SCD BIT32(7)
45 #define SCR_HCE BIT32(8)
[all …]
A Darm64.h52 #define DAIFBIT_FIQ BIT32(0)
53 #define DAIFBIT_IRQ BIT32(1)
54 #define DAIFBIT_ABT BIT32(2)
55 #define DAIFBIT_DBG BIT32(3)
60 #define DAIF_F BIT32(6)
61 #define DAIF_I BIT32(7)
62 #define DAIF_A BIT32(8)
63 #define DAIF_D BIT32(9)
211 #define ESR_ABT_WNR BIT32(6)
222 #define PAR_F BIT32(0)
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_6_7/registers/
A Dctrl_regs.h14 #define MCFGR_WDE BIT32(30)
25 #define JRxMIDR_MS_LMID BIT32(31)
26 #define JRxMIDR_MS_LAMTD BIT32(17)
27 #define JRxMIDR_MS_AMTD BIT32(16)
29 #define JRxMIDR_MS_JROWN_NS BIT32(3)
32 #define JRxMIDR_LS_NONSEQ_NS BIT32(19)
34 #define JRxMIDR_LS_SEQ_NS BIT32(3)
37 #define JRxMIDR_MS_JROWN_NS BIT32(4)
40 #define JRxMIDR_LS_NONSEQ_NS BIT32(20)
42 #define JRxMIDR_LS_SEQ_NS BIT32(4)
[all …]
/optee_os-3.20.0/core/drivers/crypto/caam/hal/ls/registers/
A Dctrl_regs.h14 #define MCFGR_WDE BIT32(30)
25 #define JRxMIDR_MS_LMID BIT32(31)
26 #define JRxMIDR_MS_LAMTD BIT32(17)
27 #define JRxMIDR_MS_TZ BIT32(15)
28 #define JRxMIDR_MS_AMTD BIT32(16)
29 #define JRxMIDR_MS_JROWN_NS BIT32(3)
32 #define JRxMIDR_LS_NONSEQ_NS BIT32(19)
34 #define JRxMIDR_LS_SEQ_NS BIT32(3)
/optee_os-3.20.0/core/drivers/crypto/caam/hal/common/registers/
A Djr_regs.h46 #define JRX_JRINTR_JRI BIT32(0)
52 #define JRX_JRCFGR_LS_ICEN BIT32(1)
53 #define JRX_JRCFGR_LS_IMSK BIT32(0)
63 #define JRX_JRCR_PARK BIT32(1)
64 #define JRX_JRCR_RESET BIT32(0)
68 #define JRX_CSTA_TRNG_IDLE BIT32(2)
69 #define JRX_CSTA_IDLE BIT32(1)
70 #define JRX_CSTA_BSY BIT32(0)
A Drng_regs.h17 #define TRNG_MCTL_PRGM BIT32(16)
18 #define TRNG_MCTL_ERR BIT32(12)
19 #define TRNG_MCTL_ACC BIT32(5)
115 #define RNG_STA_SKVN BIT32(30)
116 #define RNG_STA_IF1 BIT32(1)
117 #define RNG_STA_IF0 BIT32(0)
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_8m/registers/
A Dctrl_regs.h14 #define MCFGR_WDE BIT32(30)
23 #define JRxDID_MS_LDID BIT32(31)
25 #define JRxDID_MS_LAMTD BIT32(17)
26 #define JRxDID_MS_AMTD BIT32(16)
27 #define JRxDID_MS_TZ_OWN BIT32(15)
28 #define JRxDID_MS_PRIM_TZ BIT32(4)
35 #define BM_SCFGR_MPMRL BIT32(26)
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_8ulp/registers/
A Dctrl_regs.h14 #define MCFGR_WDE BIT32(30)
23 #define JRxDID_MS_LDID BIT32(31)
25 #define JRxDID_MS_LAMTD BIT32(17)
26 #define JRxDID_MS_AMTD BIT32(16)
27 #define JRxDID_MS_TZ_OWN BIT32(15)
28 #define JRxDID_MS_PRIM_TZ BIT32(4)
35 #define BM_SCFGR_MPMRL BIT32(26)
/optee_os-3.20.0/core/drivers/crypto/caam/include/
A Dcaam_desc_ccb_defines.h11 #define CCTRL_ULOAD_PKHA_B BIT32(27)
12 #define CCTRL_ULOAD_PKHA_A BIT32(26)
15 #define CLR_WR_IFIFO_NFIFO BIT32(31)
16 #define CLR_WR_RST_C2_CHA BIT32(28)
17 #define CLR_WR_RST_C2_DSZ BIT32(18)
25 #define NFIFO_LC2 BIT32(29)
26 #define NFIFO_LC1 BIT32(28)
27 #define NFIFO_FC1 BIT32(26)
A Dcaam_trace.h28 #define DBG_TRACE_HAL BIT32(0) /* HAL trace */
29 #define DBG_TRACE_CTRL BIT32(1) /* Controller trace */
32 #define DBG_TRACE_PWR BIT32(4) /* Power trace */
33 #define DBG_TRACE_JR BIT32(5) /* Job Ring trace */
34 #define DBG_TRACE_RNG BIT32(6) /* RNG trace */
35 #define DBG_TRACE_HASH BIT32(7) /* Hash trace */
36 #define DBG_TRACE_RSA BIT32(8) /* RSA trace */
38 #define DBG_TRACE_BLOB BIT32(10) /* BLOB trace */
40 #define DBG_TRACE_ECC BIT32(12) /* ECC trace */
41 #define DBG_TRACE_DH BIT32(13) /* DH trace */
[all …]
A Dcaam_desc_defines.h23 #define CMD_SGT BIT32(24)
24 #define CMD_IMM BIT32(23)
32 #define HDR_JD_ONE BIT32(23)
54 #define KEY_PTS BIT32(14)
141 #define FIFO_LOAD_EXT BIT32(22)
239 #define MOVE_WC BIT32(24)
410 #define ALGO_RNG_SK BIT32(12)
416 #define ALGO_RNG_PR BIT32(1)
430 #define JMP_JSL BIT32(24)
477 #define MATH_IFB BIT32(26)
[all …]
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_8q/registers/
A Dctrl_regs.h18 #define JRxDID_MS_LDID BIT32(31)
20 #define JRxDID_MS_LAMTD BIT32(17)
21 #define JRxDID_MS_AMTD BIT32(16)
22 #define JRxDID_MS_TZ_OWN BIT32(15)
23 #define JRxDID_MS_PRIM_TZ BIT32(4)
30 #define BM_SCFGR_MPMRL BIT32(26)
/optee_os-3.20.0/core/arch/arm/include/kernel/
A Dtz_ssvce_def.h86 #define PL310_CTRL_ENABLE_BIT BIT32(0)
87 #define PL310_AUX_16WAY_BIT BIT32(16)
108 #define SCU_ACCESS_CONTROL_CPU0 BIT32(0)
109 #define SCU_ACCESS_CONTROL_CPU1 BIT32(1)
110 #define SCU_ACCESS_CONTROL_CPU2 BIT32(2)
111 #define SCU_ACCESS_CONTROL_CPU3 BIT32(3)
/optee_os-3.20.0/core/include/drivers/
A Datmel_shdwc.h29 #define AT91_SHDW_RTCWKEN BIT32(17)
35 #define AT91_SHDW_WKUPIS(x) (BIT32((x) + AT91_SHDW_WKUPIS_SHIFT))
40 #define AT91_SHDW_WKUPEN(x) (BIT32(x) & AT91_SHDW_WKUPEN_MASK)
43 #define AT91_SHDW_WKUPT(x) (BIT32((x) + AT91_SHDW_WKUPT_SHIFT))
/optee_os-3.20.0/lib/libutee/include/
A Dpta_system.h54 #define PTA_SYSTEM_MAP_FLAG_SHAREABLE BIT32(0)
56 #define PTA_SYSTEM_MAP_FLAG_WRITEABLE BIT32(1)
58 #define PTA_SYSTEM_MAP_FLAG_EXECUTABLE BIT32(2)
A Dpta_scmi_client.h76 #define PTA_SCMI_CAPS_SMT_HEADER BIT32(0)
79 #define PTA_SCMI_CAPS_MSG_HEADER BIT32(1)
/optee_os-3.20.0/ldelf/include/
A Dldelf.h105 #define LDELF_MAP_FLAG_SHAREABLE BIT32(0)
106 #define LDELF_MAP_FLAG_WRITEABLE BIT32(1)
107 #define LDELF_MAP_FLAG_EXECUTABLE BIT32(2)
108 #define LDELF_MAP_FLAG_BTI BIT32(3)
/optee_os-3.20.0/core/arch/arm/plat-sunxi/
A Dpsci.c101 io_clrbits32(cpucfg + REG_CPUCFG_GEN_CTRL, BIT32(core_idx)); in psci_cpu_on()
105 io_clrbits32(cpucfg + REG_CPUCFG_DBG_CTRL1, BIT32(core_idx)); in psci_cpu_on()
118 io_clrbits32(base + REG_PRCM_CPU_PWROFF, BIT32(core_idx)); in psci_cpu_on()
127 io_setbits32(cpucfg + REG_CPUCFG_DBG_CTRL1, BIT32(core_idx)); in psci_cpu_on()
154 io_setbits32(base + REG_PRCM_CPU_PWROFF, BIT32(core_id)); in psci_cpu_off()
/optee_os-3.20.0/core/arch/arm/plat-stm/
A Drng_support.c19 #define RNG_STATUS_ERR0 BIT32(0)
20 #define RNG_STATUS_ERR1 BIT32(1)
21 #define RNG_STATUS_FULL BIT32(5)
/optee_os-3.20.0/core/arch/arm/plat-imx/pm/
A Dpsci.c79 val |= BIT32(SRC_A7RCR1_A7_CORE1_ENABLE_OFFSET + in psci_cpu_on()
88 val |= BIT32(SRC_SCR_CORE1_ENABLE_OFFSET + (core_idx - 1)); in psci_cpu_on()
89 val |= BIT32(SRC_SCR_CORE1_RST_OFFSET + (core_idx - 1)); in psci_cpu_on()
146 val &= ~BIT32(SRC_A7RCR1_A7_CORE1_ENABLE_OFFSET + (cpu - 1)); in psci_affinity_info()
154 val &= ~BIT32(SRC_SCR_CORE1_ENABLE_OFFSET + cpu - 1); in psci_affinity_info()
155 val |= BIT32(SRC_SCR_CORE1_RST_OFFSET + cpu - 1); in psci_affinity_info()
/optee_os-3.20.0/core/drivers/
A Dimx_snvs.c32 #define SNVS_HPLR_MKS_SL BIT32(9)
34 #define SNVS_LPLR_MKS_HL BIT32(9)
36 #define SNVS_HPCOMR_MKS_EN BIT32(13)
37 #define SNVS_HPCOMR_NPSWA_EN BIT32(31)
A Datmel_rstc.c17 #define AT91_RSTC_CR_PROCRST BIT32(0)
18 #define AT91_RSTC_CR_PERRST BIT32(2)

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