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Searched refs:BITS_WITH_WMASK (Results 1 – 4 of 4) sorted by relevance

/optee_os-3.20.0/core/arch/arm/plat-rockchip/
A Dcru.h44 #define PLL_POWER_UP BITS_WITH_WMASK(0, 1, 13)
45 #define PLL_POWER_DOWN BITS_WITH_WMASK(1, 1, 13)
49 #define PLL_SLOW_MODE(pll) BITS_WITH_WMASK(0, 1, PLL_MODE_BIT(pll))
50 #define PLL_NORM_MODE(pll) BITS_WITH_WMASK(1, 1, PLL_MODE_BIT(pll))
A Dpsci_rk322x.c71 BITS_WITH_WMASK(clks_gating_table[i], 0xffff, 0)); in clks_disable()
82 BITS_WITH_WMASK(dram_d.cru_clkgate[i], 0xffff, 0)); in clks_restore()
136 io_write32(va_base + CRU_CLKSEL_CON(0), BITS_WITH_WMASK(0, 0x1f, 0)); in plls_power_down()
138 BITS_WITH_WMASK(0, 0xf, 0) | BITS_WITH_WMASK(0, 0x7, 4)); in plls_power_down()
142 BITS_WITH_WMASK(0, 0x1f, 0) | BITS_WITH_WMASK(0, 0x3, 8) | in plls_power_down()
143 BITS_WITH_WMASK(0, 0x7, 12)); in plls_power_down()
146 io_write32(va_base + CRU_CLKSEL_CON(0), BITS_WITH_WMASK(0, 0x1f, 8)); in plls_power_down()
148 BITS_WITH_WMASK(0, 0x3, 8) | BITS_WITH_WMASK(0, 0x7, 12)); in plls_power_down()
152 BITS_WITH_WMASK(732, 0x3fff, 0) | in plls_power_down()
153 BITS_WITH_WMASK(2, 0x3, 14)); in plls_power_down()
A Dplatform_rk3399.c39 BITS_WITH_WMASK(st_mb, SGRF_DDR_RGN_0_16_WMSK, 0)); in platform_secure_ddr_region()
43 BITS_WITH_WMASK((ed_mb - 1), SGRF_DDR_RGN_0_16_WMSK, 0)); in platform_secure_ddr_region()
A Dcommon.h24 #define BITS_WITH_WMASK(bits, msk, shift) \ macro

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