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Searched refs:CACHELINE_LEN (Results 1 – 6 of 6) sorted by relevance

/optee_os-3.20.0/core/drivers/
A Dversal_mbox.c209 CACHELINE_LEN)) { in versal_mbox_write_req()
215 if (!IS_ALIGNED(cmd->ibuf[i].mem.alloc_len, CACHELINE_LEN)) { in versal_mbox_write_req()
255 CACHELINE_LEN)) { in versal_mbox_read_rsp()
261 if (!IS_ALIGNED(cmd->ibuf[i].mem.alloc_len, CACHELINE_LEN)) { in versal_mbox_read_rsp()
278 mem->buf = memalign(CACHELINE_LEN, ROUNDUP(len, CACHELINE_LEN)); in versal_mbox_alloc()
282 memset(mem->buf, 0, ROUNDUP(len, CACHELINE_LEN)); in versal_mbox_alloc()
287 mem->alloc_len = ROUNDUP(len, CACHELINE_LEN); in versal_mbox_alloc()
A Dversal_nvm.c26 #define __aligned_efuse __aligned(CACHELINE_LEN)
/optee_os-3.20.0/core/arch/arm/plat-versal/
A Dplatform_config.h12 #define CACHELINE_LEN 64 macro
13 #define STACK_ALIGNMENT CACHELINE_LEN
/optee_os-3.20.0/core/include/drivers/
A Dzynqmp_pm.h32 #define ZYNQMP_EFUSE_MEM(_id) (ROUNDUP(ZYNQMP_EFUSE_LEN(_id), CACHELINE_LEN))
35 #define __aligned_efuse __aligned(CACHELINE_LEN)
A Dversal_puf.h69 #define __aligned_puf __aligned(CACHELINE_LEN)
/optee_os-3.20.0/core/arch/arm/plat-zynqmp/
A Dplatform_config.h35 #define CACHELINE_LEN 64 macro
36 #define STACK_ALIGNMENT CACHELINE_LEN

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