CLK_SET_RATE_GATE (reference) in projects: optee_os-3.20.0

Searched refs:CLK_SET_RATE_GATE (Results 1 – 11 of 11) sorted by relevance

/optee_os-3.20.0/core/drivers/clk/sam/
A D	at91_plldiv.c	`57 clk->flags = CLK_SET_RATE_GATE; in at91_clk_register_plldiv()`
A D	at91_h32mx.c	`68 clk->flags = CLK_SET_RATE_GATE; in at91_clk_register_h32mx()`
A D	at91_audio_pll.c	`315 clk->flags = CLK_SET_RATE_GATE; in at91_clk_register_audio_pll_frac() 346 clk->flags = CLK_SET_RATE_GATE \| CLK_SET_PARENT_GATE; in at91_clk_register_audio_pll_pad() 377 clk->flags = CLK_SET_RATE_GATE \| CLK_SET_PARENT_GATE; in at91_clk_register_audio_pll_pmc()`
A D	at91_utmi.c	`127 clk->flags = CLK_SET_RATE_GATE; in at91_clk_register_utmi()`
A D	at91_usb.c	`105 clk->flags = CLK_SET_RATE_GATE \| CLK_SET_PARENT_GATE; in _at91sam9x5_clk_register_usb()`
A D	at91_programmable.c	`154 clk->flags = CLK_SET_RATE_GATE \| CLK_SET_PARENT_GATE; in at91_clk_register_programmable()`
A D	at91_master.c	`140 clk->flags = CLK_SET_RATE_GATE; in at91_clk_register_master_internal()`
A D	at91_generated.c	`160 clk->flags = CLK_SET_RATE_GATE \| CLK_SET_PARENT_GATE; in at91_clk_register_generated()`
A D	at91_pll.c	`290 clk->flags = CLK_SET_RATE_GATE; in at91_clk_register_pll()`
/optee_os-3.20.0/core/include/drivers/
A D	clk.h	`14 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ macro`
/optee_os-3.20.0/core/drivers/clk/
A D	clk.c	`217 if (clk->flags & CLK_SET_RATE_GATE && clk_is_enabled_no_lock(clk)) in clk_set_rate()`

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