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Searched refs:DCFG_BASE (Results 1 – 2 of 2) sorted by relevance

/optee_os-3.20.0/core/arch/arm/plat-ls/
A Dmain.c72 #ifdef DCFG_BASE
73 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, DCFG_BASE, CORE_MMU_PGDIR_SIZE);
83 io_write32(DCFG_BASE + DCFG_SCRATCHRW1, in plat_primary_init_early()
87 io_write32(DCFG_BASE + DCFG_CCSR_BRR /* cpu1 */, in plat_primary_init_early()
181 addr = (vaddr_t)phys_to_virt(DCFG_BASE + DCFG_SVR_OFFSET, in get_gic_offset()
A Dplatform_config.h60 #define DCFG_BASE 0x01EE0000 macro

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