1 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 2 /* 3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved 4 * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> 5 */ 6 7 #ifndef _DT_BINDINGS_STM32MP13_RESET_H_ 8 #define _DT_BINDINGS_STM32MP13_RESET_H_ 9 10 #define MPSYST_R 2208 11 #define TIM2_R 13568 12 #define TIM3_R 13569 13 #define TIM4_R 13570 14 #define TIM5_R 13571 15 #define TIM6_R 13572 16 #define TIM7_R 13573 17 #define LPTIM1_R 13577 18 #define SPI2_R 13579 19 #define SPI3_R 13580 20 #define USART3_R 13583 21 #define UART4_R 13584 22 #define UART5_R 13585 23 #define UART7_R 13586 24 #define UART8_R 13587 25 #define I2C1_R 13589 26 #define I2C2_R 13590 27 #define SPDIF_R 13594 28 #define TIM1_R 13632 29 #define TIM8_R 13633 30 #define SPI1_R 13640 31 #define USART6_R 13645 32 #define SAI1_R 13648 33 #define SAI2_R 13649 34 #define DFSDM_R 13652 35 #define FDCAN_R 13656 36 #define LPTIM2_R 13696 37 #define LPTIM3_R 13697 38 #define LPTIM4_R 13698 39 #define LPTIM5_R 13699 40 #define SYSCFG_R 13707 41 #define VREF_R 13709 42 #define DTS_R 13712 43 #define PMBCTRL_R 13713 44 #define LTDC_R 13760 45 #define DCMIPP_R 13761 46 #define DDRPERFM_R 13768 47 #define USBPHY_R 13776 48 #define STGEN_R 13844 49 #define USART1_R 13888 50 #define USART2_R 13889 51 #define SPI4_R 13890 52 #define SPI5_R 13891 53 #define I2C3_R 13892 54 #define I2C4_R 13893 55 #define I2C5_R 13894 56 #define TIM12_R 13895 57 #define TIM13_R 13896 58 #define TIM14_R 13897 59 #define TIM15_R 13898 60 #define TIM16_R 13899 61 #define TIM17_R 13900 62 #define DMA1_R 13952 63 #define DMA2_R 13953 64 #define DMAMUX1_R 13954 65 #define DMA3_R 13955 66 #define DMAMUX2_R 13956 67 #define ADC1_R 13957 68 #define ADC2_R 13958 69 #define USBO_R 13960 70 #define GPIOA_R 14080 71 #define GPIOB_R 14081 72 #define GPIOC_R 14082 73 #define GPIOD_R 14083 74 #define GPIOE_R 14084 75 #define GPIOF_R 14085 76 #define GPIOG_R 14086 77 #define GPIOH_R 14087 78 #define GPIOI_R 14088 79 #define TSC_R 14095 80 #define PKA_R 14146 81 #define SAES_R 14147 82 #define CRYP1_R 14148 83 #define HASH1_R 14149 84 #define RNG1_R 14150 85 #define AXIMC_R 14160 86 #define MDMA_R 14208 87 #define MCE_R 14209 88 #define ETH1MAC_R 14218 89 #define FMC_R 14220 90 #define QSPI_R 14222 91 #define SDMMC1_R 14224 92 #define SDMMC2_R 14225 93 #define CRC1_R 14228 94 #define USBH_R 14232 95 #define ETH2MAC_R 14238 96 97 /* SCMI reset domain identifiers */ 98 #define RST_SCMI_LTDC 0 99 #define RST_SCMI_MDMA 1 100 101 #endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */ 102