| /optee_os-3.20.0/core/arch/arm/plat-imx/ |
| A D | main.c | 61 #ifdef GICD_BASE
62 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, 0x10000);
120 #ifdef GICD_BASE in main_init_gic()
121 gic_init(&gic_data, 0, GICD_BASE); in main_init_gic()
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| /optee_os-3.20.0/core/arch/arm/plat-rockchip/ |
| A D | platform_config.h | 22 #define GICD_BASE (GIC_BASE + 0x1000) macro
51 #define GICD_BASE GIC_BASE macro
73 #define GICD_BASE (GIC_BASE + 0x1000) macro
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| A D | main.c | 29 gic_init(&gic_data, GICC_BASE, GICD_BASE); in main_init_gic()
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| /optee_os-3.20.0/core/arch/arm/plat-marvell/ |
| A D | platform_config.h | 72 #define GICD_BASE (GIC_BASE + GICD_OFFSET) macro
103 #define GICD_BASE (GIC_BASE + GICD_OFFSET) macro
122 #define GICD_BASE (GIC_BASE + GICD_OFFSET) macro
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| A D | main.c | 71 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, CORE_MMU_PGDIR_SIZE);
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| /optee_os-3.20.0/core/arch/arm/plat-corstone1000/ |
| A D | main.c | 22 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
27 gic_init_base_addr(&gic_data, GICC_BASE, GICD_BASE); in main_init_gic()
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| A D | platform_config.h | 26 #define GICD_BASE (GIC_BASE + GICD_OFFSET) macro
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| /optee_os-3.20.0/core/arch/arm/plat-bcm/ |
| A D | platform_config.h | 18 #define GICD_BASE 0x63c00000 macro
54 #define BCM_DEVICE0_BASE GICD_BASE
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| A D | main.c | 84 gic_init_base_addr(&gic_data, 0, GICD_BASE); in main_init_gic()
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| /optee_os-3.20.0/core/arch/arm/plat-rcar/ |
| A D | platform_config.h | 43 #define GICD_BASE 0xF1010000 macro
52 #define GICD_BASE 0xF1000000 macro
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| A D | main.c | 40 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
93 gic_init(&gic_data, GICC_BASE, GICD_BASE); in main_init_gic()
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| /optee_os-3.20.0/core/arch/arm/plat-k3/ |
| A D | main.c | 28 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE);
41 gic_init_base_addr(&gic_data, GICC_BASE, GICD_BASE); in main_init_gic()
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| A D | platform_config.h | 59 #define GICD_BASE (SCU_BASE + GICD_OFFSET) macro
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| /optee_os-3.20.0/core/arch/arm/plat-imx/registers/ |
| A D | imx93.h | 8 #define GICD_BASE 0x48000000 macro
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| A D | imx8q.h | 9 #define GICD_BASE 0x51a00000 macro
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| A D | imx8ulp.h | 10 #define GICD_BASE 0x2d400000 macro
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| A D | imx8m.h | 11 #define GICD_BASE 0x38800000 macro
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| /optee_os-3.20.0/core/arch/arm/plat-ti/ |
| A D | platform_config.h | 45 #define GICD_BASE (SCU_BASE + GICD_OFFSET) macro
80 #define GICD_BASE (SCU_BASE + GICD_OFFSET) macro
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| A D | main.c | 35 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE);
41 gic_init(&gic_data, GICC_BASE, GICD_BASE); in main_init_gic()
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| /optee_os-3.20.0/core/arch/arm/plat-rzn1/ |
| A D | platform_config.h | 20 #define GICD_BASE (GIC_BASE + GICD_OFFSET) macro
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| /optee_os-3.20.0/core/arch/arm/plat-totalcompute/ |
| A D | platform_config.h | 42 #define GICD_BASE (GIC_BASE + GICD_OFFSET) macro
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| A D | main.c | 26 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
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| /optee_os-3.20.0/core/arch/arm/plat-rzg/ |
| A D | platform_config.h | 17 #define GICD_BASE 0xF1010000 macro
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| A D | main.c | 15 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
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| /optee_os-3.20.0/core/arch/arm/plat-vexpress/ |
| A D | platform_config.h | 137 #define GICD_BASE (GIC_BASE + GICD_OFFSET) macro
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