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Searched refs:GICD_OFFSET (Results 1 – 25 of 36) sorted by relevance

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/optee_os-3.20.0/core/arch/arm/plat-ls/
A Dplatform_config.h46 #define GICD_OFFSET 0x1000 macro
69 #define GICD_OFFSET 0x10000 macro
79 #define GICD_OFFSET 0x0 macro
89 #define GICD_OFFSET 0x0 macro
99 #define GICD_OFFSET 0x0 macro
109 #define GICD_OFFSET 0x0 macro
119 #define GICD_OFFSET 0x0 macro
/optee_os-3.20.0/core/arch/arm/plat-marvell/
A Dplatform_config.h70 #define GICD_OFFSET 0x0 macro
72 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
101 #define GICD_OFFSET (0x0) macro
103 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
120 #define GICD_OFFSET (0x0) macro
122 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
/optee_os-3.20.0/core/arch/arm/plat-mediatek/
A Dplatform_config.h24 #define GICD_OFFSET 0x1000 macro
42 #define GICD_OFFSET 0x0 macro
56 #define GICD_OFFSET 0x00000 macro
70 #define GICD_OFFSET 0x0 macro
84 #define GICD_OFFSET 0x0 macro
A Dmain.c25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE + GICD_OFFSET,
33 GIC_BASE + GICD_OFFSET); in main_init_gic()
/optee_os-3.20.0/core/arch/arm/plat-vexpress/
A Dplatform_config.h100 #define GICD_OFFSET 0x3000000 macro
114 #define GICD_OFFSET 0 macro
124 #define GICD_OFFSET 0 macro
129 #define GICD_OFFSET 0 macro
137 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
/optee_os-3.20.0/core/arch/arm/plat-ti/
A Dplatform_config.h42 #define GICD_OFFSET 0x1000 macro
45 #define GICD_BASE (SCU_BASE + GICD_OFFSET)
74 #define GICD_OFFSET 0x1000 macro
80 #define GICD_BASE (SCU_BASE + GICD_OFFSET)
/optee_os-3.20.0/core/arch/arm/plat-rzn1/
A Dplatform_config.h18 #define GICD_OFFSET 0x1000 macro
20 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
/optee_os-3.20.0/core/arch/arm/plat-k3/
A Dplatform_config.h28 #define GICD_OFFSET 0x0 macro
33 #define GICD_OFFSET 0x0 macro
59 #define GICD_BASE (SCU_BASE + GICD_OFFSET)
/optee_os-3.20.0/core/arch/arm/plat-corstone1000/
A Dplatform_config.h23 #define GICD_OFFSET 0x10000 macro
26 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
/optee_os-3.20.0/core/arch/arm/plat-totalcompute/
A Dplatform_config.h19 #define GICD_OFFSET 0x0 macro
42 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
/optee_os-3.20.0/core/arch/arm/plat-sprd/
A Dmain.c46 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
54 GIC_BASE + GICD_OFFSET); in main_init_gic()
A Dplatform_config.h61 #define GICD_OFFSET 0x1000 macro
/optee_os-3.20.0/core/arch/arm/plat-uniphier/
A Dmain.c26 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
43 GIC_BASE + GICD_OFFSET); in main_init_gic()
A Dplatform_config.h17 #define GICD_OFFSET 0 macro
/optee_os-3.20.0/core/arch/arm/plat-zynqmp/
A Dplatform_config.h72 #define GICD_OFFSET 0 macro
87 #define GICD_OFFSET 0 macro
A Dmain.c62 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
84 GIC_BASE + GICD_OFFSET); in main_init_gic()
/optee_os-3.20.0/core/arch/arm/plat-zynq7k/
A Dplatform_config.h40 #define GICD_OFFSET 0x1000 macro
42 #define GIC_DIST_BASE (GIC_BASE + GICD_OFFSET)
/optee_os-3.20.0/core/arch/arm/plat-amlogic/
A Dplatform_config.h16 #define GICD_OFFSET 0x1000 macro
/optee_os-3.20.0/core/arch/arm/plat-versal/
A Dmain.c40 GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE);
56 GIC_BASE + GICD_OFFSET); in main_init_gic()
A Dplatform_config.h44 #define GICD_OFFSET 0 macro
/optee_os-3.20.0/core/arch/arm/plat-imx/registers/
A Dimx6.h87 #define GICD_OFFSET 0x1000 macro
102 #define GIC_DIST_BASE (GIC_BASE + GICD_OFFSET)
/optee_os-3.20.0/core/arch/arm/plat-aspeed/
A Dplatform_config.h17 #define GICD_OFFSET 0x1000 macro
A Dplatform_ast2600.c47 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE + GICD_OFFSET, GIC_DIST_REG_SIZE);
66 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in main_init_gic()
/optee_os-3.20.0/core/arch/arm/plat-synquacer/
A Dplatform_config.h14 #define GICD_OFFSET 0x0 macro
/optee_os-3.20.0/core/arch/arm/plat-sunxi/
A Dplatform_config.h48 #define GICD_OFFSET 0x1000 macro

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