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Searched refs:GIC_BASE (Results 1 – 25 of 42) sorted by relevance

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/optee_os-3.20.0/core/arch/arm/plat-ls/
A Dplatform_config.h44 #define GIC_BASE 0x01400000 macro
53 #define GIC_BASE 0x01400000 macro
67 #define GIC_BASE 0x01400000 macro
77 #define GIC_BASE 0x06000000 macro
87 #define GIC_BASE 0x06000000 macro
97 #define GIC_BASE 0x06000000 macro
107 #define GIC_BASE 0x06000000 macro
117 #define GIC_BASE 0x06000000 macro
/optee_os-3.20.0/core/arch/arm/plat-rockchip/
A Dplatform_config.h20 #define GIC_BASE 0x32010000 macro
22 #define GICD_BASE (GIC_BASE + 0x1000)
23 #define GICC_BASE (GIC_BASE + 0x2000)
48 #define GIC_BASE (MMIO_BASE + 0x06E00000) macro
51 #define GICD_BASE GIC_BASE
52 #define GICR_BASE (GIC_BASE + SIZE_M(1))
71 #define GIC_BASE 0xff130000 macro
73 #define GICD_BASE (GIC_BASE + 0x1000)
74 #define GICC_BASE (GIC_BASE + 0x2000)
/optee_os-3.20.0/core/arch/arm/plat-marvell/
A Dplatform_config.h60 #define GIC_BASE GIC_DIST_BASE macro
72 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
73 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
98 #define GIC_BASE GIC_DIST_BASE macro
103 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
104 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
119 #define GIC_BASE 0x801000000000ll macro
122 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
A Dmain.c70 #ifdef GIC_BASE
82 gicc_base = GIC_BASE + GICC_OFFSET; in main_init_gic()
84 gicd_base = GIC_BASE + GICD_OFFSET; in main_init_gic()
/optee_os-3.20.0/core/arch/arm/plat-vexpress/
A Dplatform_config.h17 #define GIC_BASE 0x2c000000 macro
31 #define GIC_BASE 0x2c010000 macro
57 #define GIC_BASE 0x08000000 macro
70 #define GIC_BASE 0x08000000 macro
136 #ifdef GIC_BASE
137 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
138 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
A Dmain.c51 #ifdef GIC_BASE
60 gic_init_base_addr(&gic_data, GIC_BASE + GICC_OFFSET, in main_init_gic()
61 GIC_BASE + GICD_OFFSET); in main_init_gic()
63 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in main_init_gic()
/optee_os-3.20.0/core/arch/arm/plat-totalcompute/
A Dplatform_config.h18 #define GIC_BASE 0x30000000 macro
41 #ifdef GIC_BASE
42 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
43 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
A Dmain.c39 gic_init_base_addr(&gic_data, GIC_BASE + GICC_OFFSET, in main_init_gic()
40 GIC_BASE + GICC_OFFSET); in main_init_gic()
/optee_os-3.20.0/core/arch/arm/plat-sprd/
A Dmain.c42 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
46 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
53 gic_init_base_addr(&gic_data, GIC_BASE + GICC_OFFSET, in main_init_gic()
54 GIC_BASE + GICD_OFFSET); in main_init_gic()
/optee_os-3.20.0/core/arch/arm/plat-mediatek/
A Dplatform_config.h22 #define GIC_BASE 0x10220000 macro
40 #define GIC_BASE 0x0C000000 macro
54 #define GIC_BASE 0x10310000 macro
68 #define GIC_BASE 0x0C000000 macro
82 #define GIC_BASE 0x0C000000 macro
A Dmain.c25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE + GICD_OFFSET,
27 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE + GICC_OFFSET,
32 gic_init_base_addr(&gic_data, GIC_BASE + GICC_OFFSET, in main_init_gic()
33 GIC_BASE + GICD_OFFSET); in main_init_gic()
/optee_os-3.20.0/core/arch/arm/plat-uniphier/
A Dmain.c22 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
26 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
42 gic_init_base_addr(&gic_data, GIC_BASE + GICC_OFFSET, in main_init_gic()
43 GIC_BASE + GICD_OFFSET); in main_init_gic()
/optee_os-3.20.0/core/arch/arm/plat-rzn1/
A Dplatform_config.h17 #define GIC_BASE 0x44100000 macro
20 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
21 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
/optee_os-3.20.0/core/arch/arm/plat-corstone1000/
A Dplatform_config.h14 #define GIC_BASE 0x1c000000 macro
26 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
27 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
/optee_os-3.20.0/core/arch/arm/plat-zynqmp/
A Dmain.c58 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
62 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
83 gic_init_base_addr(&gic_data, GIC_BASE + GICC_OFFSET, in main_init_gic()
84 GIC_BASE + GICD_OFFSET); in main_init_gic()
A Dplatform_config.h62 #define GIC_BASE 0xF9010000 macro
77 #define GIC_BASE 0xF9010000 macro
/optee_os-3.20.0/core/arch/arm/plat-sunxi/
A Dmain.c47 #ifdef GIC_BASE
48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
85 #ifdef GIC_BASE
131 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in main_init_gic()
/optee_os-3.20.0/core/arch/arm/plat-imx/
A Dmain.c55 #ifdef GIC_BASE
56 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
123 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in main_init_gic()
/optee_os-3.20.0/core/arch/arm/plat-versal/
A Dmain.c37 GIC_BASE, CORE_MMU_PGDIR_SIZE);
40 GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE);
55 GIC_BASE + GICC_OFFSET, in main_init_gic()
56 GIC_BASE + GICD_OFFSET); in main_init_gic()
/optee_os-3.20.0/core/arch/arm/plat-aspeed/
A Dplatform_ast2600.c47 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE + GICD_OFFSET, GIC_DIST_REG_SIZE);
48 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE + GICC_OFFSET, GIC_CPU_REG_SIZE);
66 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); in main_init_gic()
A Dplatform_config.h15 #define GIC_BASE 0x40460000 macro
/optee_os-3.20.0/core/arch/arm/plat-zynq7k/
A Dplatform_config.h38 #define GIC_BASE 0xF8F00000 macro
41 #define GIC_CPU_BASE (GIC_BASE + GICC_OFFSET)
42 #define GIC_DIST_BASE (GIC_BASE + GICD_OFFSET)
/optee_os-3.20.0/core/arch/arm/plat-imx/registers/
A Dimx6.h86 #define GIC_BASE 0x00A00000 macro
101 #define GIC_CPU_BASE (GIC_BASE + GICC_OFFSET)
102 #define GIC_DIST_BASE (GIC_BASE + GICD_OFFSET)
/optee_os-3.20.0/core/arch/arm/plat-synquacer/
A Dmain.c28 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
47 gic_init_base_addr(&gic_data, 0, GIC_BASE + GICD_OFFSET); in main_init_gic()
/optee_os-3.20.0/core/arch/arm/plat-amlogic/
A Dplatform_config.h14 #define GIC_BASE 0xFFC01000 macro

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