1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 */ 5 6 #ifndef PLATFORM_CONFIG_H 7 #define PLATFORM_CONFIG_H 8 9 #include <mm/generic_ram_layout.h> 10 11 /* Make stacks aligned to data cache line length */ 12 #define STACK_ALIGNMENT 32 13 14 /* SoC interface registers base address ranges */ 15 #define APB1_BASE 0x40000000 16 #define APB1_SIZE 0x0001d000 17 #define APB2_BASE 0x44000000 18 #define APB2_SIZE 0x00014000 19 #define APB3_BASE 0x50020000 20 #define APB3_SIZE 0x0000b000 21 #define APB4_BASE 0x5a000000 22 #define APB4_SIZE 0x00008000 23 #define APB5_BASE 0x5c000000 24 #define APB5_SIZE 0x0000b000 25 #ifdef CFG_STM32MP13 26 #define APB6_BASE 0x4c000000 27 #define APB6_SIZE 0x0000d000 28 #endif 29 30 #define AHB4_BASE 0x50000000 31 #define AHB4_SIZE 0x00020000 32 #ifdef CFG_STM32MP13 33 #define AHB5_BASE 0x54000000 34 #define AHB5_SIZE 0x00008000 35 #endif 36 #ifdef CFG_STM32MP15 37 #define AHB5_BASE 0x54000000 38 #define AHB5_SIZE 0x00005000 39 #endif 40 41 /* SoC interface registers base address */ 42 #define BSEC_BASE 0x5c005000 43 #define ETZPC_BASE 0x5c007000 44 #define CRYP1_BASE 0x54001000 45 #define DDR_BASE 0xc0000000ul 46 #define GIC_BASE 0xa0021000ul 47 #define GPIOA_BASE 0x50002000 48 #define GPIOB_BASE 0x50003000 49 #define GPIOC_BASE 0x50004000 50 #define GPIOD_BASE 0x50005000 51 #define GPIOE_BASE 0x50006000 52 #define GPIOF_BASE 0x50007000 53 #define GPIOG_BASE 0x50008000 54 #define GPIOH_BASE 0x50009000 55 #define GPIOI_BASE 0x5000a000 56 #define GPIOJ_BASE 0x5000b000 57 #define GPIOK_BASE 0x5000c000 58 #define GPIOZ_BASE 0x54004000 59 #define HASH1_BASE 0x54002000 60 #define I2C4_BASE 0x5c002000 61 #define I2C5_BASE 0x40015000 62 #define I2C6_BASE 0x5c009000 63 #define IWDG1_BASE 0x5c003000 64 #define IWDG2_BASE 0x5a002000 65 #define PWR_BASE 0x50001000 66 #define RCC_BASE 0x50000000 67 #ifdef CFG_STM32MP13 68 #define RNG1_BASE 0x54004000 69 #endif 70 #ifdef CFG_STM32MP15 71 #define RNG1_BASE 0x54003000 72 #endif 73 #define RTC_BASE 0x5c004000 74 #define SPI6_BASE 0x5c001000 75 #define SYSCFG_BASE 0x50020000 76 #ifdef CFG_STM32MP13 77 #define SYSRAM_BASE 0x2ffe0000 78 #endif 79 #ifdef CFG_STM32MP15 80 #define SYSRAM_BASE 0x2ffc0000 81 #endif 82 #define TAMP_BASE 0x5c00a000 83 #define TZC_BASE 0x5c006000 84 #ifdef CFG_STM32MP13 85 #define UART1_BASE 0x4c000000 86 #define UART2_BASE 0x4c001000 87 #endif 88 #ifdef CFG_STM32MP15 89 #define UART1_BASE 0x5c000000 90 #define UART2_BASE 0x4000e000 91 #endif 92 #define UART3_BASE 0x4000f000 93 #define UART4_BASE 0x40010000 94 #define UART5_BASE 0x40011000 95 #define UART6_BASE 0x44003000 96 #define UART7_BASE 0x40018000 97 #define UART8_BASE 0x40019000 98 99 /* Console configuration */ 100 #define STM32MP1_DEBUG_USART_BASE UART4_BASE 101 #define GIC_SPI_UART4 84 102 103 #define CONSOLE_UART_BASE STM32MP1_DEBUG_USART_BASE 104 #define CONSOLE_UART_SIZE 1024 105 106 /* BSEC OTP resources */ 107 #define STM32MP1_OTP_MAX_ID 0x5FU 108 #define STM32MP1_UPPER_OTP_START 0x20U 109 110 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 111 112 /* Bit map for BSEC word CFG0_OTP */ 113 #ifdef CFG_STM32MP13 114 #define CFG0_OTP_CLOSED_DEVICE U(0x3F) 115 #endif 116 #ifdef CFG_STM32MP15 117 #define CFG0_OTP_CLOSED_DEVICE BIT(6) 118 #endif 119 120 /* Bit map for BSEC word HW2_OTP */ 121 #define HW2_OTP_IWDG_HW_ENABLE_SHIFT U(3) 122 #define HW2_OTP_IWDG_FZ_STOP_SHIFT U(5) 123 #define HW2_OTP_IWDG_FZ_STANDBY_SHIFT U(7) 124 125 /* GIC resources */ 126 #define GIC_SIZE 0x2000 127 #define GICC_OFFSET 0x1000 128 #define GICD_OFFSET 0x0000 129 130 #define GIC_NON_SEC_SGI_0 0 131 #define GIC_SEC_SGI_0 8 132 #define GIC_SEC_SGI_1 9 133 134 #define TARGET_CPU0_GIC_MASK BIT(0) 135 #define TARGET_CPU1_GIC_MASK BIT(1) 136 #define TARGET_CPUS_GIC_MASK GENMASK_32(CFG_TEE_CORE_NB_CORE - 1, 0) 137 138 /* 139 * GPIO banks: 11 non secure banks (A to K) and 1 secure bank (Z) 140 * Bank register's base address is computed from the bank ID listed here. 141 */ 142 #define GPIOS_NSEC_COUNT 11 143 #define GPIOS_NSEC_BASE GPIOA_BASE 144 #define GPIOS_NSEC_SIZE (GPIOS_NSEC_COUNT * SMALL_PAGE_SIZE) 145 146 #define STM32MP1_GPIOZ_MAX_COUNT 1 147 #define STM32MP1_GPIOZ_PIN_MAX_COUNT 8 148 149 #define GPIO_BANK_OFFSET 0x1000U 150 151 /* Bank IDs used in GPIO driver API */ 152 #define GPIO_BANK_A 0U 153 #define GPIO_BANK_B 1U 154 #define GPIO_BANK_C 2U 155 #define GPIO_BANK_D 3U 156 #define GPIO_BANK_E 4U 157 #define GPIO_BANK_F 5U 158 #define GPIO_BANK_G 6U 159 #define GPIO_BANK_H 7U 160 #define GPIO_BANK_I 8U 161 #define GPIO_BANK_J 9U 162 #define GPIO_BANK_K 10U 163 #define GPIO_BANK_Z 25U 164 165 /* TAMP resources */ 166 #define TAMP_BKP_REGISTER_OFF 0x100 167 #define TAMP_BKP_REGISTER_COUNT U(32) 168 169 #define TAMP_BKP_REGISTER_ZONE1_COUNT U(10) 170 #define TAMP_BKP_REGISTER_ZONE2_COUNT U(5) 171 #define TAMP_BKP_REGISTER_ZONE3_COUNT U(17) 172 173 #if (TAMP_BKP_REGISTER_ZONE1_COUNT + TAMP_BKP_REGISTER_ZONE2_COUNT + \ 174 TAMP_BKP_REGISTER_ZONE3_COUNT != TAMP_BKP_REGISTER_COUNT) 175 #error Inconsistent TAMP backup register zone definition 176 #endif 177 178 /* TZC resources */ 179 #define STM32MP1_IRQ_TZC 36 180 181 #define STM32MP1_TZC_A7_ID 0 182 #define STM32MP1_TZC_M4_ID 1 183 #define STM32MP1_TZC_LCD_ID 3 184 #define STM32MP1_TZC_GPU_ID 4 185 #define STM32MP1_TZC_MDMA_ID 5 186 #define STM32MP1_TZC_DMA_ID 6 187 #define STM32MP1_TZC_USB_HOST_ID 7 188 #define STM32MP1_TZC_USB_OTG_ID 8 189 #define STM32MP1_TZC_SDMMC_ID 9 190 #define STM32MP1_TZC_ETH_ID 10 191 #define STM32MP1_TZC_DAP_ID 15 192 193 /* USART/UART resources */ 194 #define USART1_BASE UART1_BASE 195 #define USART2_BASE UART2_BASE 196 #define USART3_BASE UART3_BASE 197 #define USART6_BASE UART6_BASE 198 199 /* SYSRAM layout */ 200 #ifdef CFG_STM32MP13 201 #define SYSRAM_SIZE 0x20000 202 #else /* Assume CFG_STM32MP15 */ 203 #define SYSRAM_SIZE 0x40000 204 #endif 205 #define SYSRAM_NS_SIZE (SYSRAM_SIZE - SYSRAM_SEC_SIZE) 206 207 /* Non-secure SYSRAM must be above (higher addresses) secure SYSRAM */ 208 #if (CFG_STM32MP1_SCMI_SHM_BASE >= SYSRAM_BASE) && \ 209 ((CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) <= \ 210 (SYSRAM_BASE + SYSRAM_SIZE)) 211 #define SYSRAM_SEC_SIZE (CFG_STM32MP1_SCMI_SHM_BASE - SYSRAM_BASE) 212 #else 213 #define SYSRAM_SEC_SIZE SYSRAM_SIZE 214 #endif 215 216 #endif /*PLATFORM_CONFIG_H*/ 217