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Searched refs:MEM_AREA_IO_NSEC (Results 1 – 25 of 32) sorted by relevance

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/optee_os-3.20.0/core/arch/arm/plat-hikey/
A Dmain.c25 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
27 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMUSSI_BASE, PMUSSI_REG_SIZE);
30 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PERI_BASE, PERI_BASE_REG_SIZE);
31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMX0_BASE, PMX0_REG_SIZE);
32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMX1_BASE, PMX1_REG_SIZE);
33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIO6_BASE, PL061_REG_SIZE);
34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, SPI_BASE, PL022_REG_SIZE);
56 vaddr_t peri_base = core_mmu_get_va(PERI_BASE, MEM_AREA_IO_NSEC, in spi_init()
58 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC, in spi_init()
60 vaddr_t pmx1_base = core_mmu_get_va(PMX1_BASE, MEM_AREA_IO_NSEC, in spi_init()
[all …]
A Dspi_test.c23 vaddr_t gpio6_base = core_mmu_get_va(GPIO6_BASE, MEM_AREA_IO_NSEC, in spi_cs_callback()
25 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC, in spi_cs_callback()
50 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC, in spi_set_cs_mux()
71 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC, in spi_test_with_manual_cs_control()
160 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC, in spi_test_with_registered_cs_cb()
207 vaddr_t gpio6_base = core_mmu_get_va(GPIO6_BASE, MEM_AREA_IO_NSEC, in spi_test_with_builtin_cs_control()
209 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC, in spi_test_with_builtin_cs_control()
/optee_os-3.20.0/core/arch/arm/plat-stm32mp1/
A Dmain.c31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB1_BASE, APB1_SIZE);
32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB2_BASE, APB2_SIZE);
33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB3_BASE, APB3_SIZE);
34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB4_BASE, APB4_SIZE);
35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB5_BASE, APB5_SIZE);
36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB4_BASE, AHB4_SIZE);
37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB5_BASE, AHB5_SIZE);
51 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE,
321 uint8_t *va = phys_to_virt(nsec_start, MEM_AREA_IO_NSEC, in init_stm32mp1_drivers()
/optee_os-3.20.0/core/arch/arm/plat-bcm/
A Dmain.c37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, BCM_DEVICE5_BASE, BCM_DEVICE5_SIZE);
52 register_phys_mem(MEM_AREA_IO_NSEC, CFG_BCM_ELOG_AP_UART_LOG_BASE,
/optee_os-3.20.0/core/arch/arm/plat-ls/
A Dmain.c60 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
73 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, DCFG_BASE, CORE_MMU_PGDIR_SIZE);
182 MEM_AREA_IO_NSEC, 1); in get_gic_offset()
/optee_os-3.20.0/core/arch/arm/plat-d02/
A Dmain.c16 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
/optee_os-3.20.0/core/arch/arm/plat-rpi3/
A Dmain.c37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC,
/optee_os-3.20.0/core/arch/arm/plat-d06/
A Dmain.c12 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, LPC_BASE, LPC_SIZE);
/optee_os-3.20.0/core/arch/arm/plat-poplar/
A Dmain.c19 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
/optee_os-3.20.0/core/arch/arm/plat-aspeed/
A Dplatform_ast2600.c46 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, SMALL_PAGE_SIZE);
50 register_phys_mem(MEM_AREA_IO_NSEC, SCU_BASE, SMALL_PAGE_SIZE);
/optee_os-3.20.0/core/arch/arm/plat-hisilicon/
A Dmain.c16 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
/optee_os-3.20.0/core/arch/arm/plat-sprd/
A Dmain.c37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC,
/optee_os-3.20.0/core/arch/arm/plat-rockchip/
A Dmain.c21 register_phys_mem_pgdir(MEM_AREA_IO_NSEC,
/optee_os-3.20.0/core/arch/riscv/plat-virt/
A Dmain.c18 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART0_BASE,
/optee_os-3.20.0/core/drivers/bnxt/
A Dbnxt_images.c101 phys_to_virt(QSPI_BNXT_IMG, MEM_AREA_IO_NSEC, in get_bnxt_images_info()
112 MEM_AREA_IO_NSEC, in get_bnxt_images_info()
/optee_os-3.20.0/core/arch/arm/plat-mediatek/
A Dmain.c15 register_phys_mem_pgdir(MEM_AREA_IO_NSEC,
/optee_os-3.20.0/core/drivers/crypto/aspeed/
A Dcrypto_ast2600.c28 scu_virt = core_mmu_get_va(SCU_BASE, MEM_AREA_IO_NSEC, SMALL_PAGE_SIZE); in crypto_ast2600_init()
/optee_os-3.20.0/core/arch/arm/plat-synquacer/
A Dmain.c26 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
/optee_os-3.20.0/core/lib/scmi-server/
A Dscmi_server.c22 return (uintptr_t)phys_to_virt(pa, MEM_AREA_IO_NSEC, sz); in smt_phys_to_virt()
/optee_os-3.20.0/core/arch/riscv/plat-spike/drivers/
A Dhtif.c17 register_phys_mem(MEM_AREA_IO_NSEC, HTIF_BASE,
/optee_os-3.20.0/core/arch/arm/plat-k3/
A Dmain.c29 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
/optee_os-3.20.0/core/arch/arm/plat-imx/
A Dmain.c52 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
/optee_os-3.20.0/core/arch/arm/plat-stm/
A Dmain.c27 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART_CONSOLE_BASE, STIH_ASC_REG_SIZE);
/optee_os-3.20.0/core/arch/arm/plat-sunxi/
A Dmain.c52 register_phys_mem_pgdir(MEM_AREA_IO_NSEC,
/optee_os-3.20.0/core/kernel/
A Ddt.c116 mtype = MEM_AREA_IO_NSEC; in dt_map_dev()
122 mtype = MEM_AREA_IO_NSEC; in dt_map_dev()

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