Home
last modified time | relevance | path

Searched refs:MEM_AREA_IO_SEC (Results 1 – 25 of 94) sorted by relevance

1234

/optee_os-3.20.0/core/arch/arm/plat-imx/
A Dmain.c56 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
59 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ANATOP_BASE, CORE_MMU_PGDIR_SIZE);
62 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, 0x10000);
65 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS0_BASE,
69 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS1_BASE,
73 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS2_BASE,
77 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS3_BASE,
86 register_phys_mem(MEM_AREA_IO_SEC, M4_AIPS_BASE, M4_AIPS_SIZE);
95 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
/optee_os-3.20.0/core/arch/arm/plat-sunxi/
A Dmain.c48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
57 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_TZPC_BASE, SUNXI_TZPC_REG_SIZE);
70 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_CPUCFG_BASE,
75 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_PRCM_BASE, SUNXI_PRCM_REG_SIZE);
80 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_SMC_BASE, TZC400_REG_SIZE);
106 vaddr_t v = (vaddr_t)phys_to_virt(SUNXI_TZPC_BASE, MEM_AREA_IO_SEC, in tzpc_init()
157 return (vaddr_t)phys_to_virt(SUNXI_SMC_BASE, MEM_AREA_IO_SEC, in smc_base()
/optee_os-3.20.0/core/arch/arm/plat-versal/
A Dmain.c32 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
36 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
39 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
42 register_phys_mem(MEM_AREA_IO_SEC, PLM_RTCA, PLM_RTCA_LEN);
73 vaddr_t plm_rtca = (vaddr_t)phys_to_virt(PLM_RTCA, MEM_AREA_IO_SEC, in platform_banner()
103 vaddr_t plm_rtca = (vaddr_t)phys_to_virt(PLM_RTCA, MEM_AREA_IO_SEC, in plat_rpmb_key_is_ready()
/optee_os-3.20.0/core/arch/arm/plat-rzn1/
A Dmain.c35 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
36 register_phys_mem(MEM_AREA_IO_SEC, PERIPH_REG_BASE, CORE_MMU_PGDIR_SIZE);
61 tza_init_reg = core_mmu_get_va(FW_STATIC_TZA_INIT, MEM_AREA_IO_SEC, in rzn1_tz_init()
63 tza_targ_reg = core_mmu_get_va(FW_STATIC_TZA_TARG, MEM_AREA_IO_SEC, in rzn1_tz_init()
87 cm3_pwrctrl_reg = core_mmu_get_va(SYSCTRL_PWRCTRL_CM3, MEM_AREA_IO_SEC, in rzn1_cm3_start()
89 cm3_pwrstat_reg = core_mmu_get_va(SYSCTRL_PWRSTAT_CM3, MEM_AREA_IO_SEC, in rzn1_cm3_start()
A Dpsci.c46 MEM_AREA_IO_SEC, in psci_cpu_on()
78 io_setbits32(core_mmu_get_va(SYSCTRL_REG_RSTEN, MEM_AREA_IO_SEC, in psci_system_reset()
83 io_setbits32(core_mmu_get_va(SYSCTRL_REG_RSTCTRL, MEM_AREA_IO_SEC, in psci_system_reset()
/optee_os-3.20.0/core/arch/arm/plat-imx/pm/
A Dpm-imx7.c111 map.va = (vaddr_t)phys_to_virt(phys_addr[i], MEM_AREA_IO_SEC, in pm_imx7_iram_tbl_init()
115 map.type = MEM_AREA_IO_SEC; in pm_imx7_iram_tbl_init()
163 p->ccm_va_base = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, 1); in imx7_suspend_init()
165 p->ddrc_va_base = core_mmu_get_va(DDRC_BASE, MEM_AREA_IO_SEC, 1); in imx7_suspend_init()
167 p->ddrc_phy_va_base = core_mmu_get_va(DDRC_PHY_BASE, MEM_AREA_IO_SEC, in imx7_suspend_init()
170 p->src_va_base = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, 1); in imx7_suspend_init()
173 MEM_AREA_IO_SEC, 1); in imx7_suspend_init()
175 p->gpc_va_base = core_mmu_get_va(GPC_BASE, MEM_AREA_IO_SEC, 1); in imx7_suspend_init()
179 p->snvs_va_base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, 1); in imx7_suspend_init()
181 p->lpsr_va_base = core_mmu_get_va(LPSR_BASE, MEM_AREA_IO_SEC, 1); in imx7_suspend_init()
[all …]
A Dcpuidle-imx7d.c53 p->ddrc_va_base = core_mmu_get_va(DDRC_BASE, MEM_AREA_IO_SEC, 1); in imx7d_cpuidle_init()
55 p->ccm_va_base = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, 1); in imx7d_cpuidle_init()
57 p->anatop_va_base = core_mmu_get_va(ANATOP_BASE, MEM_AREA_IO_SEC, 1); in imx7d_cpuidle_init()
59 p->src_va_base = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, 1); in imx7d_cpuidle_init()
62 MEM_AREA_IO_SEC, 1); in imx7d_cpuidle_init()
64 p->gpc_va_base = core_mmu_get_va(GPC_BASE, MEM_AREA_IO_SEC, 1); in imx7d_cpuidle_init()
66 p->gic_va_base = core_mmu_get_va(GIC_BASE, MEM_AREA_IO_SEC, 1); in imx7d_cpuidle_init()
142 MEM_AREA_IO_SEC, sizeof(uint32_t)); in get_online_cpus()
/optee_os-3.20.0/core/arch/arm/plat-zynqmp/
A Dmain.c53 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
57 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
61 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
65 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CSU_BASE, CSU_SIZE);
102 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in plat_rpmb_key_is_ready()
/optee_os-3.20.0/core/arch/arm/plat-bcm/
A Dmain.c22 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE0_BASE, BCM_DEVICE0_SIZE);
25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE1_BASE, BCM_DEVICE1_SIZE);
28 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE2_BASE, BCM_DEVICE2_SIZE);
31 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE3_BASE, BCM_DEVICE3_SIZE);
34 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE4_BASE, BCM_DEVICE4_SIZE);
/optee_os-3.20.0/core/arch/arm/plat-k3/
A Dmain.c27 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE);
28 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE);
31 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SEC_PROXY_DATA_BASE,
33 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SEC_PROXY_SCFG_BASE,
35 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE);
/optee_os-3.20.0/core/arch/arm/plat-marvell/
A Dmain.c63 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE,
66 register_phys_mem(MEM_AREA_IO_SEC, PLAT_MARVELL_FUSF_FUSE_BASE,
71 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, CORE_MMU_PGDIR_SIZE);
73 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, CORE_MMU_PGDIR_SIZE);
117 MEM_AREA_IO_SEC, sizeof(hwkey->data)); in tee_otp_get_hw_unique_key()
/optee_os-3.20.0/core/arch/arm/plat-imx/drivers/
A Dtzc380.c25 register_phys_mem(MEM_AREA_IO_SEC, TZASC2_BASE, TZASC_SIZE);
28 register_phys_mem(MEM_AREA_IO_SEC, TZASC_BASE, TZASC_SIZE);
36 addr[0] = core_mmu_get_va(TZASC_BASE, MEM_AREA_IO_SEC, 1); in imx_configure_tzasc()
41 addr[1] = core_mmu_get_va(TZASC2_BASE, MEM_AREA_IO_SEC, 1); in imx_configure_tzasc()
/optee_os-3.20.0/core/arch/arm/plat-hisilicon/
A Dmain.c18 register_phys_mem(MEM_AREA_IO_SEC, BOOTSRAM_BASE, BOOTSRAM_SIZE);
21 register_phys_mem(MEM_AREA_IO_SEC, CPU_CRG_BASE, CPU_CRG_SIZE);
24 register_phys_mem(MEM_AREA_IO_SEC, SYS_CTRL_BASE, SYS_CTRL_SIZE);
/optee_os-3.20.0/core/drivers/
A Dhi16xx_rng.c35 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ALG_SC_BASE, ALG_SC_REG_SIZE);
36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG_BASE, RNG_REG_SIZE);
42 vaddr_t alg = (vaddr_t)phys_to_virt(ALG_SC_BASE, MEM_AREA_IO_SEC, in hi16xx_rng_init()
44 vaddr_t rng = (vaddr_t)phys_to_virt(RNG_BASE, MEM_AREA_IO_SEC, in hi16xx_rng_init()
79 r = (vaddr_t)phys_to_virt(RNG_BASE, MEM_AREA_IO_SEC, 1) + in hw_get_random_bytes()
A Dzynqmp_csu_puf.c31 vaddr_t puf = core_mmu_get_va(ZYNQMP_CSU_PUF_BASE, MEM_AREA_IO_SEC, in zynqmp_csu_puf_regenerate()
33 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in zynqmp_csu_puf_regenerate()
55 vaddr_t puf = core_mmu_get_va(ZYNQMP_CSU_PUF_BASE, MEM_AREA_IO_SEC, in zynqmp_csu_puf_reset()
63 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in zynqmp_csu_puf_init()
A Dimx_snvs.c65 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in is_otpmk_selected()
88 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in is_mks_locked()
97 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in set_mks_otpmk()
110 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in is_otpmk_valid()
119 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, in snvs_get_security_cfg()
145 vaddr_t snvs = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, in snvs_get_ssm_mode()
A Dzynqmp_csudma.c43 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CSUDMA_BASE, CSUDMA_SIZE);
47 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in csudma_clear_intr()
61 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in zynqmp_csudma_sync()
85 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in zynqmp_csudma_prepare()
100 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in zynqmp_csudma_unprepare()
111 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in zynqmp_csudma_transfer()
/optee_os-3.20.0/core/arch/arm/plat-rcar/
A Dmain.c39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, SCIF_REG_SIZE);
40 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
41 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE);
43 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PRR_BASE, SMALL_PAGE_SIZE);
/optee_os-3.20.0/core/arch/arm/plat-rzg/
A Dmain.c14 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, SCIF_REG_SIZE);
15 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
16 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
/optee_os-3.20.0/core/arch/arm/plat-vexpress/
A Dmain.c34 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TPM2_BASE, TPM2_REG_SIZE);
42 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE);
53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
195 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE);
203 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); in init_tzc400()
227 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, in release_secondary_early_hpen()
/optee_os-3.20.0/core/arch/arm/plat-corstone1000/
A Dmain.c21 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
22 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
23 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE);
/optee_os-3.20.0/core/arch/arm/plat-uniphier/
A Dmain.c17 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
21 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
25 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
/optee_os-3.20.0/core/arch/arm/plat-zynq7k/
A Dmain.c52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE);
54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_PGDIR_SIZE);
105 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC, 1); in pl310_base()
174 MEM_AREA_IO_SEC, in write_slcr()
195 MEM_AREA_IO_SEC, in read_slcr()
/optee_os-3.20.0/core/arch/arm/plat-aspeed/
A Dplatform_ast2600.c47 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE + GICD_OFFSET, GIC_DIST_REG_SIZE);
48 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE + GICC_OFFSET, GIC_CPU_REG_SIZE);
49 register_phys_mem(MEM_AREA_IO_SEC, AHBC_BASE, SMALL_PAGE_SIZE);
93 MEM_AREA_IO_SEC, SMALL_PAGE_SIZE); in plat_primary_init_early()
/optee_os-3.20.0/core/arch/arm/plat-ti/
A Dti_pl310.c15 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, PL310_SIZE);
23 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC, in pl310_base()

Completed in 28 milliseconds

1234