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Searched refs:NSEC_DDR_0_BASE (Results 1 – 4 of 4) sorted by relevance

/optee_os-3.20.0/core/arch/arm/plat-rcar/
A Dplatform_config.h63 #define NSEC_DDR_0_BASE 0x47E00000 macro
73 #define NSEC_DDR_0_BASE 0x47E00000 macro
83 #define NSEC_DDR_0_BASE 0x47E00000 macro
89 #define NSEC_DDR_0_BASE 0x47E00000 macro
97 #define NSEC_DDR_0_BASE 0x48000000 macro
A Dmain.c52 register_ddr(NSEC_DDR_0_BASE, NSEC_DDR_0_SIZE);
/optee_os-3.20.0/core/arch/arm/plat-rzg/
A Dplatform_config.h22 #define NSEC_DDR_0_BASE 0x47E00000U macro
27 #define NSEC_DDR_0_BASE 0x47E00000U macro
34 #define NSEC_DDR_0_BASE 0x47E00000U macro
41 #define NSEC_DDR_0_BASE 0x47E00000U macro
A Dmain.c18 register_dynamic_shm(NSEC_DDR_0_BASE, NSEC_DDR_0_SIZE);

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