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Searched refs:NSEC_DDR_1_BASE (Results 1 – 4 of 4) sorted by relevance

/optee_os-3.20.0/core/arch/arm/plat-rcar/
A Dplatform_config.h65 #define NSEC_DDR_1_BASE 0x500000000U macro
75 #define NSEC_DDR_1_BASE 0x500000000U macro
85 #define NSEC_DDR_1_BASE 0x600000000U macro
91 #define NSEC_DDR_1_BASE 0x480000000U macro
99 #define NSEC_DDR_1_BASE 0x480000000U macro
A Dmain.c53 register_ddr(NSEC_DDR_1_BASE, NSEC_DDR_1_SIZE);
/optee_os-3.20.0/core/arch/arm/plat-rzg/
A Dplatform_config.h29 #define NSEC_DDR_1_BASE 0x500000000U macro
36 #define NSEC_DDR_1_BASE 0x600000000U macro
43 #define NSEC_DDR_1_BASE 0x480000000U macro
A Dmain.c19 #ifdef NSEC_DDR_1_BASE
20 register_dynamic_shm(NSEC_DDR_1_BASE, NSEC_DDR_1_SIZE);

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