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Searched refs:U (Results 1 – 25 of 69) sorted by relevance

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/optee_os-3.20.0/core/include/drivers/
A Dtzc380.h52 #define FAIL_ID U(0x02c)
57 #define REGION_SETUP_LOW_OFF(n) (U(0x100) + (n) * U(0x10))
58 #define REGION_SETUP_HIGH_OFF(n) (U(0x104) + (n) * U(0x10))
59 #define REGION_ATTRIBUTES_OFF(n) (U(0x108) + (n) * U(0x10))
62 #define PID0_OFF U(0xfe0)
63 #define PID1_OFF U(0xfe4)
64 #define PID2_OFF U(0xfe8)
65 #define PID3_OFF U(0xfec)
66 #define PID4_OFF U(0xfd0)
67 #define CID0_OFF U(0xff0)
[all …]
A Dtzc400.h96 #define PID0_OFF U(0xfe0)
97 #define PID1_OFF U(0xfe4)
98 #define PID2_OFF U(0xfe8)
99 #define PID3_OFF U(0xfec)
100 #define PID4_OFF U(0xfd0)
101 #define PID5_OFF U(0xfd4)
102 #define PID6_OFF U(0xfd8)
103 #define PID7_OFF U(0xfdc)
104 #define CID0_OFF U(0xff0)
105 #define CID1_OFF U(0xff4)
[all …]
A Dls_i2c.h23 #define I2C_IBCR_MDIS U(0x80)
26 #define I2C_IBCR_IBIE U(0x40)
37 #define I2C_IBCR_MSSL U(0x20)
40 #define I2C_IBCR_TXRX U(0x10)
60 #define I2C_IBCR_RSTA U(0x04)
66 #define I2C_IBSR_TCF U(0x80)
69 #define I2C_IBSR_IBB U(0x20)
72 #define I2C_IBSR_IBAL U(0x10)
75 #define I2C_IBSR_IBIF U(0x02)
82 #define I2C_IBSR_RXAK U(0x01)
[all …]
A Dstm32mp13_rcc.h11 #define RCC_SECCFGR U(0x0)
14 #define RCC_MP_APRSTCR U(0x108)
23 #define RCC_MP_CIER U(0x200)
24 #define RCC_MP_CIFR U(0x204)
25 #define RCC_BDCR U(0x400)
26 #define RCC_RDLSICR U(0x404)
29 #define RCC_OCRDYR U(0x428)
30 #define RCC_HSICFGR U(0x440)
31 #define RCC_CSICFGR U(0x444)
38 #define RCC_PLL1CR U(0x4A0)
[all …]
A Dls_gpio.h18 #define MAX_GPIO_PINS U(31)
24 #define GPIODIR U(0x0) /* direction register */
25 #define GPIOODR U(0x4) /* open drain register */
26 #define GPIODAT U(0x8) /* data register */
27 #define GPIOIER U(0xc) /* interrupt event register */
28 #define GPIOIMR U(0x10) /* interrupt mask register */
29 #define GPIOICR U(0x14) /* interrupt control register */
30 #define GPIOIBE U(0x18) /* input buffer enable register */
A Dstm32_i2c.h25 #define I2C_STANDARD_RATE U(100000)
26 #define I2C_FAST_RATE U(400000)
27 #define I2C_FAST_PLUS_RATE U(1000000)
85 #define I2C_ERROR_NONE U(0x0)
132 #define STM32_I2C_RISE_TIME_DEFAULT U(25) /* ns */
133 #define STM32_I2C_FALL_TIME_DEFAULT U(10) /* ns */
134 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN U(50) /* ns */
135 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX U(260) /* ns */
136 #define STM32_I2C_DIGITAL_FILTER_MAX U(16)
/optee_os-3.20.0/core/arch/arm/include/kernel/
A Dtz_ssvce_def.h58 #define PL310_8_WAYS U(8)
62 #define PL310_CTRL U(0x100)
97 #define SCU_CTRL U(0x00)
98 #define SCU_CONFIG U(0x04)
99 #define SCU_POWER U(0x08)
100 #define SCU_INV_SEC U(0x0C)
101 #define SCU_FILT_SA U(0x40)
102 #define SCU_FILT_EA U(0x44)
103 #define SCU_SAC U(0x50)
104 #define SCU_NSAC U(0x54)
[all …]
A Dtz_proc_def.h16 #define CPU_ID0 U(0x00000000)
17 #define CPU_ID1 U(0x00000001)
22 #define CP15_CONFIG_NS_MASK U(0x00000001)
23 #define CP15_CONFIG_IRQ_MASK U(0x00000002)
24 #define CP15_CONFIG_FIQ_MASK U(0x00000004)
25 #define CP15_CONFIG_EA_MASK U(0x00000008)
26 #define CP15_CONFIG_FW_MASK U(0x00000010)
61 #define CP15_CACHE_ADDR_R_BIT U(12)
87 #define LINE_FIELD_OFFSET U(5)
89 #define LINE_FIELD_OVERFLOW U(13)
[all …]
/optee_os-3.20.0/core/include/
A Doptee_rpc_cmd.h28 #define OPTEE_RPC_CMD_LOAD_TA U(0)
36 #define OPTEE_RPC_CMD_RPMB U(1)
41 #define OPTEE_RPC_CMD_FS U(2)
52 #define OPTEE_RPC_CMD_GET_TIME U(3)
82 #define OPTEE_RPC_CMD_SUSPEND U(5)
126 #define OPTEE_RPC_CMD_GPROF U(9)
192 #define OPTEE_RPC_FS_OPEN U(0)
201 #define OPTEE_RPC_FS_CREATE U(1)
209 #define OPTEE_RPC_FS_CLOSE U(2)
219 #define OPTEE_RPC_FS_READ U(3)
[all …]
A Doptee_msg.h21 #define OPTEE_MSG_ATTR_TYPE_NONE U(0x0)
80 #define OPTEE_MSG_ATTR_CACHE_SHIFT U(16)
251 #define OPTEE_MSG_UID_0 U(0x384fb3e0)
252 #define OPTEE_MSG_UID_1 U(0xe7f811e3)
253 #define OPTEE_MSG_UID_2 U(0xaf630002)
254 #define OPTEE_MSG_UID_3 U(0xa5d5c51b)
262 #define OPTEE_MSG_REVISION_MAJOR U(2)
263 #define OPTEE_MSG_REVISION_MINOR U(0)
335 #define OPTEE_MSG_CMD_OPEN_SESSION U(0)
338 #define OPTEE_MSG_CMD_CANCEL U(3)
[all …]
A Dtpm2.h21 #define TPM2_ST_RSP_COMMAND U(0x00C4)
22 #define TPM2_ST_NULL U(0X8000)
23 #define TPM2_ST_NO_SESSIONS U(0x8001)
24 #define TPM2_ST_SESSIONS U(0x8002)
27 #define TPM2_SU_CLEAR U(0x0000)
28 #define TPM2_SU_STATE U(0x0001)
51 #define TPM_RS_PW U(0x40000009)
54 #define TPM2_ALG_SHA1 U(0x0004)
55 #define TPM2_ALG_SHA256 U(0x000B)
56 #define TPM2_ALG_SHA384 U(0x000C)
[all …]
A Dbench.h18 #define TEE_BENCH_DIVIDER U(64)
21 #define TEE_BENCH_MAX_STAMPS U(32)
24 #define OPTEE_MSG_RPC_CMD_BENCH_REG_NEW U(0)
25 #define OPTEE_MSG_RPC_CMD_BENCH_REG_DEL U(1)
28 #define TEE_BENCH_CLIENT U(0x10000000)
29 #define TEE_BENCH_KMOD U(0x20000000)
30 #define TEE_BENCH_CORE U(0x30000000)
31 #define TEE_BENCH_UTEE U(0x40000000)
32 #define TEE_BENCH_DUMB_TA U(0xF0000001)
/optee_os-3.20.0/core/arch/arm/include/
A Darm.h24 #define MIDR_VARIANT_WIDTH U(4)
60 #define MPIDR_AFF0_SHIFT U(0)
62 #define MPIDR_AFF1_SHIFT U(8)
67 #define MPIDR_MT_SHIFT U(24)
86 #define CTR_CWG_SHIFT U(24)
87 #define CTR_CWG_MASK U(0xf)
88 #define CTR_ERG_SHIFT U(20)
89 #define CTR_ERG_MASK U(0xf)
93 #define CTR_L1IP_SHIFT U(14)
94 #define CTR_L1IP_MASK U(0x3)
[all …]
A Darm64.h44 #define TTBR_ASID_SHIFT U(48)
47 #define CLIDR_LOC_SHIFT U(24)
48 #define CLIDR_FIELD_WIDTH U(3)
59 #define DAIF_F_SHIFT U(6)
116 #define TCR_T0SZ_SHIFT U(0)
147 #define TCR_SHX_NSH U(0x0)
149 #define TCR_SHX_OSH U(0x2)
151 #define TCR_SHX_ISH U(0x3)
153 #define ESR_EC_SHIFT U(26)
157 #define ESR_EC_WFI U(0x01)
[all …]
A Dffa.h28 #define FFA_VERSION_MAJOR U(1)
31 #define FFA_VERSION_MINOR U(0)
32 #define FFA_VERSION_MINOR_SHIFT U(0)
39 #define FFA_ERROR U(0x84000060)
43 #define FFA_VERSION U(0x84000063)
50 #define FFA_ID_GET U(0x84000069)
53 #define FFA_MSG_RUN U(0x8400006D)
107 #define FFA_MEM_PERM_RW U(0x1)
108 #define FFA_MEM_PERM_RO U(0x3)
112 #define FFA_MEM_PERM_X U(0)
[all …]
A Darm32.h101 #define PAR_PA_SHIFT U(12)
117 #define TTBCR_T0SZ_SHIFT U(0)
119 #define TTBCR_IRGN0_SHIFT U(8)
121 #define TTBCR_SH0_SHIFT U(12)
122 #define TTBCR_T1SZ_SHIFT U(16)
127 #define TTBCR_SH1_SHIFT U(28)
130 #define TTBCR_XRGNX_NC U(0x0)
139 #define TTBCR_SHX_NSH U(0x0)
141 #define TTBCR_SHX_OSH U(0x2)
143 #define TTBCR_SHX_ISH U(0x3)
[all …]
A Doptee_ffa.h34 #define OPTEE_FFA_YIELDING_CALL_BIT U(31)
160 #define OPTEE_FFA_YIELDING_CALL_RETURN_DONE U(0)
161 #define OPTEE_FFA_YIELDING_CALL_RETURN_RPC_CMD U(1)
162 #define OPTEE_FFA_YIELDING_CALL_RETURN_INTERRUPT U(2)
/optee_os-3.20.0/core/arch/arm/include/sm/
A Dpsci.h5 #define PSCI_VERSION_0_2 U(0x00000002)
6 #define PSCI_VERSION_1_0 U(0x00010000)
7 #define PSCI_VERSION_1_1 U(0x00010001)
8 #define PSCI_VERSION U(0x84000000)
9 #define PSCI_CPU_SUSPEND U(0x84000001)
10 #define PSCI_CPU_OFF U(0x84000002)
11 #define PSCI_CPU_ON U(0x84000003)
14 #define PSCI_MIGRATE U(0x84000005)
17 #define PSCI_SYSTEM_OFF U(0x84000008)
31 #define PSCI_NUM_CALLS U(21)
[all …]
A Doptee_smc.h20 #define OPTEE_SMC_32 U(0)
21 #define OPTEE_SMC_64 U(0x40000000)
23 #define OPTEE_SMC_STD_CALL U(0)
25 #define OPTEE_SMC_OWNER_MASK U(0x3F)
26 #define OPTEE_SMC_OWNER_SHIFT U(24)
28 #define OPTEE_SMC_FUNC_MASK U(0xFFFF)
49 #define OPTEE_SMC_OWNER_ARCH U(0)
50 #define OPTEE_SMC_OWNER_CPU U(1)
51 #define OPTEE_SMC_OWNER_SIP U(2)
52 #define OPTEE_SMC_OWNER_OEM U(3)
[all …]
/optee_os-3.20.0/core/arch/riscv/include/mm/
A Dcore_mmu_arch.h32 #define RISCV_MMU_MODE U(39)
34 #define RISCV_MMU_MODE U(32)
42 #define RISCV_SATP_ASID_SIZE U(16)
44 #define RISCV_MMU_PA_WIDTH U(56)
45 #define RISCV_MMU_VA_WIDTH U(48)
51 #define RISCV_MMU_PA_WIDTH U(56)
52 #define RISCV_MMU_VA_WIDTH U(39)
58 #define RISCV_SATP_ASID_SIZE U(9)
60 #define RISCV_MMU_PA_WIDTH U(32)
61 #define RISCV_MMU_VA_WIDTH U(32)
[all …]
/optee_os-3.20.0/core/drivers/
A Dstm32_bsec.c33 #define BSEC_OTP_BANK_SHIFT U(5)
40 #define BSEC_OTP_CONF_OFF U(0x000)
45 #define BSEC_DEN_OFF U(0x014)
46 #define BSEC_FEN_OFF U(0x018)
50 #define BSEC_ERROR_OFF U(0x034)
51 #define BSEC_ERROR1_OFF U(0x038)
70 #define BSEC_IPVR_OFF U(0xFF4)
71 #define BSEC_IP_ID_OFF U(0xFF8)
85 #define BSEC_READ U(0x000)
86 #define BSEC_WRITE U(0x100)
[all …]
/optee_os-3.20.0/core/arch/arm/include/mm/
A Dcore_mmu_arch.h43 #define SMALL_PAGE_SHIFT U(12)
46 #define CORE_MMU_PGDIR_SHIFT U(21)
47 #define CORE_MMU_PGDIR_LEVEL U(3)
49 #define CORE_MMU_PGDIR_SHIFT U(20)
50 #define CORE_MMU_PGDIR_LEVEL U(2)
62 #define CORE_MMU_BASE_TABLE_SHIFT U(30)
63 #define CORE_MMU_BASE_TABLE_LEVEL U(1)
65 #define CORE_MMU_BASE_TABLE_SHIFT U(39)
66 #define CORE_MMU_BASE_TABLE_LEVEL U(0)
81 U(8))
[all …]
/optee_os-3.20.0/core/arch/arm/plat-stm32mp1/
A Dplatform_config.h114 #define CFG0_OTP_CLOSED_DEVICE U(0x3F)
121 #define HW2_OTP_IWDG_HW_ENABLE_SHIFT U(3)
122 #define HW2_OTP_IWDG_FZ_STOP_SHIFT U(5)
123 #define HW2_OTP_IWDG_FZ_STANDBY_SHIFT U(7)
152 #define GPIO_BANK_A 0U
167 #define TAMP_BKP_REGISTER_COUNT U(32)
169 #define TAMP_BKP_REGISTER_ZONE1_COUNT U(10)
170 #define TAMP_BKP_REGISTER_ZONE2_COUNT U(5)
171 #define TAMP_BKP_REGISTER_ZONE3_COUNT U(17)
/optee_os-3.20.0/core/arch/riscv/include/
A Dsbi.h27 #define SBI_EXT_HSM_HART_START U(0)
28 #define SBI_EXT_HSM_HART_STOP U(1)
29 #define SBI_EXT_HSM_HART_GET_STATUS U(2)
30 #define SBI_EXT_HSM_HART_SUSPEND U(3)
/optee_os-3.20.0/core/include/mm/
A Dtee_mmu_types.h34 #define TEE_MATTR_MEM_TYPE_MASK U(0x7)
35 #define TEE_MATTR_MEM_TYPE_SHIFT U(12)
48 #define TEE_MATTR_MEM_TYPE_DEV U(0) /* Device-nGnRE */
49 #define TEE_MATTR_MEM_TYPE_CACHED U(1)
50 #define TEE_MATTR_MEM_TYPE_STRONGLY_O U(2) /* Device-nGnRnE */
51 #define TEE_MATTR_MEM_TYPE_TAGGED U(3)

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