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/optee_os-3.20.0/core/include/drivers/
A Dzynqmp_pm.h29 #define ZYNQMP_EFUSE_LEN(_id) ZYNQMP_EFUSE_##_id##_LENGTH argument
32 #define ZYNQMP_EFUSE_MEM(_id) (ROUNDUP(ZYNQMP_EFUSE_LEN(_id), CACHELINE_LEN)) argument
/optee_os-3.20.0/core/drivers/crypto/crypto_api/include/
A Ddrvcrypt_asn1_oid.h129 #define DRVCRYPT_OID_LEN(_id) (sizeof(_id) - 1) argument
/optee_os-3.20.0/ta/pkcs11/src/
A Dpkcs11_helpers.c28 #define PKCS11_ID_SZ(_id, _sz) \ argument
29 { .id = (uint32_t)(_id), .size = (_sz), .string = #_id }
31 #define PKCS11_ID_SZ(_id, _sz) \ argument
32 { .id = (uint32_t)(_id), .size = (_sz) }
115 #define PKCS11_ID(_id) { .id = _id, .string = #_id } argument
117 #define PKCS11_ID(_id) { .id = _id } argument
/optee_os-3.20.0/core/drivers/
A Dversal_puf.c20 #define PUF_API_ID(_id) ((VERSAL_PUF_MODULE << VERSAL_PUF_MODULE_SHIFT) | (_id)) argument
A Dversal_nvm.c24 #define NVM_API_ID(_id) ((NVM_MODULE << NVM_MODULE_SHIFT) | (_id)) argument
/optee_os-3.20.0/core/arch/arm/plat-stm32mp1/
A Dscmi_server.c86 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ argument
88 .clock_id = (_id), \
93 #define RESET_CELL(_scmi_id, _id, _name) \ argument
95 .reset_id = (_id), \
/optee_os-3.20.0/core/drivers/clk/
A Dclk-stm32mp13.c270 #define GATE_CFG(_id, _offset, _bit_idx, _offset_clr)\ argument
271 [(_id)] = {\
444 #define MUXRDY_CFG(_id, _offset, _shift, _witdh, _rdy)\ argument
445 [(_id)] = {\
452 #define MUX_CFG(_id, _offset, _shift, _witdh)\ argument
453 MUXRDY_CFG(_id, _offset, _shift, _witdh, MUX_NO_RDY)
527 #define DIVRDY_CFG(_id, _offset, _shift, _width, _flags, _table, _ready)\ argument
528 [(_id)] = {\
537 #define DIV_CFG(_id, _offset, _shift, _width, _flags, _table)\ argument
538 DIVRDY_CFG(_id, _offset, _shift, _width, _flags, _table, DIV_NO_RDY)

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