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/optee_os-3.20.0/core/drivers/clk/
A Dclk-stm32-core.h173 #define STM32_FIXED_FACTOR(_name, _parent, _flags, _mult, _div)\ argument
183 .parents = { (_parent) },\
186 #define STM32_GATE(_name, _parent, _flags, _gate_id)\ argument
195 .parents = { (_parent) },\
198 #define STM32_DIVIDER(_name, _parent, _flags, _div_id)\ argument
207 .parents = { (_parent) },\
222 #define STM32_GATE_READY(_name, _parent, _flags, _gate_id)\ argument
231 .parents = { _parent },\
A Dclk-stm32mp15.c257 #define _CLK_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ argument
265 .fixed = (_parent), \
281 #define _CLK_SC_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ argument
289 .fixed = (_parent), \
306 #define _CLK_SC2_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ argument
314 .fixed = (_parent), \
317 #define _CLK_PARENT(idx, _offset, _src, _mask, _parent) \ argument
322 .parent = (_parent), \
323 .nb_parent = ARRAY_SIZE(_parent) \
A Dclk-stm32mp13.c1915 #define STM32_TIMER(_name, _parent, _flags, _apbdiv, _timpre)\ argument
1925 .parents = { _parent },\

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