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Searched refs:base (Results 1 – 25 of 175) sorted by relevance

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/optee_os-3.20.0/core/drivers/
A Dtzc400.c73 vaddr_t base; member
218 assert(base); in tzc_init()
219 tzc.base = base; in tzc_init()
267 assert(tzc.base && cfg); in tzc_configure_region()
291 tzc_write_region_base_low(tzc.base, region, addr_low(cfg->base)); in tzc_configure_region()
292 tzc_write_region_base_high(tzc.base, region, addr_high(cfg->base)); in tzc_configure_region()
316 cfg->base = reg_pair_to_64(tzc_read_region_base_high(tzc.base, region), in tzc_get_region_config()
332 assert(tzc.base); in tzc_set_action()
348 assert(tzc.base); in tzc_enable_filters()
375 assert(tzc.base); in tzc_disable_filters()
[all …]
A Dtzc380.c48 vaddr_t base; member
93 void tzc_init(vaddr_t base) in tzc_init() argument
97 assert(base); in tzc_init()
98 tzc.base = base; in tzc_init()
141 vaddr_t base __maybe_unused = core_mmu_get_va(tzc.base, in tzc_fail_dump()
155 vaddr_t base = core_mmu_get_va(tzc.base, MEM_AREA_IO_SEC, in tzc_int_clear() local
158 io_write32(base + INT_CLEAR, 0); in tzc_int_clear()
182 assert(tzc.base); in tzc_configure_region()
204 assert(tzc.base); in tzc_set_action()
216 assert(tzc.base); in tzc_get_action()
[all …]
A Dhi16xx_uart.c71 vaddr_t base = chip_to_base(chip); in hi16xx_uart_flush() local
79 vaddr_t base = chip_to_base(chip); in hi16xx_uart_putc() local
86 io_write32(base + UART_THR, ch & 0xFF); in hi16xx_uart_putc()
91 vaddr_t base = chip_to_base(chip); in hi16xx_uart_have_rx_data() local
98 vaddr_t base = chip_to_base(chip); in hi16xx_uart_getchar() local
102 return io_read32(base + UART_RBR) & 0xFF; in hi16xx_uart_getchar()
118 pd->base.pa = base; in hi16xx_uart_init()
125 io_write32(base + UART_LCR, UART_LCR_DLAB); in hi16xx_uart_init()
128 io_write32(base + UART_DLL, freq_div & 0xFF); in hi16xx_uart_init()
134 io_write32(base + UART_LCR, UART_LCR_DLS8); in hi16xx_uart_init()
[all …]
A Dmvebu_uart.c67 vaddr_t base = chip_to_base(chip); in mvebu_uart_flush() local
82 vaddr_t base = chip_to_base(chip); in mvebu_uart_have_rx_data() local
89 vaddr_t base = chip_to_base(chip); in mvebu_uart_getchar() local
98 vaddr_t base = chip_to_base(chip); in mvebu_uart_putc() local
107 io_write32(base + UART_TX_REG, ch); in mvebu_uart_putc()
121 vaddr_t base; in mvebu_uart_init() local
124 pd->base.pa = pbase; in mvebu_uart_init()
127 base = io_pa_or_va(&pd->base, UART_SIZE); in mvebu_uart_init()
135 io_write32(base + UART_POSSR_REG, 0); in mvebu_uart_init()
138 io_write32(base + UART_CTRL_REG, in mvebu_uart_init()
[all …]
A Damlogic_uart.c30 return io_pa_or_va(&pd->base, AML_UART_SIZE); in chip_to_base()
35 vaddr_t base = chip_to_base(chip); in amlogic_uart_flush() local
37 while (!(io_read32(base + AML_UART_STATUS) & AML_UART_TX_EMPTY)) in amlogic_uart_flush()
43 vaddr_t base = chip_to_base(chip); in amlogic_uart_getchar() local
45 if (io_read32(base + AML_UART_STATUS) & AML_UART_RX_EMPTY) in amlogic_uart_getchar()
48 return io_read32(base + AML_UART_RFIFO) & 0xff; in amlogic_uart_getchar()
53 vaddr_t base = chip_to_base(chip); in amlogic_uart_putc() local
55 while (io_read32(base + AML_UART_STATUS) & AML_UART_TX_FULL) in amlogic_uart_putc()
58 io_write32(base + AML_UART_WFIFO, ch); in amlogic_uart_putc()
67 void amlogic_uart_init(struct amlogic_uart_data *pd, paddr_t base) in amlogic_uart_init() argument
[all …]
A Dscif.c53 return io_pa_or_va(&pd->base, SCIF_REG_SIZE); in chip_to_base()
58 vaddr_t base = chip_to_base(chip); in scif_uart_flush() local
60 while (!(io_read16(base + SCIF_SCFSR) & SCFSR_TEND)) in scif_uart_flush()
66 vaddr_t base = chip_to_base(chip); in scif_uart_putc() local
69 while ((io_read16(base + SCIF_SCFDR) >> SCFDR_T_SHIFT) >= in scif_uart_putc()
72 io_write8(base + SCIF_SCFTDR, ch); in scif_uart_putc()
73 io_clrbits16(base + SCIF_SCFSR, SCFSR_TEND | SCFSR_TDFE); in scif_uart_putc()
84 vaddr_t base; in scif_uart_init() local
86 pd->base.pa = pbase; in scif_uart_init()
89 base = io_pa_or_va(&pd->base, SCIF_REG_SIZE); in scif_uart_init()
[all …]
A Dsprd_uart.c49 return io_pa_or_va(&pd->base, UART_SIZE); in chip_to_base()
54 vaddr_t base = chip_to_base(chip); in sprd_uart_flush() local
56 while (io_read32(base + UART_STS1) & STS1_TXF_CNT_MASK) in sprd_uart_flush()
62 vaddr_t base = chip_to_base(chip); in sprd_uart_have_rx_data() local
64 return !!(io_read32(base + UART_STS1) & STS1_RXF_CNT_MASK); in sprd_uart_have_rx_data()
69 vaddr_t base = chip_to_base(chip); in sprd_uart_putc() local
72 io_write32(base + UART_TXD, ch); in sprd_uart_putc()
77 vaddr_t base = chip_to_base(chip); in sprd_uart_getchar() local
82 return io_read32(base + UART_RXD) & 0xff; in sprd_uart_getchar()
93 void sprd_uart_init(struct sprd_uart_data *pd, paddr_t base) in sprd_uart_init() argument
[all …]
A Datmel_uart.c58 return io_pa_or_va(&pd->base, ATMEL_UART_SIZE); in chip_to_base()
63 vaddr_t base = chip_to_base(chip); in atmel_uart_flush() local
65 while (!(io_read32(base + ATMEL_UART_SR) & ATMEL_SR_TXEMPTY)) in atmel_uart_flush()
71 vaddr_t base = chip_to_base(chip); in atmel_uart_getchar() local
73 while (io_read32(base + ATMEL_UART_SR) & ATMEL_SR_RXRDY) in atmel_uart_getchar()
76 return io_read32(base + ATMEL_UART_RHR); in atmel_uart_getchar()
81 vaddr_t base = chip_to_base(chip); in atmel_uart_putc() local
83 while (!(io_read32(base + ATMEL_UART_SR) & ATMEL_SR_TXRDY)) in atmel_uart_putc()
86 io_write32(base + ATMEL_UART_THR, ch); in atmel_uart_putc()
95 void atmel_uart_init(struct atmel_uart_data *pd, paddr_t base) in atmel_uart_init() argument
[all …]
A Dcdns_uart.c64 return io_pa_or_va(&pd->base, CDNS_UART_SIZE); in chip_to_base()
69 vaddr_t base = chip_to_base(chip); in cdns_uart_flush() local
71 while (!(io_read32(base + CDNS_UART_CHANNEL_STATUS) & in cdns_uart_flush()
78 vaddr_t base = chip_to_base(chip); in cdns_uart_have_rx_data() local
86 vaddr_t base = chip_to_base(chip); in cdns_uart_getchar() local
90 return io_read32(base + CDNS_UART_FIFO) & 0xff; in cdns_uart_getchar()
95 vaddr_t base = chip_to_base(chip); in cdns_uart_putc() local
98 while (io_read32(base + CDNS_UART_CHANNEL_STATUS) & in cdns_uart_putc()
103 io_write32(base + CDNS_UART_FIFO, ch); in cdns_uart_putc()
122 pd->base.pa = base; in cdns_uart_init()
[all …]
A Dpl011.c87 vaddr_t base = chip_to_base(chip); in pl011_flush() local
103 vaddr_t base = chip_to_base(chip); in pl011_have_rx_data() local
110 vaddr_t base = chip_to_base(chip); in pl011_getchar() local
114 return io_read32(base + UART_DR) & 0xff; in pl011_getchar()
119 vaddr_t base = chip_to_base(chip); in pl011_putc() local
126 io_write32(base + UART_DR, ch); in pl011_putc()
140 vaddr_t base; in pl011_init() local
142 pd->base.pa = pbase; in pl011_init()
145 base = io_pa_or_va(&pd->base, PL011_REG_SIZE); in pl011_init()
148 io_write32(base + UART_RSR_ECR, 0); in pl011_init()
[all …]
A Dstih_asc.c22 return io_pa_or_va(&pd->base, STIH_ASC_REG_SIZE); in chip_to_base()
27 vaddr_t base = chip_to_base(chip); in stih_asc_flush() local
29 while (!(io_read32(base + ASC_STATUS) & ASC_STATUS_TX_EMPTY)) in stih_asc_flush()
35 vaddr_t base = chip_to_base(chip); in stih_asc_putc() local
37 while (!(io_read32(base + ASC_STATUS) & ASC_STATUS_TX_HALF_EMPTY)) in stih_asc_putc()
40 io_write32(base + ASC_TXBUFFER, ch); in stih_asc_putc()
49 void stih_asc_init(struct stih_asc_pd *pd, vaddr_t base) in stih_asc_init() argument
51 pd->base.pa = base; in stih_asc_init()
A Dsp805_wdt.c20 return io_pa_or_va(&pd->base, WDT_SIZE); in chip_to_base()
50 vaddr_t base = chip_to_base(chip); in sp805_config() local
53 io_write32(base + WDT_LOAD_OFFSET, pd->load_val); in sp805_config()
57 io_write32(base + WDT_CONTROL_OFFSET, in sp805_config()
60 io_write32(base + WDT_LOCK_OFFSET, WDT_LOCK_KEY); in sp805_config()
63 (void)io_read32(base + WDT_LOCK_OFFSET); in sp805_config()
78 vaddr_t base = chip_to_base(chip); in sp805_disable() local
81 io_write32(base + WDT_CONTROL_OFFSET, 0); in sp805_disable()
82 io_write32(base + WDT_LOCK_OFFSET, WDT_LOCK_KEY); in sp805_disable()
85 (void)io_read32(base + WDT_LOCK_OFFSET); in sp805_disable()
[all …]
A Dimx_snvs.c67 hp_mks = io_read32(base + SNVS_HPCOMR); in is_otpmk_selected()
74 uint32_t lp_mks = io_read32(base + SNVS_LPMKCR); in is_otpmk_selected()
90 return io_read32(base + SNVS_HPLR) & SNVS_HPLR_MKS_SL || in is_mks_locked()
91 io_read32(base + SNVS_LPLR) & SNVS_LPLR_MKS_HL; in is_mks_locked()
99 io_setbits32(base + SNVS_HPCOMR, SNVS_HPCOMR_MKS_EN); in set_mks_otpmk()
100 io_clrbits32(base + SNVS_LPMKCR, SNVS_LPMKCR_MKCR_MKS_SEL); in set_mks_otpmk()
101 io_clrbits32(base + SNVS_HPLR, SNVS_HPLR_MKS_SL); in set_mks_otpmk()
102 io_setbits32(base + SNVS_LPLR, SNVS_LPLR_MKS_HL); in set_mks_otpmk()
111 uint32_t status = io_read32(base + SNVS_HPSR); in is_otpmk_valid()
119 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, in snvs_get_security_cfg() local
[all …]
A Dstm32_tamp.c109 struct io_pa_va base; member
140 vaddr_t base = 0; in stm32_tamp_set_secure_bkpregs() local
150 base = io_pa_or_va(&tamp->base, 1); in stm32_tamp_set_secure_bkpregs()
160 io_clrsetbits32(base + _TAMP_SECCFGR, in stm32_tamp_set_secure_bkpregs()
170 io_clrsetbits32(base + _TAMP_SMCR, in stm32_tamp_set_secure_bkpregs()
175 io_clrsetbits32(base + _TAMP_SMCR, in stm32_tamp_set_secure_bkpregs()
187 vaddr_t base = io_pa_or_va(&tamp->base, 1); in stm32_tamp_set_secure() local
208 vaddr_t base = io_pa_or_va(&tamp->base, 1); in stm32_tamp_set_privilege() local
229 tamp->base.pa = dt_tamp.reg; in stm32_tamp_parse_fdt()
241 vaddr_t base = 0; in stm32_tamp_probe() local
[all …]
A Dimx_lpuart.c25 return io_pa_or_va(&pd->base, UART_SIZE); in chip_to_base()
31 vaddr_t base = chip_to_base(chip); in imx_lpuart_getchar() local
33 while (io_read32(base + STAT) & STAT_RDRF) in imx_lpuart_getchar()
36 ch = io_read32(base + DATA) & 0x3ff; in imx_lpuart_getchar()
38 if (io_read32(base + STAT) & STAT_OR) in imx_lpuart_getchar()
39 io_write32(base + STAT, STAT_OR); in imx_lpuart_getchar()
46 vaddr_t base = chip_to_base(chip); in imx_lpuart_putc() local
48 while (!(io_read32(base + STAT) & STAT_TDRE)) in imx_lpuart_putc()
51 io_write32(base + DATA, ch); in imx_lpuart_putc()
60 void imx_uart_init(struct imx_uart_data *pd, paddr_t base) in imx_uart_init() argument
[all …]
A Dstm32_uart.c54 return io_pa_or_va(&pd->base, 1); in loc_chip_to_base()
59 vaddr_t base = loc_chip_to_base(chip); in loc_flush() local
69 vaddr_t base = loc_chip_to_base(chip); in loc_putc() local
76 io_write32(base + UART_REG_TDR, ch); in loc_putc()
81 vaddr_t base = loc_chip_to_base(chip); in loc_have_rx_data() local
88 vaddr_t base = loc_chip_to_base(chip); in loc_getchar() local
93 return io_read32(base + UART_REG_RDR) & 0xff; in loc_getchar()
107 pd->base.pa = base; in stm32_uart_init()
116 stm32mp_register_secure_periph_iomem(pd->base.pa); in register_secure_uart()
153 pd->base.pa = info.reg; in stm32_uart_init_from_dt_node()
[all …]
A Dimx_uart.c91 return io_pa_or_va(&pd->base, USIZE); in chip_to_base()
96 vaddr_t base = chip_to_base(chip); in imx_uart_flush() local
99 while (!(io_read32(base + UTS) & UTS_TXEMPTY)) in imx_uart_flush()
100 if (!(io_read32(base + UCR1) & UCR1_UARTEN)) in imx_uart_flush()
106 vaddr_t base = chip_to_base(chip); in imx_uart_getchar() local
108 while (io_read32(base + UTS) & UTS_RXEMPTY) in imx_uart_getchar()
116 vaddr_t base = chip_to_base(chip); in imx_uart_putc() local
119 while (io_read32(base + UTS) & UTS_TXFULL) in imx_uart_putc()
120 if (!(io_read32(base + UCR1) & UCR1_UARTEN)) in imx_uart_putc()
123 io_write32(base + UTXD, ch); in imx_uart_putc()
[all …]
A Dns16550.c52 vaddr_t base = io_pa_or_va(&pd->base, in ns16550_flush() local
55 while ((serial_in(base + (UART_LSR << pd->reg_shift), pd->io_width) & in ns16550_flush()
64 vaddr_t base = io_pa_or_va(&pd->base, (UART_THR << pd->reg_shift) + in ns16550_putc() local
70 serial_out(base + (UART_THR << pd->reg_shift), pd->io_width, ch); in ns16550_putc()
79 void ns16550_init(struct ns16550_data *pd, paddr_t base, uint8_t io_width, in ns16550_init() argument
82 pd->base.pa = base; in ns16550_init()
A Dimx_rngb.c64 struct io_pa_va base; member
69 .base.pa = RNGB_BASE,
80 status = io_read32(rng->base.va + RNG_SR); in wait_for_irq()
90 io_setbits32(rng->base.va + RNG_CR, in irq_clear()
92 io_setbits32(rng->base.va + RNG_CMD, in irq_clear()
98 io_clrbits32(rng->base.va + RNG_CR, in irq_unmask()
122 rngb.base.pa, rngb.size); in map_controller_static()
123 if (!rngb.base.va) in map_controller_static()
163 rngb.base.pa = virt_to_phys((void *)rngb.base.va); in map_controller()
179 status = io_read32(rngb.base.va + RNG_SR); in hw_get_random_bytes()
[all …]
/optee_os-3.20.0/core/arch/arm/plat-bcm/
A Dbcm_elog.c15 vaddr_t base = 0; in bcm_elog_putchar() local
17 base = io_pa_or_va(&elog->base, elog->max_size); in bcm_elog_putchar()
19 offset = io_read32(base + BCM_ELOG_OFF_OFFSET); in bcm_elog_putchar()
20 len = io_read32(base + BCM_ELOG_LEN_OFFSET); in bcm_elog_putchar()
21 io_write8(base + offset, ch); in bcm_elog_putchar()
33 io_write32(base + BCM_ELOG_LEN_OFFSET, len); in bcm_elog_putchar()
40 vaddr_t base = 0; in bcm_elog_init() local
42 elog->base.pa = pa_base; in bcm_elog_init()
45 base = io_pa_or_va(&elog->base, BCM_ELOG_HEADER_LEN); in bcm_elog_init()
52 val = io_read32(base + BCM_ELOG_SIG_OFFSET); in bcm_elog_init()
[all …]
/optee_os-3.20.0/lib/libutils/isoc/newlib/
A Dstrtoul.c158 _DEFUN (_strtoul, (nptr, endptr, base),
161 int base)
180 if ((base == 0 || base == 16) &&
184 base = 16;
186 if (base == 0)
187 base = c == '0' ? 8 : 10;
197 if (c >= base)
203 acc *= base;
219 _DEFUN (strtoul, (s, ptr, base),
222 int base)
[all …]
/optee_os-3.20.0/core/drivers/imx/mu/
A Dimx_mu.c18 __weak void imx_mu_plat_init(vaddr_t base __unused) in imx_mu_plat_init()
50 assert(base && msg); in imx_mu_receive_msg()
53 res = imx_mu_plat_receive(base, 0, &response); in imx_mu_receive_msg()
94 assert(base && msg); in imx_mu_send_msg()
102 res = imx_mu_plat_send(base, 0, word); in imx_mu_send_msg()
118 void imx_mu_init(vaddr_t base) in imx_mu_init() argument
122 if (!base) { in imx_mu_init()
129 imx_mu_plat_init(base); in imx_mu_init()
140 if (!base || !msg) in imx_mu_call()
145 res = imx_mu_send_msg(base, msg); in imx_mu_call()
[all …]
A Dimx_mu_8ulp.c50 TEE_Result imx_mu_plat_send(vaddr_t base, unsigned int index, uint32_t msg) in imx_mu_plat_send() argument
55 if (mu_wait_for(base + MU_TSR, MU_TSR_TE(index))) in imx_mu_plat_send()
58 io_write32(base + MU_TR(index), msg); in imx_mu_plat_send()
63 TEE_Result imx_mu_plat_receive(vaddr_t base, unsigned int index, uint32_t *msg) in imx_mu_plat_receive() argument
68 if (mu_wait_for(base + MU_RSR, MU_RSR_RF(index))) in imx_mu_plat_receive()
71 *msg = io_read32(base + MU_RR(index)); in imx_mu_plat_receive()
76 void imx_mu_plat_init(vaddr_t base) in imx_mu_plat_init() argument
79 io_write32(base + MU_TCR, 0x0); in imx_mu_plat_init()
80 io_write32(base + MU_RCR, 0x0); in imx_mu_plat_init()
/optee_os-3.20.0/core/drivers/clk/sam/
A Dat91_main.c34 vaddr_t base; member
51 io_clrsetbits32(osc->base + AT91_CKGR_MOR, in pmc_main_rc_osc_enable()
70 io_clrsetbits32(osc->base + AT91_CKGR_MOR, in pmc_main_rc_osc_disable()
105 osc->base = pmc->base; in pmc_register_main_rc_osc()
140 io_write32(pmc->base + AT91_CKGR_MOR, mor); in pmc_main_osc_enable()
181 io_clrsetbits32(pmc->base + AT91_CKGR_MOR, in pmc_register_main_osc()
213 mcfr = io_read32(base + AT91_CKGR_MCFR); in clk_main_get_rate()
231 while (!clk_sam9x5_main_ready(pmc->base)) in clk_sam9x5_main_enable()
234 return clk_main_probe_frequency(pmc->base); in clk_sam9x5_main_enable()
262 io_clrsetbits32(pmc->base + AT91_CKGR_MOR, in clk_sam9x5_main_set_parent()
[all …]
/optee_os-3.20.0/core/arch/arm/plat-stm32mp1/
A Dplat_tzc400.c43 static bool tzc_region_is_non_secure(unsigned int i, vaddr_t base, size_t size) in tzc_region_is_non_secure() argument
52 return region_cfg.base == base && region_cfg.top == (base + size - 1) && in tzc_region_is_non_secure()
58 static bool tzc_region_is_secure(unsigned int i, vaddr_t base, size_t size) in tzc_region_is_secure() argument
66 return region_cfg.base == base && region_cfg.top == (base + size - 1) && in tzc_region_is_secure()
74 void *base = phys_to_virt(TZC_BASE, MEM_AREA_IO_SEC, 1); in init_stm32mp1_tzc() local
82 assert(base); in init_stm32mp1_tzc()
84 tzc_init((vaddr_t)base); in init_stm32mp1_tzc()

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