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Searched refs:baseaddr (Results 1 – 19 of 19) sorted by relevance

/optee_os-3.20.0/core/drivers/crypto/caam/hal/common/
A Dhal_jr.c86 io_caam_write32(baseaddr + JRX_IRSR, nbjobs); in caam_hal_jr_config()
99 caam_hal_jr_disable_itr(baseaddr); in caam_hal_jr_config()
121 return io_caam_read32(baseaddr + JRX_IRSAR); in caam_hal_jr_read_nbslot_available()
124 void caam_hal_jr_add_newjob(vaddr_t baseaddr) in caam_hal_jr_add_newjob() argument
126 io_caam_write32(baseaddr + JRX_IRJAR, 1); in caam_hal_jr_add_newjob()
134 void caam_hal_jr_del_job(vaddr_t baseaddr) in caam_hal_jr_del_job() argument
136 io_caam_write32(baseaddr + JRX_ORJRR, 1); in caam_hal_jr_del_job()
183 val = io_caam_read32(baseaddr + JRX_IRSR); in caam_hal_jr_halt()
213 val = io_caam_read32(baseaddr + JRX_IRSR); in caam_hal_jr_flush()
231 void caam_hal_jr_resume(vaddr_t baseaddr) in caam_hal_jr_resume() argument
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A Dhal_rng.c22 if (caam_hal_ctrl_era(baseaddr) < 10) { in caam_hal_rng_instantiated()
23 vid = io_caam_read32(baseaddr + CHAVID_LS); in caam_hal_rng_instantiated()
35 nb_sh = caam_hal_rng_get_nb_sh(baseaddr); in caam_hal_rng_instantiated()
50 reg = io_caam_read32(baseaddr + CTPR_MS); in caam_hal_rng_get_nb_sh()
110 io_caam_write32(baseaddr + TRNG_RTSCMISC, in caam_hal_rng_kick()
114 io_caam_write32(baseaddr + TRNG_RTSCML, in caam_hal_rng_kick()
116 io_caam_write32(baseaddr + TRNG_RTSCR1L, in caam_hal_rng_kick()
118 io_caam_write32(baseaddr + TRNG_RTSCR2L, in caam_hal_rng_kick()
120 io_caam_write32(baseaddr + TRNG_RTSCR3L, in caam_hal_rng_kick()
122 io_caam_write32(baseaddr + TRNG_RTSCR4L, in caam_hal_rng_kick()
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A Dhal_ctrl.c16 uint8_t caam_hal_ctrl_era(vaddr_t baseaddr) in caam_hal_ctrl_era() argument
24 uint8_t caam_hal_ctrl_jrnum(vaddr_t baseaddr) in caam_hal_ctrl_jrnum() argument
29 if (caam_hal_ctrl_era(baseaddr) < 10) { in caam_hal_ctrl_jrnum()
30 val = io_caam_read32(baseaddr + CHANUM_MS); in caam_hal_ctrl_jrnum()
44 if (caam_hal_ctrl_era(baseaddr) < 10) { in caam_hal_ctrl_hash_limit()
46 val = io_caam_read32(baseaddr + CHANUM_LS); in caam_hal_ctrl_hash_limit()
86 if (caam_hal_ctrl_era(baseaddr) < 10) { in caam_hal_ctrl_pknum()
107 val = io_caam_read32(baseaddr + SCFGR); in caam_hal_ctrl_inc_priblob()
120 val = io_caam_read32(baseaddr + SCFGR); in caam_hal_ctrl_inc_priblob()
122 io_caam_write32(baseaddr + SCFGR, val); in caam_hal_ctrl_inc_priblob()
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/optee_os-3.20.0/core/drivers/crypto/caam/include/
A Dcaam_hal_jr.h29 enum caam_status caam_hal_jr_reset(vaddr_t baseaddr);
54 void caam_hal_jr_add_newjob(vaddr_t baseaddr);
61 uint32_t caam_hal_jr_get_nbjob_done(vaddr_t baseaddr);
68 void caam_hal_jr_del_job(vaddr_t baseaddr);
75 void caam_hal_jr_disable_itr(vaddr_t baseaddr);
82 void caam_hal_jr_enable_itr(vaddr_t baseaddr);
89 bool caam_hal_jr_check_ack_itr(vaddr_t baseaddr);
97 enum caam_status caam_hal_jr_halt(vaddr_t baseaddr);
111 void caam_hal_jr_resume(vaddr_t baseaddr);
119 uint8_t caam_hal_jr_input_index(vaddr_t baseaddr);
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A Dcaam_hal_ctrl.h17 void caam_hal_ctrl_init(vaddr_t baseaddr);
24 uint8_t caam_hal_ctrl_jrnum(vaddr_t baseaddr);
32 uint8_t caam_hal_ctrl_hash_limit(vaddr_t baseaddr);
39 uint8_t caam_hal_ctrl_pknum(vaddr_t baseaddr);
46 bool caam_hal_ctrl_splitkey_support(vaddr_t baseaddr);
53 uint8_t caam_hal_ctrl_era(vaddr_t baseaddr);
60 void caam_hal_ctrl_inc_priblob(vaddr_t baseaddr);
A Dcaam_hal_rng.h19 enum caam_status caam_hal_rng_instantiated(vaddr_t baseaddr);
26 uint32_t caam_hal_rng_get_nb_sh(vaddr_t baseaddr);
33 uint32_t caam_hal_rng_get_sh_status(vaddr_t baseaddr);
40 bool caam_hal_rng_key_loaded(vaddr_t baseaddr);
48 enum caam_status caam_hal_rng_kick(vaddr_t baseaddr, uint32_t inc_delay);
A Dcaam_blob.h16 enum caam_status caam_blob_mkvb_init(vaddr_t baseaddr);
18 static inline enum caam_status caam_blob_mkvb_init(vaddr_t baseaddr __unused) in caam_blob_mkvb_init()
A Dcaam_pwr.h34 vaddr_t baseaddr; /* Register virtual base address */ member
49 void caam_pwr_add_backup(vaddr_t baseaddr, const struct reglist *regs,
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_6_7/
A Dhal_ctrl.c26 void caam_hal_ctrl_init(vaddr_t baseaddr) in caam_hal_ctrl_init() argument
29 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
42 io_mask32(baseaddr + MCFGR, MCFGR_AXIPIPE(1), BM_MCFGR_AXIPIPE); in caam_hal_ctrl_init()
44 caam_pwr_add_backup(baseaddr, ctrl_backup, ARRAY_SIZE(ctrl_backup)); in caam_hal_ctrl_init()
/optee_os-3.20.0/core/drivers/crypto/caam/
A Dcaam_jr.c41 vaddr_t baseaddr; /* Job Ring base address */ member
262 caam_hal_jr_del_job(jr_privdata->baseaddr); in do_jr_dequeue()
373 caam_hal_jr_add_newjob(jr_privdata->baseaddr); in do_jr_enqueue()
555 jr_privdata->baseaddr = jrcfg->base + jrcfg->offset; in caam_jr_init()
589 caam_hal_jr_enable_itr(jr_privdata->baseaddr); in caam_jr_init()
605 retstatus = caam_hal_jr_halt(jr_privdata->baseaddr); in caam_jr_halt()
654 caam_hal_jr_input_index(jr_privdata->baseaddr); in caam_jr_resume()
657 caam_hal_jr_output_index(jr_privdata->baseaddr); in caam_jr_resume()
667 caam_hal_jr_resume(jr_privdata->baseaddr); in caam_jr_resume()
675 ret = caam_hal_jr_flush(jr_privdata->baseaddr); in caam_jr_complete()
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A Dcaam_pwr.c19 void caam_pwr_add_backup(vaddr_t baseaddr, const struct reglist *regs, in caam_pwr_add_backup() argument
35 newelem->baseaddr = baseaddr; in caam_pwr_add_backup()
71 io_caam_read32(elem->baseaddr + in do_save_regs()
77 elem->baseaddr + reg->offset + in do_save_regs()
101 elem->baseaddr + reg->offset + in do_restore_regs()
104 io_caam_write32(elem->baseaddr + reg->offset + in do_restore_regs()
A Dcaam_rng.c61 vaddr_t baseaddr; /* RNG base address */ member
370 key_loaded = caam_hal_rng_key_loaded(rng_privdata->baseaddr); in prepare_inst_desc()
435 retstatus = caam_hal_rng_instantiated(rng_privdata->baseaddr); in caam_rng_instantiation()
447 nb_sh = caam_hal_rng_get_nb_sh(rng_privdata->baseaddr); in caam_rng_instantiation()
484 sh_status = caam_hal_rng_get_sh_status(rng_privdata->baseaddr); in caam_rng_instantiation()
494 retstatus = caam_hal_rng_kick(rng_privdata->baseaddr, in caam_rng_instantiation()
543 rng_privdata->baseaddr = ctrl_addr; in caam_rng_init()
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_8m/
A Dhal_ctrl.c12 void caam_hal_ctrl_init(vaddr_t baseaddr) in caam_hal_ctrl_init() argument
15 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_8ulp/
A Dhal_ctrl.c13 void caam_hal_ctrl_init(vaddr_t baseaddr) in caam_hal_ctrl_init() argument
16 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
/optee_os-3.20.0/core/drivers/crypto/caam/hal/ls/
A Dhal_ctrl.c11 void caam_hal_ctrl_init(vaddr_t baseaddr __unused) in caam_hal_ctrl_init()
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_8q/
A Dhal_ctrl.c8 void caam_hal_ctrl_init(vaddr_t baseaddr __unused) in caam_hal_ctrl_init()
A Dhal_rng.c11 enum caam_status caam_hal_rng_instantiated(vaddr_t baseaddr __unused) in caam_hal_rng_instantiated()
/optee_os-3.20.0/core/drivers/crypto/caam/blob/
A Dcaam_blob.c23 enum caam_status caam_blob_mkvb_init(vaddr_t baseaddr) in caam_blob_mkvb_init() argument
68 caam_hal_ctrl_inc_priblob(baseaddr); in caam_blob_mkvb_init()
/optee_os-3.20.0/core/drivers/
A Dbcm_gpio.c163 vaddr_t baseaddr = in iproc_gpio_set_secure() local
169 regaddr = baseaddr + IPROC_GPIO_SEC_CFG_REG(gpiopin); in iproc_gpio_set_secure()

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