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/optee_os-3.20.0/core/arch/arm/kernel/
A Darm32_sysreg.txt38 AMAIR0 c10 0 c3 0 RW Auxiliary Memory Attribute Indirection Register 0
39 AMAIR1 c10 0 c3 1 RW Auxiliary Memory Attribute Indirection Register 1
41 DACR c3 0 c0 0 RW Domain Access Control Register
83 TLBIALLIS c8 0 c3 0 WOD Invalidate entire unified TLB IS
85 TLBIASIDIS c8 0 c3 2 WO Invalidate unified TLB by ASID IS
87 TLBIMVAAIS c8 0 c3 3 WO Invalidate unified TLB by MVA, all ASID IS
89 TLBIMVAIS c8 0 c3 1 WO Invalidate unified TLB by MVA IS
124 CNTV_TVAL c14 0 c3 0 RW Virtual TimerValue register
125 CNTV_CTL c14 0 c3 1 RW Virtual Timer Control register
/optee_os-3.20.0/lib/libutils/ext/include/
A Dfault_mitigation.h200 #define __ftmn_step_count_4(c0, c1, c2, c3) \ argument
201 (__ftmn_step_count_3(c0, c1, c2) + (c3) * FTMN_INCR3)
202 #define __ftmn_step_count_5(c0, c1, c2, c3, c4) \ argument
203 (__ftmn_step_count_4(c0, c1, c2, c3) + (c4) * FTMN_INCR4)
204 #define __ftmn_step_count_6(c0, c1, c2, c3, c4, c5) \ argument
205 (__ftmn_step_count_5(c0, c1, c2, c3, c4) + (c5) * FTMN_INCR5)

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